abstractaccelerator/fpga/xc7z010/design_1/ui/bd_1f5defd0.ui

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1.0 KiB
XML

{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.25",
"Default View_TopLeft":"-969,-462",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS
# -string -flagsOSRD
preplace port DDR -pg 1 -lvl 2 -x 330 -y 60 -defaultsOSRD
preplace port FIXED_IO -pg 1 -lvl 2 -x 330 -y 80 -defaultsOSRD
preplace port UART -pg 1 -lvl 2 -x 330 -y 100 -defaultsOSRD
preplace port port-id_clk_axi -pg 1 -lvl 2 -x 330 -y 140 -defaultsOSRD
preplace port port-id_rstn_axi -pg 1 -lvl 2 -x 330 -y 160 -defaultsOSRD
preplace inst processing_system7_0 -pg 1 -lvl 1 -x 160 -y 110 -defaultsOSRD
preplace netloc processing_system7_0_FCLK_CLK0 1 1 1 N 140
preplace netloc processing_system7_0_FCLK_RESET0_N 1 1 1 N 160
preplace netloc processing_system7_0_DDR 1 1 1 N 60
preplace netloc processing_system7_0_FIXED_IO 1 1 1 N 80
preplace netloc processing_system7_0_UART_0 1 1 1 N 100
levelinfo -pg 1 0 160 330
pagesize -pg 1 -db -bbox -sgen 0 0 450 220
"
}
0