80 lines
1.8 KiB
Verilog
80 lines
1.8 KiB
Verilog
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module ahb_fifo_counter(
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counter_done,
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counter_en,
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counter_load,
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cpu_clk,
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cpu_rst_b
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);
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// &Ports; @20
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input counter_en;
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input [31:0] counter_load;
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input cpu_clk;
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input cpu_rst_b;
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output counter_done;
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// &Regs; @21
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reg [31:0] counter;
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reg counter_en_ff;
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// &Wires; @22
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wire counter_done;
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wire counter_en;
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wire [31:0] counter_load;
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wire cpu_clk;
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wire cpu_rst_b;
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wire load_cnt_en;
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always @(posedge cpu_clk or negedge cpu_rst_b)
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begin
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if(!cpu_rst_b)
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begin
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counter_en_ff <= 1'b0;
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end
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else
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begin
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counter_en_ff <=counter_en ;
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end
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end
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assign load_cnt_en= (counter_en && !counter_en_ff);
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/// || !(|counter[31:0]);
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always @(posedge cpu_clk or negedge cpu_rst_b)
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begin
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if(!cpu_rst_b)
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begin
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counter[31:0] <= 32'h0;
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end
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else if (load_cnt_en)
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begin
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counter[31:0] <= counter_load[31:0];
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end
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else if (counter_done)
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counter[31:0] <= 32'b0;
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else
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counter[31:0] <= counter[31:0] -1'b1;
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end
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assign counter_done = (counter[31:0] == 32'b0) ;
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// &Force("output","counter_done"); @56
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// &ModuleEnd; @57
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endmodule
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