78 lines
2.0 KiB
Verilog
78 lines
2.0 KiB
Verilog
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module smpu_comp_hit(
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biu_pad_haddr,
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biu_pad_hprot,
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smpu_entry,
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smpu_entry0,
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smpu_hit,
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smpu_hsec
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);
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// &Ports; @20
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input [31:0] biu_pad_haddr;
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input [3 :0] biu_pad_hprot;
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input [31:0] smpu_entry;
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input [31:0] smpu_entry0;
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output smpu_hit;
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output smpu_hsec;
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// &Regs; @21
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reg [22:0] addr_mask;
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// &Wires; @22
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wire addr_match;
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wire [31:0] biu_pad_haddr;
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wire [3 :0] biu_pad_hprot;
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wire [31:0] smpu_entry;
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wire [31:0] smpu_entry0;
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wire smpu_hit;
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wire smpu_hsec;
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// &Force("bus", "biu_pad_haddr", 31, 0); @25
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// &Force("bus", "biu_pad_hprot", 3, 0); @26
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assign smpu_hit =1'b0;
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// &Force("nonport", "addr_match"); @32
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assign addr_match = {(smpu_entry[0] & !biu_pad_hprot[2]),
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(addr_mask[22:0] & biu_pad_haddr[31:9])}
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== { 1'b1, smpu_entry[31:9]};
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assign smpu_hsec = {(smpu_entry0[0] & biu_pad_hprot[2]),
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(addr_mask[22:0] & biu_pad_haddr[31:9])}
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== { 1'b1, smpu_entry0[31:9]};
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//Generate the address mask for the addr
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// &CombBeg; @44
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always @( smpu_entry[4:1])
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begin
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case(smpu_entry[4:1])
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4'b0111 : addr_mask[22:0] = 23'h7f_ffff;
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4'b1000 : addr_mask[22:0] = 23'h7f_fffe;
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4'b1001 : addr_mask[22:0] = 23'h7f_fffc;
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default : addr_mask[22:0] = 23'h00_0000;
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endcase
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// &CombEnd; @51
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end
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// &ModuleEnd; @54
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endmodule
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