209 lines
5.1 KiB
Verilog
209 lines
5.1 KiB
Verilog
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// &Depend("cpu_cfig.h") @18
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// &ModuleBeg; @19
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module smpu_top(
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biu_pad_haddr,
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biu_pad_hprot,
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paddr,
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pclk,
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penable,
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prdata,
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presetn,
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psel,
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pwdata,
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pwrite,
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smpu_deny
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);
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// &Ports; @20
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input [31:0] biu_pad_haddr;
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input [3 :0] biu_pad_hprot;
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input [3 :2] paddr;
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input pclk;
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input penable;
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input presetn;
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input psel;
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input [31:0] pwdata;
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input pwrite;
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output [31:0] prdata;
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output smpu_deny;
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// &Regs; @21
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reg [31:0] prdata;
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reg [31:0] smpu_entry0;
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reg [31:0] smpu_entry1;
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reg [31:0] smpu_entry2;
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// &Wires; @22
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wire [31:0] biu_pad_haddr;
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wire [3 :0] biu_pad_hprot;
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wire hsec_0;
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wire hsec_1;
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wire hsec_2;
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wire pad_biu_hsec_pre;
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wire [3 :2] paddr;
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wire pclk;
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wire penable;
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wire presetn;
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wire psel;
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wire [31:0] pwdata;
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wire pwrite;
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wire smpu_deny;
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wire smpu_hit0;
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wire smpu_hit1;
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wire smpu_hit2;
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// &Force("bus","biu_pad_haddr",31,0); @25
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//==========================================================
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// APB PWDATA
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//==========================================================
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always @(posedge pclk or negedge presetn)
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begin
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if(!presetn)
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begin
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smpu_entry0 <= 32'b0;
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smpu_entry1 <= 32'b0;
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smpu_entry2 <= 32'b0;
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end
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else
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begin
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if(psel && pwrite && penable)
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begin
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case(paddr[3:2])
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2'b00:
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begin
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smpu_entry0[31:0] <= pwdata[31:0];
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end
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2'b01:
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begin
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smpu_entry1[31:0] <= pwdata[31:0];
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end
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2'b10:
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begin
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smpu_entry2[31:0] <= pwdata[31:0];
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end
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endcase
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end
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end
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end
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//==========================================================
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// APB PRDATA
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//==========================================================
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always @(posedge pclk)
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begin
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if(psel && !pwrite && !penable)
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begin
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case(paddr[3:2])
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2'b00:
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begin
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prdata[31:0] <= smpu_entry0[31:0];
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end
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2'b01:
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begin
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prdata[31:0] <= smpu_entry1[31:0];
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end
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2'b10:
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begin
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prdata[31:0] <= smpu_entry2[31:0];
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end
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default:
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begin
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prdata[31:0] <= 32'bx;
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end
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endcase
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end
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end
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//&Instance("gated_clk_cell", "x_smpu_gated_clk");
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// //&Connect(.clk_in(forever_cpuclk), @93
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// // .global_en(cp0_yy_clk_en), @94
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// // .module_en(mpu_module_en), @95
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// // .local_en(1'b0), @96
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// // .external_en(1'b0), @97
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// // .clk_out(cpuclk)); @98
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// &Force("output", "smpu_deny") @100
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assign smpu_deny = smpu_hit0 || smpu_hit1 || smpu_hit2;
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// &Instance("smpu_comp_hit", "x_smpu_comp_hit_0"); @103
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smpu_comp_hit x_smpu_comp_hit_0 (
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.biu_pad_haddr (biu_pad_haddr),
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.biu_pad_hprot (biu_pad_hprot),
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.smpu_entry (smpu_entry0 ),
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.smpu_entry0 (smpu_entry0 ),
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.smpu_hit (smpu_hit0 ),
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.smpu_hsec (hsec_0 )
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);
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// &Connect(.smpu_hit (smpu_hit0 ), @104
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// .smpu_entry (smpu_entry0 ), @105
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// .smpu_hsec (hsec_0 ) @106
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// @107
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// ); @108
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// &Instance("smpu_comp_hit", "x_smpu_comp_hit_1"); @110
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smpu_comp_hit x_smpu_comp_hit_1 (
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.biu_pad_haddr (biu_pad_haddr),
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.biu_pad_hprot (biu_pad_hprot),
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.smpu_entry (smpu_entry1 ),
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.smpu_entry0 (smpu_entry0 ),
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.smpu_hit (smpu_hit1 ),
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.smpu_hsec (hsec_1 )
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);
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// &Connect(.smpu_hit (smpu_hit1 ), @111
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// .smpu_entry (smpu_entry1 ), @112
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// .smpu_hsec (hsec_1 ) @113
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// ); @114
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// &Instance("smpu_comp_hit", "x_smpu_comp_hit_2"); @116
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smpu_comp_hit x_smpu_comp_hit_2 (
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.biu_pad_haddr (biu_pad_haddr),
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.biu_pad_hprot (biu_pad_hprot),
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.smpu_entry (smpu_entry2 ),
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.smpu_entry0 (smpu_entry0 ),
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.smpu_hit (smpu_hit2 ),
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.smpu_hsec (hsec_2 )
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);
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// &Connect(.smpu_hit (smpu_hit2 ), @117
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// .smpu_entry (smpu_entry2 ), @118
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// .smpu_hsec (hsec_2 ) @119
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// ); @120
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//biu hsec
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assign pad_biu_hsec_pre = hsec_0 || hsec_1 || hsec_2;
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// &Force("nonport", "pad_biu_hsec_pre"); @140
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// &Force("nonport","pad_biu_hsec"); @145
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// &ModuleEnd; @148
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endmodule
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