240 lines
9.9 KiB
Verilog
240 lines
9.9 KiB
Verilog
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// &ModuleBeg; @22
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module uart(
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apb_uart_paddr,
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apb_uart_penable,
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apb_uart_psel,
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apb_uart_pwdata,
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apb_uart_pwrite,
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rst_b,
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s_in,
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s_out,
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sys_clk,
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uart_apb_prdata,
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uart_vic_int
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);
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// &Ports; @23
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input [31:0] apb_uart_paddr;
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input apb_uart_penable;
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input apb_uart_psel;
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input [31:0] apb_uart_pwdata;
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input apb_uart_pwrite;
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input rst_b;
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input s_in;
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input sys_clk;
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output s_out;
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output [31:0] uart_apb_prdata;
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output uart_vic_int;
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// &Regs; @24
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// &Wires; @25
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wire [31:0] apb_uart_paddr;
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wire apb_uart_penable;
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wire apb_uart_psel;
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wire [31:0] apb_uart_pwdata;
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wire apb_uart_pwrite;
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wire [15:0] ctrl_baud_gen_divisor;
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wire ctrl_baud_gen_set_dllh_vld;
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wire [1 :0] ctrl_receive_data_length;
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wire ctrl_receive_parity_bit;
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wire ctrl_receive_parity_en;
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wire ctrl_receive_stop_length;
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wire ctrl_reg_busy;
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wire ctrl_reg_fe;
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wire [3 :0] ctrl_reg_iid;
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wire ctrl_reg_iid_vld;
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wire ctrl_reg_oe;
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wire ctrl_reg_pe;
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wire [7 :0] ctrl_reg_rbr_wdata;
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wire ctrl_reg_rbr_write_en;
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wire ctrl_reg_thr_read;
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wire ctrl_reg_thsr_empty;
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wire [1 :0] ctrl_trans_data_length;
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wire ctrl_trans_parity_bit;
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wire ctrl_trans_parity_en;
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wire [7 :0] ctrl_trans_shift_data;
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wire ctrl_trans_stop_length;
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wire ctrl_trans_thr_vld;
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wire receive_clk_en;
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wire receive_ctrl_busy;
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wire receive_ctrl_fe;
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wire receive_ctrl_pe;
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wire [7 :0] receive_ctrl_rdata;
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wire receive_ctrl_redata_over;
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wire [15:0] reg_ctrl_dllh_data;
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wire [2 :0] reg_ctrl_ier_enable;
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wire [1 :0] reg_ctrl_lcr_dls;
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wire reg_ctrl_lcr_eps;
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wire reg_ctrl_lcr_pen;
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wire reg_ctrl_lcr_stop;
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wire reg_ctrl_lcr_wen;
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wire reg_ctrl_rbr_vld;
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wire reg_ctrl_set_dllh_vld;
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wire [7 :0] reg_ctrl_thr_data;
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wire reg_ctrl_thr_vld;
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wire reg_ctrl_threint_en;
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wire rst_b;
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wire s_in;
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wire s_out;
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wire sys_clk;
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wire trans_clk_en;
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wire trans_ctrl_busy;
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wire trans_ctrl_thr_read;
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wire trans_ctrl_thsr_empty;
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wire [31:0] uart_apb_prdata;
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wire uart_vic_int;
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// &Instance("uart_apb_reg"); @28
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uart_apb_reg x_uart_apb_reg (
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.apb_uart_paddr (apb_uart_paddr ),
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.apb_uart_penable (apb_uart_penable ),
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.apb_uart_psel (apb_uart_psel ),
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.apb_uart_pwdata (apb_uart_pwdata ),
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.apb_uart_pwrite (apb_uart_pwrite ),
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.ctrl_reg_busy (ctrl_reg_busy ),
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.ctrl_reg_fe (ctrl_reg_fe ),
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.ctrl_reg_iid (ctrl_reg_iid ),
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.ctrl_reg_iid_vld (ctrl_reg_iid_vld ),
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.ctrl_reg_oe (ctrl_reg_oe ),
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.ctrl_reg_pe (ctrl_reg_pe ),
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.ctrl_reg_rbr_wdata (ctrl_reg_rbr_wdata ),
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.ctrl_reg_rbr_write_en (ctrl_reg_rbr_write_en),
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.ctrl_reg_thr_read (ctrl_reg_thr_read ),
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.ctrl_reg_thsr_empty (ctrl_reg_thsr_empty ),
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.reg_ctrl_dllh_data (reg_ctrl_dllh_data ),
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.reg_ctrl_ier_enable (reg_ctrl_ier_enable ),
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.reg_ctrl_lcr_dls (reg_ctrl_lcr_dls ),
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.reg_ctrl_lcr_eps (reg_ctrl_lcr_eps ),
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.reg_ctrl_lcr_pen (reg_ctrl_lcr_pen ),
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.reg_ctrl_lcr_stop (reg_ctrl_lcr_stop ),
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.reg_ctrl_lcr_wen (reg_ctrl_lcr_wen ),
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.reg_ctrl_rbr_vld (reg_ctrl_rbr_vld ),
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.reg_ctrl_set_dllh_vld (reg_ctrl_set_dllh_vld),
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.reg_ctrl_thr_data (reg_ctrl_thr_data ),
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.reg_ctrl_thr_vld (reg_ctrl_thr_vld ),
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.reg_ctrl_threint_en (reg_ctrl_threint_en ),
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.rst_b (rst_b ),
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.sys_clk (sys_clk ),
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.uart_apb_prdata (uart_apb_prdata ),
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.uart_vic_int (uart_vic_int )
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);
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// &Instance("uart_baud_gen"); @29
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uart_baud_gen x_uart_baud_gen (
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.ctrl_baud_gen_divisor (ctrl_baud_gen_divisor ),
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.ctrl_baud_gen_set_dllh_vld (ctrl_baud_gen_set_dllh_vld),
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.receive_clk_en (receive_clk_en ),
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.rst_b (rst_b ),
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.sys_clk (sys_clk ),
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.trans_clk_en (trans_clk_en )
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);
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// &Instance("uart_ctrl"); @30
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uart_ctrl x_uart_ctrl (
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.ctrl_baud_gen_divisor (ctrl_baud_gen_divisor ),
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.ctrl_baud_gen_set_dllh_vld (ctrl_baud_gen_set_dllh_vld),
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.ctrl_receive_data_length (ctrl_receive_data_length ),
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.ctrl_receive_parity_bit (ctrl_receive_parity_bit ),
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.ctrl_receive_parity_en (ctrl_receive_parity_en ),
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.ctrl_receive_stop_length (ctrl_receive_stop_length ),
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.ctrl_reg_busy (ctrl_reg_busy ),
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.ctrl_reg_fe (ctrl_reg_fe ),
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.ctrl_reg_iid (ctrl_reg_iid ),
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.ctrl_reg_iid_vld (ctrl_reg_iid_vld ),
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.ctrl_reg_oe (ctrl_reg_oe ),
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.ctrl_reg_pe (ctrl_reg_pe ),
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.ctrl_reg_rbr_wdata (ctrl_reg_rbr_wdata ),
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.ctrl_reg_rbr_write_en (ctrl_reg_rbr_write_en ),
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.ctrl_reg_thr_read (ctrl_reg_thr_read ),
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.ctrl_reg_thsr_empty (ctrl_reg_thsr_empty ),
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.ctrl_trans_data_length (ctrl_trans_data_length ),
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.ctrl_trans_parity_bit (ctrl_trans_parity_bit ),
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.ctrl_trans_parity_en (ctrl_trans_parity_en ),
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.ctrl_trans_shift_data (ctrl_trans_shift_data ),
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.ctrl_trans_stop_length (ctrl_trans_stop_length ),
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.ctrl_trans_thr_vld (ctrl_trans_thr_vld ),
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.receive_ctrl_busy (receive_ctrl_busy ),
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.receive_ctrl_fe (receive_ctrl_fe ),
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.receive_ctrl_pe (receive_ctrl_pe ),
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.receive_ctrl_rdata (receive_ctrl_rdata ),
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.receive_ctrl_redata_over (receive_ctrl_redata_over ),
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.reg_ctrl_dllh_data (reg_ctrl_dllh_data ),
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.reg_ctrl_ier_enable (reg_ctrl_ier_enable ),
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.reg_ctrl_lcr_dls (reg_ctrl_lcr_dls ),
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.reg_ctrl_lcr_eps (reg_ctrl_lcr_eps ),
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.reg_ctrl_lcr_pen (reg_ctrl_lcr_pen ),
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.reg_ctrl_lcr_stop (reg_ctrl_lcr_stop ),
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.reg_ctrl_lcr_wen (reg_ctrl_lcr_wen ),
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.reg_ctrl_rbr_vld (reg_ctrl_rbr_vld ),
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.reg_ctrl_set_dllh_vld (reg_ctrl_set_dllh_vld ),
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.reg_ctrl_thr_data (reg_ctrl_thr_data ),
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.reg_ctrl_thr_vld (reg_ctrl_thr_vld ),
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.reg_ctrl_threint_en (reg_ctrl_threint_en ),
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.rst_b (rst_b ),
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.sys_clk (sys_clk ),
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.trans_ctrl_busy (trans_ctrl_busy ),
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.trans_ctrl_thr_read (trans_ctrl_thr_read ),
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.trans_ctrl_thsr_empty (trans_ctrl_thsr_empty )
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);
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// &Instance("uart_trans"); @31
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uart_trans x_uart_trans (
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.ctrl_trans_data_length (ctrl_trans_data_length),
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.ctrl_trans_parity_bit (ctrl_trans_parity_bit ),
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.ctrl_trans_parity_en (ctrl_trans_parity_en ),
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.ctrl_trans_shift_data (ctrl_trans_shift_data ),
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.ctrl_trans_stop_length (ctrl_trans_stop_length),
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.ctrl_trans_thr_vld (ctrl_trans_thr_vld ),
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.rst_b (rst_b ),
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.s_out (s_out ),
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.sys_clk (sys_clk ),
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.trans_clk_en (trans_clk_en ),
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.trans_ctrl_busy (trans_ctrl_busy ),
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.trans_ctrl_thr_read (trans_ctrl_thr_read ),
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.trans_ctrl_thsr_empty (trans_ctrl_thsr_empty )
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);
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// &Instance("uart_receive"); @32
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uart_receive x_uart_receive (
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.ctrl_receive_data_length (ctrl_receive_data_length),
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.ctrl_receive_parity_bit (ctrl_receive_parity_bit ),
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.ctrl_receive_parity_en (ctrl_receive_parity_en ),
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.ctrl_receive_stop_length (ctrl_receive_stop_length),
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.ctrl_trans_parity_en (ctrl_trans_parity_en ),
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.receive_clk_en (receive_clk_en ),
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.receive_ctrl_busy (receive_ctrl_busy ),
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.receive_ctrl_fe (receive_ctrl_fe ),
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.receive_ctrl_pe (receive_ctrl_pe ),
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.receive_ctrl_rdata (receive_ctrl_rdata ),
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.receive_ctrl_redata_over (receive_ctrl_redata_over),
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.rst_b (rst_b ),
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.s_in (s_in ),
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.sys_clk (sys_clk )
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);
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// &ModuleEnd; @34
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endmodule
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