522 lines
15 KiB
Verilog
522 lines
15 KiB
Verilog
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// &ModuleBeg; @22
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module uart_apb_reg(
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apb_uart_paddr,
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apb_uart_penable,
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apb_uart_psel,
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apb_uart_pwdata,
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apb_uart_pwrite,
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ctrl_reg_busy,
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ctrl_reg_fe,
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ctrl_reg_iid,
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ctrl_reg_iid_vld,
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ctrl_reg_oe,
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ctrl_reg_pe,
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ctrl_reg_rbr_wdata,
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ctrl_reg_rbr_write_en,
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ctrl_reg_thr_read,
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ctrl_reg_thsr_empty,
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reg_ctrl_dllh_data,
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reg_ctrl_ier_enable,
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reg_ctrl_lcr_dls,
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reg_ctrl_lcr_eps,
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reg_ctrl_lcr_pen,
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reg_ctrl_lcr_stop,
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reg_ctrl_lcr_wen,
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reg_ctrl_rbr_vld,
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reg_ctrl_set_dllh_vld,
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reg_ctrl_thr_data,
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reg_ctrl_thr_vld,
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reg_ctrl_threint_en,
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rst_b,
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sys_clk,
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uart_apb_prdata,
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uart_vic_int
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);
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// &Ports; @23
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input [31:0] apb_uart_paddr;
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input apb_uart_penable;
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input apb_uart_psel;
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input [31:0] apb_uart_pwdata;
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input apb_uart_pwrite;
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input ctrl_reg_busy;
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input ctrl_reg_fe;
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input [3 :0] ctrl_reg_iid;
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input ctrl_reg_iid_vld;
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input ctrl_reg_oe;
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input ctrl_reg_pe;
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input [7 :0] ctrl_reg_rbr_wdata;
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input ctrl_reg_rbr_write_en;
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input ctrl_reg_thr_read;
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input ctrl_reg_thsr_empty;
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input rst_b;
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input sys_clk;
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output [15:0] reg_ctrl_dllh_data;
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output [2 :0] reg_ctrl_ier_enable;
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output [1 :0] reg_ctrl_lcr_dls;
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output reg_ctrl_lcr_eps;
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output reg_ctrl_lcr_pen;
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output reg_ctrl_lcr_stop;
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output reg_ctrl_lcr_wen;
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output reg_ctrl_rbr_vld;
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output reg_ctrl_set_dllh_vld;
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output [7 :0] reg_ctrl_thr_data;
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output reg_ctrl_thr_vld;
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output reg_ctrl_threint_en;
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output [31:0] uart_apb_prdata;
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output uart_vic_int;
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// &Regs; @24
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reg iid_priv_vld;
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reg iir_iid_clr_vld;
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reg [7 :0] uart_dlh;
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reg [7 :0] uart_dll;
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reg [3 :0] uart_ier;
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reg [3 :0] uart_iir_iid;
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reg [4 :0] uart_lcr;
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reg uart_lcr_dlab;
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reg uart_lsr_dr;
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reg uart_lsr_fe;
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reg uart_lsr_oe;
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reg uart_lsr_pe;
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reg uart_lsr_thre;
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reg [7 :0] uart_rbr;
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reg [7 :0] uart_reg_data_pre;
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reg [7 :0] uart_thr;
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reg uart_usr;
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reg uart_vic_int;
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// &Wires; @25
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wire ahb_iir_read_vld;
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wire ahb_lsr_read_vld;
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wire ahb_rbr_read_vld;
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wire ahb_usr_read_vld;
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wire [31:0] apb_uart_paddr;
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wire apb_uart_penable;
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wire apb_uart_psel;
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wire [31:0] apb_uart_pwdata;
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wire apb_uart_pwrite;
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wire ctrl_reg_busy;
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wire ctrl_reg_fe;
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wire [3 :0] ctrl_reg_iid;
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wire ctrl_reg_iid_vld;
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wire ctrl_reg_oe;
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wire ctrl_reg_pe;
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wire [7 :0] ctrl_reg_rbr_wdata;
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wire ctrl_reg_rbr_write_en;
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wire ctrl_reg_thr_read;
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wire ctrl_reg_thsr_empty;
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wire dllh_en;
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wire [7 :0] endian_wdata;
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wire iir_iid_write_vld;
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wire rd_acc;
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wire [15:0] reg_ctrl_dllh_data;
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wire [2 :0] reg_ctrl_ier_enable;
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wire [1 :0] reg_ctrl_lcr_dls;
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wire reg_ctrl_lcr_eps;
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wire reg_ctrl_lcr_pen;
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wire reg_ctrl_lcr_stop;
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wire reg_ctrl_lcr_wen;
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wire reg_ctrl_rbr_vld;
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wire reg_ctrl_set_dllh_vld;
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wire [7 :0] reg_ctrl_thr_data;
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wire reg_ctrl_thr_vld;
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wire reg_ctrl_threint_en;
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wire rst_b;
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wire sys_clk;
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wire [31:0] uart_apb_prdata;
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wire uart_dlh_wen;
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wire uart_dll_wen;
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wire uart_ier_wen;
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wire uart_lcr_wen;
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wire uart_lsr_temt;
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wire [7 :0] uart_reg_data;
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wire [5 :0] uart_reg_haddr;
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wire uart_thr_wen;
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wire wr_acc;
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parameter RBR = 6'h00;
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parameter THR = 6'h00;
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parameter DLL = 6'h00;
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parameter DLH = 6'h01;
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parameter IER = 6'h01;
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parameter IIR = 6'h02;
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parameter LCR = 6'h03;
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parameter LSR = 6'h05;
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parameter USR = 6'h1f;
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// &Force("bus","apb_uart_paddr",31,0); @37
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// &Force("bus","apb_uart_pwdata",31,0); @38
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// //&Force("output","uart_ahb_hready_resp"); @39
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//==================================================================================
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// write register control signal
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//==================================================================================
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// define transfer type;
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//parameter TRANS_NONSEQ = 2'b10,
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// TRANS_SEQ = 2'b11,
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// RESP_OKAY = 2'b00,
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// RESP_ERROR = 2'b01;
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//assign acc_vld = ((ahb_uart_htrans[1:0] == TRANS_NONSEQ)
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// || (ahb_uart_htrans[1:0] == TRANS_SEQ))
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// && ahb_uart_hsel && uart_ahb_hready_resp;
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//
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//assign rd_acc_pre = acc_vld && !ahb_uart_hwrite;
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//assign wr_acc_pre = acc_vld && ahb_uart_hwrite;
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//
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//assign uart_ahb_hresp[1:0] = RESP_OKAY;
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//
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//parameter S_WRITE = 2'b10;
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//parameter S_IDLE = 2'b00;
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//parameter S_READ = 2'b01;
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//parameter S_RAW = 2'b11;
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//
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//always @(posedge sys_clk or negedge rst_b)
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//begin
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// if(!rst_b)
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// cur_state[1:0] <= S_IDLE;
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// else
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// cur_state[1:0] <= next_state[1:0];
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//end
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//
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//&CombBeg;
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//next_state[1:0] = S_IDLE;
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//rd_acc = 1'b0;
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//casez(cur_state[1:0])
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// S_IDLE,
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// S_READ,
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// S_RAW: begin
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// if(rd_acc_pre)
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// begin
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// rd_acc = 1'b1;
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// next_state[1:0] = S_READ;
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// end
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// else if(wr_acc_pre)
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// next_state[1:0] = S_WRITE;
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// end
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// S_WRITE: begin
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// if(rd_acc_pre)
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// next_state[1:0] = S_RAW;
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// else if(wr_acc_pre)
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// next_state[1:0] = S_WRITE;
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// end
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// default:next_state[1:0] = 2'bx;
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//endcase
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//&CombEnd;
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//
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//assign wr_acc = (cur_state[1:0] == S_WRITE);
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// //&Force("output","uart_ahb_hready_resp"); @97
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//assign uart_ahb_hready_resp = ~(cur_state[1:0] == S_RAW);
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//assign raw = (cur_state[2:0] == S_RAW);
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//assign uart_reg_haddr[5:0] = (wr_acc || raw)
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// ? uart_addr_lat[5:0]
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// : ahb_uart_haddr[7:2];
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//// latch address
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//// for byte or half word operation, data needs to be swapped.
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//always @(posedge sys_clk or negedge rst_b)
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//begin
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// if(!rst_b)
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// uart_addr_lat[5:0] <= 14'b0;
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// else if(uart_ahb_hready_resp)
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// begin
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// uart_addr_lat[5:0] <= ahb_uart_haddr[7:2];
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// end
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//end
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//assign endian_wdata[7:0] = i_bigend_b ? ahb_uart_hwdata[7:0] : ahb_uart_hwdata[31:24];
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// &Force("bus","ahb_uart_hwdata",31,0); @117
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assign endian_wdata[7:0] = apb_uart_pwdata[7:0];
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assign wr_acc = apb_uart_psel && apb_uart_pwrite && apb_uart_penable;
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assign rd_acc = apb_uart_psel && !apb_uart_pwrite && apb_uart_penable;
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assign uart_reg_haddr[5:0] = apb_uart_paddr[7:2];
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//==================================================================================
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// ahb write the uart register
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//==================================================================================
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assign dllh_en = !uart_usr && uart_lcr_dlab;
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assign uart_dll_wen = dllh_en && wr_acc && (uart_reg_haddr[5:0] == DLL);
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assign uart_dlh_wen = dllh_en && wr_acc && (uart_reg_haddr[5:0] == DLH);
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assign uart_thr_wen = !uart_lcr_dlab && wr_acc && (uart_reg_haddr[5:0] == THR);
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assign uart_ier_wen = !uart_lcr_dlab && wr_acc && (uart_reg_haddr[5:0] == IER);
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assign uart_lcr_wen = wr_acc && (uart_reg_haddr[5:0] == LCR);
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always @(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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uart_dll[7:0] <= 8'h0;
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else if(uart_dll_wen)
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uart_dll[7:0] <= endian_wdata[7:0];
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end
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always @(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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uart_dlh[7:0] <= 8'h0;
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else if(uart_dlh_wen)
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uart_dlh[7:0] <= endian_wdata[7:0];
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end
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always @(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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uart_thr[7:0] <= 8'h0;
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else if(uart_thr_wen)
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uart_thr[7:0] <= endian_wdata[7:0];
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end
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always @(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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uart_ier[3:0] <= 4'h0;
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else if(uart_ier_wen)
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uart_ier[3:0] <= endian_wdata[3:0] ;
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end
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always @(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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begin
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uart_lcr_dlab <= 1'b0;
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uart_lcr[4:0] <= 5'h0;
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end
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else if(uart_lcr_wen)
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begin
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uart_lcr_dlab <= endian_wdata[7];
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uart_lcr[4:0] <= endian_wdata[4:0] ;
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end
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else
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begin
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uart_lcr_dlab <= uart_lcr_dlab;
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uart_lcr[4:0] <= uart_lcr[4:0];
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end
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end
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//==================================================================================
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// ahb read the uart register
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//==================================================================================
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//always@(posedge sys_clk or negedge rst_b)
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//begin
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// if(!rst_b)
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// uart_reg_data[7:0] <= 8'b0;
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// else if(rd_acc)
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// uart_reg_data[7:0] <= uart_reg_data_pre[7:0];
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//end
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assign uart_reg_data[7:0] = rd_acc ? uart_reg_data_pre[7:0] : 8'bx;
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// &CombBeg; @194
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always @( uart_dll[7:0]
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or uart_lsr_fe
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or uart_ier[2:0]
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or uart_dlh[7:0]
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or uart_lsr_oe
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or uart_iir_iid[3:0]
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or uart_rbr[7:0]
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or uart_lcr_dlab
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or uart_usr
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or uart_lsr_pe
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or uart_lsr_temt
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or uart_reg_haddr[5:0]
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or uart_lsr_thre
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or uart_lcr[4:0]
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or uart_lsr_dr)
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begin
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case(uart_reg_haddr[5:0])
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RBR: uart_reg_data_pre[7:0] = uart_lcr_dlab ? uart_dll[7:0] : uart_rbr[7:0];
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IER: uart_reg_data_pre[7:0] = uart_lcr_dlab ? uart_dlh[7:0] : {5'b0,uart_ier[2:0]};
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IIR: uart_reg_data_pre[7:0] = {4'b0,uart_iir_iid[3:0]};
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LCR: uart_reg_data_pre[7:0] = {uart_lcr_dlab,2'b0,uart_lcr[4:0]};
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LSR: uart_reg_data_pre[7:0] = {1'b0,uart_lsr_temt,uart_lsr_thre,1'b0,
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uart_lsr_fe,uart_lsr_pe,uart_lsr_oe,uart_lsr_dr};
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USR: uart_reg_data_pre[7:0] = {6'b0,uart_usr};
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default:uart_reg_data_pre[7:0] = 8'b0;
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endcase
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// &CombEnd; @205
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end
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//assign uart_ahb_hrdata[31:24] = i_bigend_b ? 8'b0 : uart_reg_data[7:0];
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assign uart_apb_prdata[31:0] = {24'b0,uart_reg_data[7:0]};
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// &CombBeg; @209
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always @( uart_iir_iid[3:0])
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begin
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casez(uart_iir_iid[3:0])
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4'b0010:uart_vic_int =1'b1;
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4'b0100:uart_vic_int =1'b1;
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4'b0110:uart_vic_int =1'b1;
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default: uart_vic_int = 1'b0;
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endcase
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// &CombEnd; @216
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end
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//==================================================================================
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// Interface with UART_CTRL
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//==================================================================================
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//==================================================================================
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// UART_CTRL write the uart register
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//==================================================================================
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always @(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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uart_rbr[7:0] <= 8'b0;
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else if(ctrl_reg_rbr_write_en)
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uart_rbr[7:0] <= ctrl_reg_rbr_wdata[7:0];
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end
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always @(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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uart_iir_iid[3:0] <= 4'b0001;
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else if(iir_iid_write_vld)
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uart_iir_iid[3:0] <= ctrl_reg_iid[3:0];
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else if(iir_iid_clr_vld)
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uart_iir_iid[3:0] <= 4'b0001;
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end
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assign iir_iid_write_vld = ctrl_reg_iid_vld && iid_priv_vld;
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// &CombBeg; @245
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always @( uart_iir_iid[3:0]
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or ctrl_reg_iid[2:0])
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begin
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casez(uart_iir_iid[3:0])
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4'b0001: iid_priv_vld = 1'b1;
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4'b0111: iid_priv_vld = 1'b1;
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4'b0010: iid_priv_vld = (ctrl_reg_iid[2] && !ctrl_reg_iid[0]) ? 1 : 0;
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4'b0100: iid_priv_vld = (ctrl_reg_iid[2:0] == 3'b110) ? 1 : 0;
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4'b0110: iid_priv_vld = 1'b0;
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default: iid_priv_vld = 1'b0;
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endcase
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// &CombEnd; @254
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end
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// &CombBeg; @257
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always @( ahb_rbr_read_vld
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or uart_iir_iid[3:0]
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or ahb_lsr_read_vld
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or uart_lsr_thre
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or ahb_iir_read_vld
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or ahb_usr_read_vld)
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begin
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casez(uart_iir_iid[3:0])
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4'b0010: iir_iid_clr_vld = !uart_lsr_thre || ahb_iir_read_vld;
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4'b0100: iir_iid_clr_vld = ahb_rbr_read_vld;
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4'b0110: iir_iid_clr_vld = ahb_lsr_read_vld;
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4'b0111: iir_iid_clr_vld = ahb_usr_read_vld;
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default: iir_iid_clr_vld = 1'b0;
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endcase
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// &CombEnd; @265
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end
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assign ahb_iir_read_vld = rd_acc && ( uart_reg_haddr[5:0] == IIR );
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assign ahb_lsr_read_vld = rd_acc && ( uart_reg_haddr[5:0] == LSR );
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assign ahb_usr_read_vld = rd_acc && ( uart_reg_haddr[5:0] == USR );
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assign ahb_rbr_read_vld = rd_acc && !uart_lcr_dlab &&( uart_reg_haddr[5:0] == RBR);
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always @(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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begin
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uart_lsr_thre <= 1'b1;
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end
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else if(uart_thr_wen)
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begin
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uart_lsr_thre <= 1'b0;
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end
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else if(ctrl_reg_thr_read)
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begin
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uart_lsr_thre <= 1'b1;
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end
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end
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|
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assign uart_lsr_temt = ctrl_reg_thsr_empty && uart_lsr_thre;
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always @(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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uart_lsr_dr <= 1'b0;
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else if(ctrl_reg_rbr_write_en && !uart_lsr_pe && !uart_lsr_fe)
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uart_lsr_dr <= 1'b1;
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else if(ahb_rbr_read_vld )
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uart_lsr_dr <= 1'b0;
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end
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|
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always @(posedge sys_clk or negedge rst_b)
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|
begin
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|
if(!rst_b)
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uart_lsr_fe <= 1'b0;
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else if(ctrl_reg_fe)
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uart_lsr_fe <= 1'b1;
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else if( ahb_lsr_read_vld )
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uart_lsr_fe <= 1'b0;
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end
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|
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|
always @(posedge sys_clk or negedge rst_b)
|
|
begin
|
|
if(!rst_b)
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uart_lsr_pe <= 1'b0;
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else if(ctrl_reg_pe)
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uart_lsr_pe <= 1'b1;
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|
else if( ahb_lsr_read_vld )
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|
uart_lsr_pe <= 1'b0;
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|
end
|
|
|
|
always @(posedge sys_clk or negedge rst_b)
|
|
begin
|
|
if(!rst_b)
|
|
uart_lsr_oe <= 1'b0;
|
|
else if(ctrl_reg_oe)
|
|
uart_lsr_oe <= 1'b1;
|
|
else if( ahb_lsr_read_vld )
|
|
uart_lsr_oe <= 1'b0;
|
|
end
|
|
|
|
always @(posedge sys_clk or negedge rst_b)
|
|
begin
|
|
if(!rst_b)
|
|
uart_usr <= 1'b0;
|
|
else if(ctrl_reg_busy)
|
|
uart_usr <= 1'b1;
|
|
else if(!ctrl_reg_busy)
|
|
uart_usr <= 1'b0;
|
|
end
|
|
|
|
//==================================================================================
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// Interface with UART_CTRL
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|
//==================================================================================
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|
assign reg_ctrl_thr_vld = !uart_lsr_thre;
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|
assign reg_ctrl_thr_data[7:0] = uart_thr[7:0];
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|
assign reg_ctrl_ier_enable[2:0] = uart_ier[2:0];
|
|
assign reg_ctrl_dllh_data[15:0] = {uart_dlh[7:0],uart_dll[7:0]};
|
|
assign reg_ctrl_lcr_eps = uart_lcr[4];
|
|
assign reg_ctrl_lcr_pen = uart_lcr[3];
|
|
assign reg_ctrl_lcr_stop = uart_lcr[2];
|
|
assign reg_ctrl_lcr_dls[1:0] = uart_lcr[1:0];
|
|
assign reg_ctrl_rbr_vld = uart_lsr_dr;
|
|
assign reg_ctrl_lcr_wen = uart_lcr_wen;
|
|
assign reg_ctrl_set_dllh_vld = uart_dlh_wen || uart_dll_wen;
|
|
assign reg_ctrl_threint_en = uart_ier_wen && endian_wdata[1];
|
|
|
|
// &ModuleEnd; @358
|
|
endmodule
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