314 lines
7.8 KiB
Verilog
314 lines
7.8 KiB
Verilog
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// &ModuleBeg; @22
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module uart_receive(
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ctrl_receive_data_length,
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ctrl_receive_parity_bit,
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ctrl_receive_parity_en,
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ctrl_receive_stop_length,
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ctrl_trans_parity_en,
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receive_clk_en,
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receive_ctrl_busy,
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receive_ctrl_fe,
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receive_ctrl_pe,
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receive_ctrl_rdata,
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receive_ctrl_redata_over,
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rst_b,
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s_in,
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sys_clk
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);
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// &Ports; @23
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input [1:0] ctrl_receive_data_length;
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input ctrl_receive_parity_bit;
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input ctrl_receive_parity_en;
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input ctrl_receive_stop_length;
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input ctrl_trans_parity_en;
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input receive_clk_en;
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input rst_b;
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input s_in;
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input sys_clk;
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output receive_ctrl_busy;
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output receive_ctrl_fe;
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output receive_ctrl_pe;
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output [7:0] receive_ctrl_rdata;
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output receive_ctrl_redata_over;
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// &Regs; @24
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reg [3:0] counter;
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reg [5:0] cur_state;
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reg [2:0] da_conter;
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reg di_reg1;
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reg di_reg2;
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reg fram_error;
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reg [5:0] next_state;
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reg parity_cout;
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reg [7:0] receive_shift_reg;
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reg sync1;
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reg sync2;
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// &Wires; @25
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wire cont_16;
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wire cont_8;
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wire [1:0] ctrl_receive_data_length;
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wire ctrl_receive_parity_bit;
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wire ctrl_receive_parity_en;
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wire ctrl_receive_stop_length;
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wire ctrl_trans_parity_en;
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wire data_over;
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wire di_rx_in;
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wire receive_clk_en;
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wire receive_ctrl_busy;
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wire receive_ctrl_fe;
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wire receive_ctrl_pe;
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wire [7:0] receive_ctrl_rdata;
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wire receive_ctrl_redata_over;
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wire rst_b;
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wire rx_in;
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wire s_in;
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wire stop_over;
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wire sys_clk;
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parameter IDLE = 6'b000001,
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START = 6'b000010,
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DATA = 6'b000100,
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PARITY = 6'b001000,
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STOP = 6'b010000,
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CLECT_SIG = 6'b100000;
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always@(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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cur_state[5:0] <= IDLE;
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else if(receive_clk_en)
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cur_state[5:0] <= next_state[5:0];
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end
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//////////////////////////////////////////////////////////
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////////////// midified by huawm, 2016-2-26 //////////////
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//////////////////////////////////////////////////////////
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always @(posedge sys_clk or negedge rst_b)
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begin
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if(rst_b == 1'b0)
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begin
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sync1 <= 1'b1;
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sync2 <= 1'b1;
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end
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else
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begin
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sync1 <= s_in;
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sync2 <= sync1;
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end
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end
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assign rx_in = sync2;
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//-------------------------------------------------------
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// data integrity, the best two out of three samples will
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// give the resulting serial input that will be passed to
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// the RX FSM
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// ------------------------------------------------------
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always @(posedge sys_clk or negedge rst_b)
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begin
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if(rst_b == 1'b0)
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begin
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di_reg1 <= 1'b1;
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di_reg2 <= 1'b1;
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end
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else if(receive_clk_en)
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begin
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di_reg1 <= rx_in;
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di_reg2 <= di_reg1;
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end
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end
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assign di_rx_in = (rx_in & di_reg1) | (rx_in & di_reg2) | (di_reg1 & di_reg2);
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///////////////////////////////////////////////////////
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// &CombBeg; @82
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always @( di_rx_in
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or stop_over
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or cur_state[5:0]
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or cont_8
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or cont_16
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or data_over
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or ctrl_trans_parity_en)
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begin
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next_state[5:0] = IDLE;
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case(cur_state[5:0])
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IDLE:
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begin
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if(!di_rx_in)
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next_state[5:0] = START;
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end
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START:
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begin
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if(cont_8)
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begin
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if(!di_rx_in)
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next_state[5:0] = DATA;
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end
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else
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next_state[5:0] = START;
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end
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DATA:
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begin
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if(cont_16 && data_over)
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next_state[5:0] = ctrl_trans_parity_en ? PARITY : STOP;
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else
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next_state[5:0] = DATA;
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end
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PARITY:
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begin
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if(cont_16)
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next_state[5:0] = STOP;
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else
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next_state[5:0] = PARITY;
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end
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STOP:
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begin
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if(cont_16 && stop_over)
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begin
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next_state[5:0] = CLECT_SIG;
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end
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else
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next_state[5:0] = STOP;
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end
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CLECT_SIG:
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next_state[5:0] = IDLE;
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default: next_state[5:0] = IDLE;
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endcase
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// &CombEnd; @127
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end
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// the clock counter
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always@(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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counter[3:0] <= 4'b0;
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else if(receive_clk_en)
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begin
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if( (cur_state[0]) || ((cur_state[1]) && cont_8))
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counter[3:0] <= 4'b0;
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else
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counter[3:0] <= counter[3:0] + 1;
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end
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end
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assign cont_8 = (counter[3:0] == 4'b0111);
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assign cont_16 = (counter[3:0] == 4'b1111);
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//the data and the stop bit counter
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always@(posedge sys_clk or negedge rst_b)
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begin
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if(!rst_b)
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da_conter[2:0] <= 2'b0;
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else if(receive_clk_en)
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begin
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if((data_over || stop_over)&& cont_16)
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da_conter[2:0] <= 2'b0;
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else if(((cur_state[2]) ||(cur_state[4])) && cont_16)
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da_conter[2:0] <= da_conter[2:0] + 1'b1;
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end
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end
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assign data_over = (da_conter[2:0] == {1'b1,ctrl_receive_data_length[1:0]});
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assign stop_over = (cur_state[4]) && (da_conter[2:0] == {2'b0,ctrl_receive_stop_length});
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//==============================================================
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// generate the output s_out signal
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//==============================================================
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always@(posedge sys_clk or negedge rst_b)
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begin
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if( !rst_b )
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receive_shift_reg[7:0] <= 8'b0;
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else if(receive_clk_en)
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begin
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if((cur_state[2])&& cont_16)
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receive_shift_reg[7:0] <= {di_rx_in,receive_shift_reg[7:1]};
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else if((cur_state[0]))
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receive_shift_reg[7:0] <= 8'b0;
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end
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end
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assign receive_ctrl_rdata[7:0] = receive_shift_reg[7:0];
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// generate the receive busy signal
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assign receive_ctrl_busy = ~(cur_state[0]);
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//receive the parity and check the parity
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always@(posedge sys_clk or negedge rst_b)
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begin
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if( !rst_b )
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parity_cout <= 1'b0;
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else if(receive_clk_en)
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begin
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if((cur_state[2]) || (cur_state[3]))
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begin
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if(cont_16)
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parity_cout <= parity_cout ^ di_rx_in;
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else
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parity_cout <= parity_cout;
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end
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else if(cur_state[4] || cur_state[5])
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parity_cout <= parity_cout;
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else
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parity_cout <= 1'b0;
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end
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end
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//generate the fram error signal
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always@(posedge sys_clk or negedge rst_b)
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begin
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if( !rst_b )
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fram_error <= 1'b0;
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else if((cur_state[4]))
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begin
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if(fram_error == 1'b1)
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fram_error <= fram_error;
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else if(cont_16)
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fram_error <= ~di_rx_in;
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else
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fram_error <= fram_error;
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end
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else if(cur_state[5])
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fram_error <= fram_error;
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else
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fram_error <= 1'b0;
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end
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// the parity error bit
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assign receive_ctrl_pe = (~(parity_cout ^ ctrl_receive_parity_bit)) && ctrl_receive_parity_en && (cur_state[5]);
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//the frame error bit
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assign receive_ctrl_fe = fram_error && (cur_state[5]);
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//generate the data receive control signal
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// &Force("output","receive_ctrl_pe"); @236
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assign receive_ctrl_redata_over = cur_state[5] && !fram_error && !receive_ctrl_pe;
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// &ModuleEnd; @241
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endmodule
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