137 lines
3.2 KiB
Verilog
137 lines
3.2 KiB
Verilog
module tb_top;
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reg clk;
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reg rst;
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reg [7:0] mem[65535:0];
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integer i;
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integer f;
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initial
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begin
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$display("Starting bench");
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if (`TRACE)
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begin
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$dumpfile("waveform.vcd");
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$dumpvars(0, tb_top);
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end
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// Reset
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clk = 0;
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rst = 1;
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repeat (5) @(posedge clk);
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rst = 0;
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// Load TCM memory
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for (i=0;i<65535;i=i+1)
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mem[i] = 0;
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f = $fopenr("./build/tcm.bin");
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i = $fread(mem, f);
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for (i=0;i<65535;i=i+1)
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u_mem.write(i, mem[i]);
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end
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initial
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begin
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forever
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begin
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clk = #5 ~clk;
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end
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end
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wire mem_i_rd_w;
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wire mem_i_flush_w;
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wire mem_i_invalidate_w;
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wire [ 31:0] mem_i_pc_w;
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wire [ 31:0] mem_d_addr_w;
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wire [ 31:0] mem_d_data_wr_w;
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wire mem_d_rd_w;
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wire [ 3:0] mem_d_wr_w;
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wire mem_d_cacheable_w;
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wire [ 10:0] mem_d_req_tag_w;
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wire mem_d_invalidate_w;
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wire mem_d_writeback_w;
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wire mem_d_flush_w;
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wire mem_i_accept_w;
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wire mem_i_valid_w;
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wire mem_i_error_w;
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wire [ 31:0] mem_i_inst_w;
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wire [ 31:0] mem_d_data_rd_w;
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wire mem_d_accept_w;
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wire mem_d_ack_w;
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wire mem_d_error_w;
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wire [ 10:0] mem_d_resp_tag_w;
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riscv_core
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u_dut
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//-----------------------------------------------------------------
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// Ports
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//-----------------------------------------------------------------
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(
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// Inputs
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.clk_i(clk)
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,.rst_i(rst)
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,.mem_d_data_rd_i(mem_d_data_rd_w)
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,.mem_d_accept_i(mem_d_accept_w)
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,.mem_d_ack_i(mem_d_ack_w)
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,.mem_d_error_i(mem_d_error_w)
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,.mem_d_resp_tag_i(mem_d_resp_tag_w)
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,.mem_i_accept_i(mem_i_accept_w)
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,.mem_i_valid_i(mem_i_valid_w)
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,.mem_i_error_i(mem_i_error_w)
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,.mem_i_inst_i(mem_i_inst_w)
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,.intr_i(1'b0)
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,.reset_vector_i(32'h80000000)
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,.cpu_id_i('b0)
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// Outputs
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,.mem_d_addr_o(mem_d_addr_w)
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,.mem_d_data_wr_o(mem_d_data_wr_w)
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,.mem_d_rd_o(mem_d_rd_w)
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,.mem_d_wr_o(mem_d_wr_w)
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,.mem_d_cacheable_o(mem_d_cacheable_w)
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,.mem_d_req_tag_o(mem_d_req_tag_w)
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,.mem_d_invalidate_o(mem_d_invalidate_w)
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,.mem_d_writeback_o(mem_d_writeback_w)
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,.mem_d_flush_o(mem_d_flush_w)
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,.mem_i_rd_o(mem_i_rd_w)
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,.mem_i_flush_o(mem_i_flush_w)
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,.mem_i_invalidate_o(mem_i_invalidate_w)
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,.mem_i_pc_o(mem_i_pc_w)
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);
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tcm_mem
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u_mem
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(
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// Inputs
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.clk_i(clk)
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,.rst_i(rst)
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,.mem_i_rd_i(mem_i_rd_w)
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,.mem_i_flush_i(mem_i_flush_w)
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,.mem_i_invalidate_i(mem_i_invalidate_w)
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,.mem_i_pc_i(mem_i_pc_w)
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,.mem_d_addr_i(mem_d_addr_w)
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,.mem_d_data_wr_i(mem_d_data_wr_w)
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,.mem_d_rd_i(mem_d_rd_w)
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,.mem_d_wr_i(mem_d_wr_w)
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,.mem_d_cacheable_i(mem_d_cacheable_w)
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,.mem_d_req_tag_i(mem_d_req_tag_w)
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,.mem_d_invalidate_i(mem_d_invalidate_w)
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,.mem_d_writeback_i(mem_d_writeback_w)
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,.mem_d_flush_i(mem_d_flush_w)
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// Outputs
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,.mem_i_accept_o(mem_i_accept_w)
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,.mem_i_valid_o(mem_i_valid_w)
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,.mem_i_error_o(mem_i_error_w)
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,.mem_i_inst_o(mem_i_inst_w)
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,.mem_d_data_rd_o(mem_d_data_rd_w)
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,.mem_d_accept_o(mem_d_accept_w)
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,.mem_d_ack_o(mem_d_ack_w)
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,.mem_d_error_o(mem_d_error_w)
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,.mem_d_resp_tag_o(mem_d_resp_tag_w)
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);
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endmodule |