189 lines
10 KiB
Systemverilog
189 lines
10 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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//
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// Owner:
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// Function: Checks the memory map for the address
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// Comments:
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//
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//********************************************************************************
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module lsu_addrcheck
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import swerv_types::*;
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(
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input logic lsu_freeze_c2_dc2_clk, // clock
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input logic lsu_freeze_c2_dc3_clk,
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input logic lsu_freeze_c2_dc2_clken,
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input logic lsu_freeze_c2_dc3_clken,
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input logic rst_l, // reset
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input logic clk,
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input logic [31:0] start_addr_dc1, // start address for lsu
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input logic [31:0] end_addr_dc1, // end address for lsu
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input lsu_pkt_t lsu_pkt_dc1, // packet in dc1
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input logic [31:0] dec_tlu_mrac_ff, // CSR read
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output logic is_sideeffects_dc2, // is sideffects space
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output logic is_sideeffects_dc3,
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output logic addr_in_dccm_dc1, // address in dccm
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output logic addr_in_pic_dc1, // address in pic
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output logic addr_external_dc1, // address in external
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output logic access_fault_dc1, // access fault
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output logic misaligned_fault_dc1, // misaligned
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input logic scan_mode
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);
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`include "global.h"
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localparam DCCM_REGION = `RV_DCCM_REGION;
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localparam PIC_REGION = `RV_PIC_REGION;
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localparam ICCM_REGION = `RV_ICCM_REGION;
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`ifdef RV_ICCM_ENABLE
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localparam ICCM_ENABLE = 1'b1;
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`else
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localparam ICCM_ENABLE = 1'b0;
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`endif
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`ifdef RV_DCCM_ENABLE
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localparam DCCM_ENABLE = 1'b1;
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`else
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localparam DCCM_ENABLE = 1'b0;
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`endif
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logic is_sideeffects_dc1, is_aligned_dc1;
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logic start_addr_in_dccm_dc1, end_addr_in_dccm_dc1;
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logic start_addr_in_dccm_region_dc1, end_addr_in_dccm_region_dc1;
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logic start_addr_in_pic_dc1, end_addr_in_pic_dc1;
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logic start_addr_in_pic_region_dc1, end_addr_in_pic_region_dc1;
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logic [4:0] csr_idx;
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logic addr_in_iccm;
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logic non_dccm_access_ok;
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if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
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// Start address check
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rvrangecheck #(.CCM_SADR(`RV_DCCM_SADR),
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.CCM_SIZE(`RV_DCCM_SIZE)) start_addr_dccm_rangecheck (
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.addr(start_addr_dc1[31:0]),
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.in_range(start_addr_in_dccm_dc1),
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.in_region(start_addr_in_dccm_region_dc1)
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);
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// End address check
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rvrangecheck #(.CCM_SADR(`RV_DCCM_SADR),
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.CCM_SIZE(`RV_DCCM_SIZE)) end_addr_dccm_rangecheck (
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.addr(end_addr_dc1[31:0]),
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.in_range(end_addr_in_dccm_dc1),
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.in_region(end_addr_in_dccm_region_dc1)
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);
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end else begin: Gen_dccm_disable // block: Gen_dccm_enable
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assign start_addr_in_dccm_dc1 = '0;
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assign start_addr_in_dccm_region_dc1 = '0;
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assign end_addr_in_dccm_dc1 = '0;
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assign end_addr_in_dccm_region_dc1 = '0;
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end
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if (ICCM_ENABLE == 1) begin : check_iccm
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assign addr_in_iccm = (start_addr_dc1[31:28] == ICCM_REGION);
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end
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else begin
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assign addr_in_iccm = 1'b0;
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end
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// PIC memory check
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// Start address check
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rvrangecheck #(.CCM_SADR(`RV_PIC_BASE_ADDR),
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.CCM_SIZE(`RV_PIC_SIZE)) start_addr_pic_rangecheck (
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.addr(start_addr_dc1[31:0]),
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.in_range(start_addr_in_pic_dc1),
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.in_region(start_addr_in_pic_region_dc1)
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);
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// End address check
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rvrangecheck #(.CCM_SADR(`RV_PIC_BASE_ADDR),
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.CCM_SIZE(`RV_PIC_SIZE)) end_addr_pic_rangecheck (
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.addr(end_addr_dc1[31:0]),
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.in_range(end_addr_in_pic_dc1),
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.in_region(end_addr_in_pic_region_dc1)
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);
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assign addr_in_dccm_dc1 = (start_addr_in_dccm_dc1 & end_addr_in_dccm_dc1);
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assign addr_in_pic_dc1 = (start_addr_in_pic_dc1 & end_addr_in_pic_dc1);
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assign addr_external_dc1 = ~(addr_in_dccm_dc1 | addr_in_pic_dc1); //~addr_in_dccm_region_dc1;
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assign csr_idx[4:0] = {start_addr_dc1[31:28], 1'b1};
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assign is_sideeffects_dc1 = dec_tlu_mrac_ff[csr_idx] & ~(start_addr_in_dccm_region_dc1 | start_addr_in_pic_region_dc1 | addr_in_iccm); //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
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assign is_aligned_dc1 = (lsu_pkt_dc1.word & (start_addr_dc1[1:0] == 2'b0)) |
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(lsu_pkt_dc1.half & (start_addr_dc1[0] == 1'b0)) |
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lsu_pkt_dc1.by;
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assign non_dccm_access_ok = (~(|{`RV_DATA_ACCESS_ENABLE0,`RV_DATA_ACCESS_ENABLE1,`RV_DATA_ACCESS_ENABLE2,`RV_DATA_ACCESS_ENABLE3,`RV_DATA_ACCESS_ENABLE4,`RV_DATA_ACCESS_ENABLE5,`RV_DATA_ACCESS_ENABLE6,`RV_DATA_ACCESS_ENABLE7})) |
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(((`RV_DATA_ACCESS_ENABLE0 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK0)) == (`RV_DATA_ACCESS_ADDR0 | `RV_DATA_ACCESS_MASK0)) |
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(`RV_DATA_ACCESS_ENABLE1 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK1)) == (`RV_DATA_ACCESS_ADDR1 | `RV_DATA_ACCESS_MASK1)) |
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(`RV_DATA_ACCESS_ENABLE2 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK2)) == (`RV_DATA_ACCESS_ADDR2 | `RV_DATA_ACCESS_MASK2)) |
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(`RV_DATA_ACCESS_ENABLE3 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK3)) == (`RV_DATA_ACCESS_ADDR3 | `RV_DATA_ACCESS_MASK3)) |
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(`RV_DATA_ACCESS_ENABLE4 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK4)) == (`RV_DATA_ACCESS_ADDR4 | `RV_DATA_ACCESS_MASK4)) |
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(`RV_DATA_ACCESS_ENABLE5 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK5)) == (`RV_DATA_ACCESS_ADDR5 | `RV_DATA_ACCESS_MASK5)) |
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(`RV_DATA_ACCESS_ENABLE6 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK6)) == (`RV_DATA_ACCESS_ADDR6 | `RV_DATA_ACCESS_MASK6)) |
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(`RV_DATA_ACCESS_ENABLE7 & ((start_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK7)) == (`RV_DATA_ACCESS_ADDR7 | `RV_DATA_ACCESS_MASK7))) &
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((`RV_DATA_ACCESS_ENABLE0 & ((end_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK0)) == (`RV_DATA_ACCESS_ADDR0 | `RV_DATA_ACCESS_MASK0)) |
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(`RV_DATA_ACCESS_ENABLE1 & ((end_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK1)) == (`RV_DATA_ACCESS_ADDR1 | `RV_DATA_ACCESS_MASK1)) |
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(`RV_DATA_ACCESS_ENABLE2 & ((end_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK2)) == (`RV_DATA_ACCESS_ADDR2 | `RV_DATA_ACCESS_MASK2)) |
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(`RV_DATA_ACCESS_ENABLE3 & ((end_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK3)) == (`RV_DATA_ACCESS_ADDR3 | `RV_DATA_ACCESS_MASK3)) |
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(`RV_DATA_ACCESS_ENABLE4 & ((end_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK4)) == (`RV_DATA_ACCESS_ADDR4 | `RV_DATA_ACCESS_MASK4)) |
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(`RV_DATA_ACCESS_ENABLE5 & ((end_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK5)) == (`RV_DATA_ACCESS_ADDR5 | `RV_DATA_ACCESS_MASK5)) |
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(`RV_DATA_ACCESS_ENABLE6 & ((end_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK6)) == (`RV_DATA_ACCESS_ADDR6 | `RV_DATA_ACCESS_MASK6)) |
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(`RV_DATA_ACCESS_ENABLE7 & ((end_addr_dc1[31:0] | `RV_DATA_ACCESS_MASK7)) == (`RV_DATA_ACCESS_ADDR7 | `RV_DATA_ACCESS_MASK7))));
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// Access fault logic
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// 1. Addr in dccm region but not in dccm offset
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// 2. Addr in picm region but not in picm offset
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// 3. DCCM -> PIC offset cross when DCCM/PIC in same region (PIC access are always word aligned so no cross possible from PIC->DCCM)
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// 4. Ld/St access to picm are not word aligned
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// 5. Address not in protected space or dccm/pic region
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if (DCCM_ENABLE & (DCCM_REGION == PIC_REGION)) begin
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assign access_fault_dc1 = ((start_addr_in_dccm_region_dc1 & ~(start_addr_in_dccm_dc1 | start_addr_in_pic_dc1)) |
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(end_addr_in_dccm_region_dc1 & ~(end_addr_in_dccm_dc1 | end_addr_in_pic_dc1)) |
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(start_addr_in_dccm_dc1 & end_addr_in_pic_dc1) |
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(start_addr_in_pic_dc1 & end_addr_in_dccm_dc1) |
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((addr_in_pic_dc1 & ((start_addr_dc1[1:0] != 2'b0) | ~lsu_pkt_dc1.word))) |
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(~start_addr_in_dccm_region_dc1 & ~non_dccm_access_ok)) & lsu_pkt_dc1.valid & ~lsu_pkt_dc1.dma;
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end else begin
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assign access_fault_dc1 = ((start_addr_in_dccm_region_dc1 & ~start_addr_in_dccm_dc1) |
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(end_addr_in_dccm_region_dc1 & ~end_addr_in_dccm_dc1) |
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(start_addr_in_pic_region_dc1 & ~start_addr_in_pic_dc1) |
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(end_addr_in_pic_region_dc1 & ~end_addr_in_pic_dc1) |
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((addr_in_pic_dc1 & ((start_addr_dc1[1:0] != 2'b0) | ~lsu_pkt_dc1.word))) |
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(~start_addr_in_pic_region_dc1 & ~start_addr_in_dccm_region_dc1 & ~non_dccm_access_ok)) & lsu_pkt_dc1.valid & ~lsu_pkt_dc1.dma;
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end
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// Misaligned happens due to 2 reasons
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// 1. Region cross
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// 2. sideeffects access which are not aligned
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assign misaligned_fault_dc1 = ((start_addr_dc1[31:28] != end_addr_dc1[31:28]) |
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(is_sideeffects_dc1 & ~is_aligned_dc1)) & addr_external_dc1 & lsu_pkt_dc1.valid & ~lsu_pkt_dc1.dma;
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rvdff_fpga #(.WIDTH(1)) is_sideeffects_dc2ff (.din(is_sideeffects_dc1), .dout(is_sideeffects_dc2), .clk(lsu_freeze_c2_dc2_clk), .clken(lsu_freeze_c2_dc2_clken), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(1)) is_sideeffects_dc3ff (.din(is_sideeffects_dc2), .dout(is_sideeffects_dc3), .clk(lsu_freeze_c2_dc3_clk), .clken(lsu_freeze_c2_dc3_clken), .rawclk(clk), .*);
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endmodule // lsu_addrcheck
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