1026 lines
20 KiB
Systemverilog
1026 lines
20 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//=========================================================================================================================
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//=================================== START OF CCM =======================================================================
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//============= Possible sram sizes for a 39 bit wide memory ( 4 bytes + 7 bits ECC ) =====================================
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//-------------------------------------------------------------------------------------------------------------------------
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module ram_32768x39
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( input logic CLK,
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input logic [14:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [32767:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_32768x39
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module ram_16384x39
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( input logic CLK,
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input logic [13:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [16383:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_16384x39
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module ram_8192x39
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( input logic CLK,
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input logic [12:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [8191:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_8192x39
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module ram_4096x39
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( input logic CLK,
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input logic [11:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [4095:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_4096x39
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module ram_3072x39
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( input logic CLK,
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input logic [11:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [3071:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_3072x39
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module ram_2048x39
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( input logic CLK,
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input logic [10:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [2047:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_2048x39
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module ram_1536x39 // need this for the 48KB DCCM option
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( input logic CLK,
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input logic [10:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [1535:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_1536x39
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module ram_1024x39
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( input logic CLK,
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input logic [9:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [1023:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_1024x39
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module ram_768x39
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( input logic CLK,
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input logic [9:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [767:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_768x39
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module ram_512x39
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( input logic CLK,
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input logic [8:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [511:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_512x39
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module ram_256x39
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( input logic CLK,
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input logic [7:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [255:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_512x39
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module ram_128x39
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( input logic CLK,
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input logic [6:0] ADR,
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input logic [38:0] D,
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output logic [38:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [38:0] ram_core [127:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_128x39
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//=========================================================================================================================
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//=================================== START OF TAGS =======================================================================
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// I CACHE TAGS
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module ram_1024x20
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( input logic CLK,
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input logic [9:0] ADR,
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input logic [19:0] D,
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output logic [19:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [19:0] ram_core [1023:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_1024x20
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module ram_512x20
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( input logic CLK,
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input logic [8:0] ADR,
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input logic [19:0] D,
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output logic [19:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [19:0] ram_core [511:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_512x20
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module ram_256x20
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( input logic CLK,
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input logic [7:0] ADR,
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input logic [19:0] D,
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output logic [19:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [19:0] ram_core [255:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_256x20
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module ram_128x20
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( input logic CLK,
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input logic [6:0] ADR,
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input logic [19:0] D,
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output logic [19:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [19:0] ram_core [127:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_128x20
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module ram_64x20
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( input logic CLK,
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input logic [5:0] ADR,
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input logic [19:0] D,
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output logic [19:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [19:0] ram_core [63:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_64x20
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// LATEST ICACHE MEMORIES
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// 4096 x 34
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module ram_4096x34
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( input logic CLK,
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input logic [11:0] ADR,
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input logic [33:0] D,
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output logic [33:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [33:0] ram_core [4095:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_4096x34
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// 2048x34
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module ram_2048x34
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( input logic CLK,
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input logic [10:0] ADR,
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input logic [33:0] D,
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output logic [33:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [33:0] ram_core [2047:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_2048x34
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// 1024x34
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module ram_1024x34
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( input logic CLK,
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input logic [9:0] ADR,
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input logic [33:0] D,
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output logic [33:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [33:0] ram_core [1023:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_1024x34
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// 512x34
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module ram_512x34
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( input logic CLK,
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input logic [8:0] ADR,
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input logic [33:0] D,
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output logic [33:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [33:0] ram_core [511:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_512x34
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// 256x34
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module ram_256x34
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( input logic CLK,
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input logic [7:0] ADR,
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input logic [33:0] D,
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output logic [33:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [33:0] ram_core [255:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_256x34
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// 128x34
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module ram_128x34
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( input logic CLK,
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input logic [6:0] ADR,
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input logic [33:0] D,
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output logic [33:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [33:0] ram_core [127:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_128x34
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// 64x34
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module ram_64x34
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( input logic CLK,
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input logic [5:0] ADR,
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input logic [33:0] D,
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output logic [33:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [33:0] ram_core [63:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_64x34
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// New SRAMS for ECC; ECC on 16b boundaries
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// 4096x44
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module ram_4096x42
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( input logic CLK,
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input logic [11:0] ADR,
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input logic [41:0] D,
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output logic [41:0] Q,
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input logic WE );
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// behavior to be replaced by actual SRAM in VLE
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reg [41:0] ram_core [4095:0];
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always @(posedge CLK) begin
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if (WE) begin// for active high WE - must be specified by user
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ram_core[ADR] <= D; Q <= 'x; end else
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Q <= ram_core[ADR];
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end
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endmodule // ram_4096x42
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// 2048x44
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module ram_2048x42
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( input logic CLK,
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input logic [10:0] ADR,
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input logic [41:0] D,
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output logic [41:0] Q,
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [41:0] ram_core [2047:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
endmodule // ram_2048x42
|
|
|
|
// 1024x44
|
|
module ram_1024x42
|
|
( input logic CLK,
|
|
input logic [9:0] ADR,
|
|
input logic [41:0] D,
|
|
|
|
output logic [41:0] Q,
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [41:0] ram_core [1023:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
endmodule // ram_1024x42
|
|
|
|
|
|
// 512x44
|
|
module ram_512x42
|
|
( input logic CLK,
|
|
input logic [8:0] ADR,
|
|
input logic [41:0] D,
|
|
|
|
output logic [41:0] Q,
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [41:0] ram_core [511:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // ram_512x42
|
|
|
|
|
|
// 256x42
|
|
module ram_256x42
|
|
( input logic CLK,
|
|
input logic [7:0] ADR,
|
|
input logic [41:0] D,
|
|
|
|
output logic [41:0] Q,
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [41:0] ram_core [255:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // ram_256x42
|
|
|
|
// 128x42
|
|
module ram_128x42
|
|
( input logic CLK,
|
|
input logic [6:0] ADR,
|
|
input logic [41:0] D,
|
|
|
|
output logic [41:0] Q,
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [41:0] ram_core [127:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // ram_128x42
|
|
|
|
// 64x42
|
|
module ram_64x42
|
|
( input logic CLK,
|
|
input logic [5:0] ADR,
|
|
input logic [41:0] D,
|
|
|
|
output logic [41:0] Q,
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [41:0] ram_core [63:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
endmodule // ram_64x42
|
|
|
|
|
|
/// END DATA
|
|
|
|
// START TAGS
|
|
|
|
// 1024x21
|
|
module ram_1024x21
|
|
( input logic CLK,
|
|
input logic [9:0] ADR,
|
|
input logic [20:0] D,
|
|
|
|
output logic [20:0] Q,
|
|
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [20:0] ram_core [1023:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
endmodule // ram_1024x21
|
|
|
|
// 512x21
|
|
module ram_512x21
|
|
( input logic CLK,
|
|
input logic [8:0] ADR,
|
|
input logic [20:0] D,
|
|
|
|
output logic [20:0] Q,
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [20:0] ram_core [511:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // ram_512x21
|
|
|
|
// 256x21
|
|
module ram_256x21
|
|
( input logic CLK,
|
|
input logic [7:0] ADR,
|
|
input logic [20:0] D,
|
|
|
|
output logic [20:0] Q,
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [20:0] ram_core [255:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // ram_256x21
|
|
|
|
// 128x21
|
|
module ram_128x21
|
|
( input logic CLK,
|
|
input logic [6:0] ADR,
|
|
input logic [20:0] D,
|
|
|
|
output logic [20:0] Q,
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [20:0] ram_core [127:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // ram_128x21
|
|
|
|
// 64x21
|
|
module ram_64x21
|
|
( input logic CLK,
|
|
input logic [5:0] ADR,
|
|
input logic [20:0] D,
|
|
|
|
output logic [20:0] Q,
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [20:0] ram_core [63:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
endmodule // ram_64x21
|
|
|
|
// New tag rams for ECC.
|
|
|
|
// 1024x25
|
|
module ram_1024x25
|
|
( input logic CLK,
|
|
input logic [9:0] ADR,
|
|
input logic [24:0] D,
|
|
|
|
output logic [24:0] Q,
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [24:0] ram_core [1023:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // ram_1024x25
|
|
|
|
// 512x25
|
|
module ram_512x25
|
|
( input logic CLK,
|
|
input logic [8:0] ADR,
|
|
input logic [24:0] D,
|
|
|
|
output logic [24:0] Q,
|
|
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [24:0] ram_core [511:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // ram_512x25
|
|
|
|
// 256x25
|
|
module ram_256x25
|
|
( input logic CLK,
|
|
input logic [7:0] ADR,
|
|
input logic [24:0] D,
|
|
|
|
output logic [24:0] Q,
|
|
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [24:0] ram_core [255:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // ram_256x25
|
|
|
|
// 128x25
|
|
module ram_128x25
|
|
( input logic CLK,
|
|
input logic [6:0] ADR,
|
|
input logic [24:0] D,
|
|
|
|
output logic [24:0] Q,
|
|
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [24:0] ram_core [127:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // ram_128x25
|
|
|
|
// 64x25
|
|
module ram_64x25
|
|
( input logic CLK,
|
|
input logic [5:0] ADR,
|
|
input logic [24:0] D,
|
|
|
|
output logic [24:0] Q,
|
|
|
|
input logic WE );
|
|
|
|
// behavior to be replaced by actual SRAM in VLE
|
|
|
|
reg [24:0] ram_core [63:0];
|
|
|
|
always @(posedge CLK) begin
|
|
if (WE) begin// for active high WE - must be specified by user
|
|
ram_core[ADR] <= D; Q <= 'x; end else
|
|
Q <= ram_core[ADR];
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
endmodule // ram_64x25
|