144 lines
6.5 KiB
Systemverilog
144 lines
6.5 KiB
Systemverilog
//********************************************************************************
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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//********************************************************************************
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// Icache closely coupled memory --- ICCM
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//********************************************************************************
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module ifu_iccm_mem
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import swerv_types::*;
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(
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input logic clk,
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input logic rst_l,
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input logic clk_override,
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input logic iccm_wren,
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input logic iccm_rden,
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input logic [`RV_ICCM_BITS-1:2] iccm_rw_addr,
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input logic [2:0] iccm_wr_size,
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input logic [77:0] iccm_wr_data,
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output logic [155:0] iccm_rd_data,
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input logic scan_mode
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);
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`include "global.h"
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logic [ICCM_NUM_BANKS/4-1:0] wren_bank;
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logic [ICCM_NUM_BANKS/4-1:0] rden_bank;
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logic [ICCM_NUM_BANKS/4-1:0] iccm_hi0_clken;
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logic [ICCM_NUM_BANKS/4-1:0] iccm_hi1_clken;
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logic [ICCM_NUM_BANKS/4-1:0] iccm_lo0_clken;
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logic [ICCM_NUM_BANKS/4-1:0] iccm_lo1_clken;
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logic [ICCM_NUM_BANKS/4-1:0] iccm_hi0_clk ;
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logic [ICCM_NUM_BANKS/4-1:0] iccm_hi1_clk ;
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logic [ICCM_NUM_BANKS/4-1:0] iccm_lo0_clk ;
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logic [ICCM_NUM_BANKS/4-1:0] iccm_lo1_clk ;
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logic [ICCM_NUM_BANKS/4-1:0] wren_bank_hi0;
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logic [ICCM_NUM_BANKS/4-1:0] wren_bank_lo0;
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logic [ICCM_NUM_BANKS/4-1:0] wren_bank_hi1;
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logic [ICCM_NUM_BANKS/4-1:0] wren_bank_lo1;
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logic [ICCM_NUM_BANKS/4-1:0] [ICCM_INDEX_BITS-1:0] addr_bank;
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logic [ICCM_NUM_BANKS/4-1:0] [77:0] iccm_bank_dout_hi;
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logic [ICCM_NUM_BANKS/4-1:0] [77:0] iccm_bank_dout_lo;
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logic [5:4] iccm_rw_addr_q;
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// assign CLK = clk ;
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for (genvar i=0; i<ICCM_NUM_BANKS/4; i++) begin: mem_bank
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assign wren_bank[i] = iccm_wren & ( (iccm_rw_addr[ICCM_BANK_HI:4] == i) | (ICCM_BANK_BITS == 2));
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assign rden_bank[i] = iccm_rden & ( (iccm_rw_addr[ICCM_BANK_HI:4] == i) | (ICCM_BANK_BITS == 2));
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assign wren_bank_hi0[i] = wren_bank[i] & iccm_rw_addr[3] & (~iccm_rw_addr[2] | (iccm_wr_size[1:0] == 2'b11));
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assign wren_bank_hi1[i] = wren_bank[i] & iccm_rw_addr[3] & ( iccm_rw_addr[2] | (iccm_wr_size[1:0] == 2'b11));
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assign wren_bank_lo0[i] = wren_bank[i] & ~iccm_rw_addr[3] & (~iccm_rw_addr[2] | (iccm_wr_size[1:0] == 2'b11));
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assign wren_bank_lo1[i] = wren_bank[i] & ~iccm_rw_addr[3] & ( iccm_rw_addr[2] | (iccm_wr_size[1:0] == 2'b11));
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assign iccm_hi0_clken[i] = wren_bank_hi0[i] | (rden_bank[i] | clk_override); // Do not override the writes
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assign iccm_hi1_clken[i] = wren_bank_hi1[i] | (rden_bank[i] | clk_override); // Do not override the writes
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assign iccm_lo0_clken[i] = wren_bank_lo0[i] | (rden_bank[i] | clk_override); // Do not override the writes
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assign iccm_lo1_clken[i] = wren_bank_lo1[i] | (rden_bank[i] | clk_override); // Do not override the writes
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rvclkhdr iccm_hi0_c1_cgc ( .en(iccm_hi0_clken[i]), .l1clk(iccm_hi0_clk[i]), .* );
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rvclkhdr iccm_hi1_c1_cgc ( .en(iccm_hi1_clken[i]), .l1clk(iccm_hi1_clk[i]), .* );
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rvclkhdr iccm_lo0_c1_cgc ( .en(iccm_lo0_clken[i]), .l1clk(iccm_lo0_clk[i]), .* );
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rvclkhdr iccm_lo1_c1_cgc ( .en(iccm_lo1_clken[i]), .l1clk(iccm_lo1_clk[i]), .* );
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assign addr_bank[i][ICCM_INDEX_BITS-1:0] = iccm_rw_addr[ICCM_BITS-1:(ICCM_BANK_BITS+2)];
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`RV_ICCM_DATA_CELL iccm_bank_hi0 (
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// Primary ports
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.CLK(iccm_hi0_clk[i]),
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.WE(wren_bank_hi0[i]),
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.ADR(addr_bank[i]),
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.D(iccm_wr_data[38:0]),
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.Q(iccm_bank_dout_hi[i][38:0])
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);
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`RV_ICCM_DATA_CELL iccm_bank_hi1 (
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// Primary ports
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.CLK(iccm_hi1_clk[i]),
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.WE(wren_bank_hi1[i]),
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.ADR(addr_bank[i]),
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.D(iccm_wr_data[77:39]),
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.Q(iccm_bank_dout_hi[i][77:39])
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);
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`RV_ICCM_DATA_CELL iccm_bank_lo0 (
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// Primary ports
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.CLK(iccm_lo0_clk[i]),
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.WE(wren_bank_lo0[i]),
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.ADR(addr_bank[i]),
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.D(iccm_wr_data[38:0]),
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.Q(iccm_bank_dout_lo[i][38:0])
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);
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`RV_ICCM_DATA_CELL iccm_bank_lo1 (
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// Primary ports
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.CLK(iccm_lo1_clk[i]),
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.WE(wren_bank_lo1[i]),
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.ADR(addr_bank[i]),
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.D(iccm_wr_data[77:39]),
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.Q(iccm_bank_dout_lo[i][77:39])
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);
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end : mem_bank
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assign iccm_rd_data[155:0] = (ICCM_BANK_BITS == 2) ? {iccm_bank_dout_hi[0][77:0], iccm_bank_dout_lo[0][77:0]} :
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{ iccm_bank_dout_hi[iccm_rw_addr_q[ICCM_BANK_HI:4]][77:0], iccm_bank_dout_lo[iccm_rw_addr_q[ICCM_BANK_HI:4]][77:0] };
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if (ICCM_BANK_BITS == 2) begin
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assign iccm_rw_addr_q[5:4] = '0;
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end
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// 8 banks, each bank 8B, we index as 4 banks
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else begin
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rvdff #(2) rd_addr_ff (.*, .din(iccm_rw_addr[5:4]), .dout(iccm_rw_addr_q[5:4]) );
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end
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endmodule // ifu_iccm_mem
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