abstractaccelerator/VexRiscv/fpga/gen/synth.log

9321 lines
578 KiB
Plaintext

/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.13+28 (git sha1 fc40df091, gcc 11.2.0-7ubuntu2 -fPIC -Os)
-- Executing script file `gen/synth.ys' --
1. Executing Verilog-2005 frontend: ../Murax.v
Parsing Verilog input from `../Murax.v' to AST representation.
Generating RTLIL representation for module `\Murax'.
Generating RTLIL representation for module `\Apb3Router'.
Generating RTLIL representation for module `\Apb3Decoder'.
Generating RTLIL representation for module `\MuraxApb3Timer'.
Generating RTLIL representation for module `\Apb3UartCtrl'.
Generating RTLIL representation for module `\Apb3Gpio'.
Generating RTLIL representation for module `\PipelinedMemoryBusToApbBridge'.
Generating RTLIL representation for module `\MuraxPipelinedMemoryBusRam'.
Generating RTLIL representation for module `\SystemDebugger'.
Generating RTLIL representation for module `\JtagBridge'.
Generating RTLIL representation for module `\VexRiscv'.
Generating RTLIL representation for module `\MuraxMasterArbiter'.
Generating RTLIL representation for module `\BufferCC_3'.
Generating RTLIL representation for module `\InterruptCtrl'.
Generating RTLIL representation for module `\Timer'.
Generating RTLIL representation for module `\Prescaler'.
Generating RTLIL representation for module `\StreamFifo'.
Generating RTLIL representation for module `\UartCtrl'.
Generating RTLIL representation for module `\BufferCC_2'.
Generating RTLIL representation for module `\FlowCCByToggle'.
Generating RTLIL representation for module `\StreamFifoLowLatency'.
Generating RTLIL representation for module `\UartCtrlRx'.
Generating RTLIL representation for module `\UartCtrlTx'.
Generating RTLIL representation for module `\BufferCC_1'.
Generating RTLIL representation for module `\BufferCC'.
Successfully finished Verilog frontend.
2. Executing HIERARCHY pass (managing design hierarchy).
2.1. Analyzing design hierarchy..
Top module: \Murax
Used module: \Apb3Router
Used module: \Apb3Decoder
Used module: \MuraxApb3Timer
Used module: \InterruptCtrl
Used module: \Timer
Used module: \Prescaler
Used module: \Apb3UartCtrl
Used module: \StreamFifo
Used module: \UartCtrl
Used module: \UartCtrlRx
Used module: \BufferCC
Used module: \UartCtrlTx
Used module: \Apb3Gpio
Used module: \BufferCC_2
Used module: \PipelinedMemoryBusToApbBridge
Used module: \MuraxPipelinedMemoryBusRam
Used module: \SystemDebugger
Used module: \JtagBridge
Used module: \FlowCCByToggle
Used module: \BufferCC_1
Used module: \VexRiscv
Used module: \StreamFifoLowLatency
Used module: \MuraxMasterArbiter
Used module: \BufferCC_3
2.2. Analyzing design hierarchy..
Top module: \Murax
Used module: \Apb3Router
Used module: \Apb3Decoder
Used module: \MuraxApb3Timer
Used module: \InterruptCtrl
Used module: \Timer
Used module: \Prescaler
Used module: \Apb3UartCtrl
Used module: \StreamFifo
Used module: \UartCtrl
Used module: \UartCtrlRx
Used module: \BufferCC
Used module: \UartCtrlTx
Used module: \Apb3Gpio
Used module: \BufferCC_2
Used module: \PipelinedMemoryBusToApbBridge
Used module: \MuraxPipelinedMemoryBusRam
Used module: \SystemDebugger
Used module: \JtagBridge
Used module: \FlowCCByToggle
Used module: \BufferCC_1
Used module: \VexRiscv
Used module: \StreamFifoLowLatency
Used module: \MuraxMasterArbiter
Used module: \BufferCC_3
Removed 0 unused modules.
3. Executing SYNTH pass.
3.1. Executing PROC pass (convert processes to netlists).
3.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `FlowCCByToggle.$proc$../Murax.v:0$942'.
Removing empty process `JtagBridge.$proc$../Murax.v:0$263'.
Cleaned up 0 empty switches.
3.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$../Murax.v:6826$1043 in module BufferCC.
Marked 3 switch rules as full_case in process $proc$../Murax.v:6714$1034 in module UartCtrlTx.
Marked 3 switch rules as full_case in process $proc$../Murax.v:6688$1027 in module UartCtrlTx.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6669$1025 in module UartCtrlTx.
Marked 2 switch rules as full_case in process $proc$../Murax.v:6658$1023 in module UartCtrlTx.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6648$1020 in module UartCtrlTx.
Marked 2 switch rules as full_case in process $proc$../Murax.v:6519$998 in module UartCtrlRx.
Marked 6 switch rules as full_case in process $proc$../Murax.v:6440$985 in module UartCtrlRx.
Marked 2 switch rules as full_case in process $proc$../Murax.v:6418$970 in module UartCtrlRx.
Marked 5 switch rules as full_case in process $proc$../Murax.v:6389$968 in module UartCtrlRx.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6270$962 in module StreamFifoLowLatency.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6259$959 in module StreamFifoLowLatency.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6251$958 in module StreamFifoLowLatency.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6243$957 in module StreamFifoLowLatency.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6224$948 in module StreamFifoLowLatency.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6217$947 in module StreamFifoLowLatency.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6208$945 in module StreamFifoLowLatency.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6201$944 in module StreamFifoLowLatency.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6194$943 in module StreamFifoLowLatency.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6145$941 in module FlowCCByToggle.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6049$934 in module UartCtrl.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6035$933 in module UartCtrl.
Marked 1 switch rules as full_case in process $proc$../Murax.v:6028$932 in module UartCtrl.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5914$929 in module StreamFifo.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5895$910 in module StreamFifo.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5886$907 in module StreamFifo.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5879$906 in module StreamFifo.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5872$904 in module StreamFifo.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5863$901 in module StreamFifo.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5856$900 in module StreamFifo.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5849$899 in module StreamFifo.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5843$892 in module StreamFifo.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5735$881 in module Timer.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5701$872 in module InterruptCtrl.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5653$869 in module MuraxMasterArbiter.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5637$860 in module MuraxMasterArbiter.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5630$857 in module MuraxMasterArbiter.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5615$855 in module MuraxMasterArbiter.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5605$851 in module MuraxMasterArbiter.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5502$850 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5018$829 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:5007$821 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4998$820 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4989$819 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4980$818 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4963$811 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$../Murax.v:4841$690 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4829$688 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$../Murax.v:4814$687 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4794$679 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4714$673 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4697$670 in module VexRiscv.
Marked 12 switch rules as full_case in process $proc$../Murax.v:4642$648 in module VexRiscv.
Marked 12 switch rules as full_case in process $proc$../Murax.v:4609$647 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4596$643 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4583$632 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4566$631 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4501$628 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4487$627 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4473$623 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4466$622 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4459$621 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4452$619 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4411$589 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4399$581 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4392$578 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$../Murax.v:4381$574 in module VexRiscv.
Marked 8 switch rules as full_case in process $proc$../Murax.v:4354$573 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4337$560 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4326$559 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4316$556 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4291$537 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4276$535 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4208$528 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4191$520 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4175$512 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4165$502 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4138$493 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4102$477 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$../Murax.v:4073$461 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4045$447 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4026$438 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4017$436 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:4007$431 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3998$428 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3987$424 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3980$423 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3973$422 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3966$421 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$../Murax.v:3950$420 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$../Murax.v:3940$419 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3933$418 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$../Murax.v:3920$417 in module VexRiscv.
Marked 6 switch rules as full_case in process $proc$../Murax.v:3899$416 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$../Murax.v:3885$415 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3877$414 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3868$413 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3860$412 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3852$411 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$../Murax.v:3843$410 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$../Murax.v:3834$409 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3827$408 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3820$407 in module VexRiscv.
Marked 5 switch rules as full_case in process $proc$../Murax.v:3803$406 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3794$405 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$../Murax.v:3781$404 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3770$403 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3759$402 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3741$401 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$../Murax.v:3724$400 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3717$399 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3709$397 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$../Murax.v:3102$374 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$../Murax.v:1995$235 in module JtagBridge.
Marked 2 switch rules as full_case in process $proc$../Murax.v:1977$234 in module JtagBridge.
Marked 1 switch rules as full_case in process $proc$../Murax.v:1923$217 in module JtagBridge.
Marked 1 switch rules as full_case in process $proc$../Murax.v:1718$213 in module SystemDebugger.
Marked 1 switch rules as full_case in process $proc$../Murax.v:1692$211 in module SystemDebugger.
Marked 1 switch rules as full_case in process $proc$../Murax.v:1633$198 in module MuraxPipelinedMemoryBusRam.
Marked 4 switch rules as full_case in process $proc$../Murax.v:1612$163 in module MuraxPipelinedMemoryBusRam.
Marked 2 switch rules as full_case in process $proc$../Murax.v:1534$151 in module PipelinedMemoryBusToApbBridge.
Marked 2 switch rules as full_case in process $proc$../Murax.v:1523$147 in module PipelinedMemoryBusToApbBridge.
Marked 2 switch rules as full_case in process $proc$../Murax.v:1509$145 in module PipelinedMemoryBusToApbBridge.
Marked 1 switch rules as full_case in process $proc$../Murax.v:1417$141 in module Apb3Gpio.
Marked 1 switch rules as full_case in process $proc$../Murax.v:1393$128 in module Apb3Gpio.
Marked 1 switch rules as full_case in process $proc$../Murax.v:1297$126 in module Apb3UartCtrl.
Marked 2 switch rules as full_case in process $proc$../Murax.v:1282$125 in module Apb3UartCtrl.
Marked 2 switch rules as full_case in process $proc$../Murax.v:1268$124 in module Apb3UartCtrl.
Marked 2 switch rules as full_case in process $proc$../Murax.v:1254$123 in module Apb3UartCtrl.
Marked 2 switch rules as full_case in process $proc$../Murax.v:1238$118 in module Apb3UartCtrl.
Marked 2 switch rules as full_case in process $proc$../Murax.v:1224$117 in module Apb3UartCtrl.
Marked 2 switch rules as full_case in process $proc$../Murax.v:1208$112 in module Apb3UartCtrl.
Marked 1 switch rules as full_case in process $proc$../Murax.v:1200$111 in module Apb3UartCtrl.
Marked 1 switch rules as full_case in process $proc$../Murax.v:1193$110 in module Apb3UartCtrl.
Marked 2 switch rules as full_case in process $proc$../Murax.v:1177$109 in module Apb3UartCtrl.
Marked 1 switch rules as full_case in process $proc$../Murax.v:1141$94 in module Apb3UartCtrl.
Marked 1 switch rules as full_case in process $proc$../Murax.v:920$90 in module MuraxApb3Timer.
Marked 2 switch rules as full_case in process $proc$../Murax.v:901$87 in module MuraxApb3Timer.
Marked 2 switch rules as full_case in process $proc$../Murax.v:886$81 in module MuraxApb3Timer.
Marked 2 switch rules as full_case in process $proc$../Murax.v:873$80 in module MuraxApb3Timer.
Marked 2 switch rules as full_case in process $proc$../Murax.v:863$79 in module MuraxApb3Timer.
Marked 2 switch rules as full_case in process $proc$../Murax.v:848$73 in module MuraxApb3Timer.
Marked 2 switch rules as full_case in process $proc$../Murax.v:835$72 in module MuraxApb3Timer.
Marked 2 switch rules as full_case in process $proc$../Murax.v:825$71 in module MuraxApb3Timer.
Marked 2 switch rules as full_case in process $proc$../Murax.v:812$70 in module MuraxApb3Timer.
Marked 1 switch rules as full_case in process $proc$../Murax.v:770$57 in module MuraxApb3Timer.
Marked 1 switch rules as full_case in process $proc$../Murax.v:679$54 in module Apb3Decoder.
Marked 1 switch rules as full_case in process $proc$../Murax.v:671$53 in module Apb3Decoder.
Marked 1 switch rules as full_case in process $proc$../Murax.v:593$41 in module Apb3Router.
Marked 1 switch rules as full_case in process $proc$../Murax.v:538$39 in module Murax.
Marked 1 switch rules as full_case in process $proc$../Murax.v:497$36 in module Murax.
Marked 1 switch rules as full_case in process $proc$../Murax.v:467$19 in module Murax.
Marked 1 switch rules as full_case in process $proc$../Murax.v:458$15 in module Murax.
Marked 1 switch rules as full_case in process $proc$../Murax.v:449$11 in module Murax.
Marked 1 switch rules as full_case in process $proc$../Murax.v:419$5 in module Murax.
Marked 1 switch rules as full_case in process $proc$../Murax.v:412$4 in module Murax.
Marked 1 switch rules as full_case in process $proc$../Murax.v:402$2 in module Murax.
Marked 1 switch rules as full_case in process $proc$../Murax.v:395$1 in module Murax.
Removed a total of 0 dead cases.
3.1.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 28 redundant assignments.
Promoted 341 assignments to connections.
3.1.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\Murax.$proc$../Murax.v:0$40'.
Set init value: \resetCtrl_systemClkResetCounter = 6'000000
3.1.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \resetCtrl_systemReset in `\BufferCC.$proc$../Murax.v:6826$1043'.
Found async reset \resetCtrl_systemReset in `\UartCtrlTx.$proc$../Murax.v:6714$1034'.
Found async reset \resetCtrl_systemReset in `\UartCtrlRx.$proc$../Murax.v:6440$985'.
Found async reset \resetCtrl_systemReset in `\StreamFifoLowLatency.$proc$../Murax.v:6270$962'.
Found async reset \resetCtrl_mainClkReset in `\FlowCCByToggle.$proc$../Murax.v:6145$941'.
Found async reset \resetCtrl_systemReset in `\UartCtrl.$proc$../Murax.v:6049$934'.
Found async reset \resetCtrl_systemReset in `\StreamFifo.$proc$../Murax.v:5914$929'.
Found async reset \resetCtrl_systemReset in `\Timer.$proc$../Murax.v:5735$881'.
Found async reset \resetCtrl_systemReset in `\InterruptCtrl.$proc$../Murax.v:5701$872'.
Found async reset \resetCtrl_systemReset in `\MuraxMasterArbiter.$proc$../Murax.v:5653$869'.
Found async reset \resetCtrl_mainClkReset in `\VexRiscv.$proc$../Murax.v:5502$850'.
Found async reset \resetCtrl_systemReset in `\VexRiscv.$proc$../Murax.v:5018$829'.
Found async reset \resetCtrl_mainClkReset in `\SystemDebugger.$proc$../Murax.v:1692$211'.
Found async reset \resetCtrl_systemReset in `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1633$198'.
Found async reset \resetCtrl_systemReset in `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'.
Found async reset \resetCtrl_systemReset in `\Apb3Gpio.$proc$../Murax.v:1417$141'.
Found async reset \resetCtrl_systemReset in `\Apb3UartCtrl.$proc$../Murax.v:1297$126'.
Found async reset \resetCtrl_systemReset in `\MuraxApb3Timer.$proc$../Murax.v:920$90'.
Found async reset \resetCtrl_mainClkReset in `\Murax.$proc$../Murax.v:538$39'.
Found async reset \resetCtrl_systemReset in `\Murax.$proc$../Murax.v:497$36'.
3.1.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\BufferCC.$proc$../Murax.v:6826$1043'.
1/2: $0\buffers_1[0:0]
2/2: $0\buffers_0[0:0]
Creating decoders for process `\BufferCC_1.$proc$../Murax.v:6807$1042'.
Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6760$1038'.
1/2: $0\tickCounter_value[2:0]
2/2: $0\stateMachine_parity[0:0]
Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6714$1034'.
1/3: $0\_zz_io_txd[0:0]
2/3: $0\clockDivider_counter_value[2:0]
3/3: $0\stateMachine_state[2:0]
Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6688$1027'.
1/3: $3\io_write_ready[0:0]
2/3: $2\io_write_ready[0:0]
3/3: $1\io_write_ready[0:0]
Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6669$1025'.
1/1: $1\stateMachine_txd[0:0]
Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6658$1023'.
1/2: $2\clockDivider_counter_valueNext[2:0]
2/2: $1\clockDivider_counter_valueNext[2:0]
Creating decoders for process `\UartCtrlTx.$proc$../Murax.v:6648$1020'.
1/1: $1\clockDivider_counter_willIncrement[0:0]
Creating decoders for process `\UartCtrlRx.$proc$../Murax.v:6519$998'.
1/9: $2$lookahead\stateMachine_shifter$997[7:0]$1011
2/9: $2$bitselwrite$data$../Murax.v:6546$965[7:0]$1010
3/9: $2$bitselwrite$mask$../Murax.v:6546$964[7:0]$1009
4/9: $1$lookahead\stateMachine_shifter$997[7:0]$1007
5/9: $1$bitselwrite$data$../Murax.v:6546$965[7:0]$1006
6/9: $1$bitselwrite$mask$../Murax.v:6546$964[7:0]$1005
7/9: $0\stateMachine_parity[0:0]
8/9: $0\bitCounter_value[2:0]
9/9: $0\bitTimer_counter[2:0]
Creating decoders for process `\UartCtrlRx.$proc$../Murax.v:6440$985'.
1/8: $0\stateMachine_validReg[0:0]
2/8: $0\sampler_tick[0:0]
3/8: $0\sampler_value[0:0]
4/8: $0\_zz_io_rts[0:0]
5/8: $0\stateMachine_state[2:0]
6/8: $0\break_counter[6:0]
7/8: $0\sampler_samples_2[0:0]
8/8: $0\sampler_samples_1[0:0]
Creating decoders for process `\UartCtrlRx.$proc$../Murax.v:6418$970'.
1/2: $2\bitTimer_tick[0:0]
2/2: $1\bitTimer_tick[0:0]
Creating decoders for process `\UartCtrlRx.$proc$../Murax.v:6389$968'.
1/5: $5\io_error[0:0]
2/5: $4\io_error[0:0]
3/5: $3\io_error[0:0]
4/5: $2\io_error[0:0]
5/5: $1\io_error[0:0]
Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6283$963'.
1/1: $0\_zz_readed_error_2[32:0]
Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6270$962'.
1/1: $0\risingOccupancy[0:0]
Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6259$959'.
1/1: $1\io_pop_payload_inst[31:0]
Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6251$958'.
1/1: $1\io_pop_payload_error[0:0]
Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6243$957'.
1/1: $1\io_pop_valid[0:0]
Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6224$948'.
1/1: $1\popPtr_willClear[0:0]
Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6217$947'.
1/1: $1\popPtr_willIncrement[0:0]
Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6208$945'.
1/1: $1\pushPtr_willClear[0:0]
Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6201$944'.
1/1: $1\pushPtr_willIncrement[0:0]
Creating decoders for process `\StreamFifoLowLatency.$proc$../Murax.v:6194$943'.
1/1: $1\when_Phase_l623[0:0]
Creating decoders for process `\FlowCCByToggle.$proc$../Murax.v:6145$941'.
1/1: $0\outputArea_flow_m2sPipe_valid[0:0]
Creating decoders for process `\FlowCCByToggle.$proc$../Murax.v:6137$940'.
1/2: $0\outputArea_flow_m2sPipe_payload_fragment[0:0]
2/2: $0\outputArea_flow_m2sPipe_payload_last[0:0]
Creating decoders for process `\FlowCCByToggle.$proc$../Murax.v:6129$938'.
1/3: $0\inputArea_data_fragment[0:0]
2/3: $0\inputArea_data_last[0:0]
3/3: $0\inputArea_target[0:0]
Creating decoders for process `\BufferCC_2.$proc$../Murax.v:6076$936'.
Creating decoders for process `\UartCtrl.$proc$../Murax.v:6049$934'.
1/2: $0\clockDivider_counter[19:0]
2/2: $0\clockDivider_tickReg[0:0]
Creating decoders for process `\UartCtrl.$proc$../Murax.v:6035$933'.
1/1: $1\io_write_ready[0:0]
Creating decoders for process `\UartCtrl.$proc$../Murax.v:6028$932'.
1/1: $1\io_write_thrown_valid[0:0]
Creating decoders for process `\StreamFifo.$proc$../Murax.v:5914$929'.
1/4: $0\_zz_io_pop_valid[0:0]
2/4: $0\logic_popPtr_value[3:0]
3/4: $0\logic_pushPtr_value[3:0]
4/4: $0\logic_risingOccupancy[0:0]
Creating decoders for process `\StreamFifo.$proc$../Murax.v:5895$910'.
1/1: $1\logic_popPtr_valueNext[3:0]
Creating decoders for process `\StreamFifo.$proc$../Murax.v:5886$907'.
1/1: $1\logic_popPtr_willClear[0:0]
Creating decoders for process `\StreamFifo.$proc$../Murax.v:5879$906'.
1/1: $1\logic_popPtr_willIncrement[0:0]
Creating decoders for process `\StreamFifo.$proc$../Murax.v:5872$904'.
1/1: $1\logic_pushPtr_valueNext[3:0]
Creating decoders for process `\StreamFifo.$proc$../Murax.v:5863$901'.
1/1: $1\logic_pushPtr_willClear[0:0]
Creating decoders for process `\StreamFifo.$proc$../Murax.v:5856$900'.
1/1: $1\logic_pushPtr_willIncrement[0:0]
Creating decoders for process `\StreamFifo.$proc$../Murax.v:5849$899'.
1/1: $1\_zz_1[0:0]
Creating decoders for process `\StreamFifo.$proc$../Murax.v:5843$892'.
1/3: $1$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$898
2/3: $1$memwr$\logic_ram$../Murax.v:5845$888_DATA[7:0]$897
3/3: $1$memwr$\logic_ram$../Murax.v:5845$888_ADDR[3:0]$896
Creating decoders for process `\StreamFifo.$proc$../Murax.v:5837$890'.
1/1: $0\_zz_logic_ram_port0[7:0]
Creating decoders for process `\Prescaler.$proc$../Murax.v:5773$886'.
1/1: $0\counter[15:0]
Creating decoders for process `\Timer.$proc$../Murax.v:5748$882'.
1/1: $0\counter[15:0]
Creating decoders for process `\Timer.$proc$../Murax.v:5735$881'.
1/1: $0\inhibitFull[0:0]
Creating decoders for process `\InterruptCtrl.$proc$../Murax.v:5701$872'.
1/1: $0\pendings[1:0]
Creating decoders for process `\BufferCC_3.$proc$../Murax.v:5681$870'.
Creating decoders for process `\MuraxMasterArbiter.$proc$../Murax.v:5653$869'.
1/2: $0\rspTarget[0:0]
2/2: $0\rspPending[0:0]
Creating decoders for process `\MuraxMasterArbiter.$proc$../Murax.v:5637$860'.
1/1: $1\io_dBus_cmd_ready[0:0]
Creating decoders for process `\MuraxMasterArbiter.$proc$../Murax.v:5630$857'.
1/1: $1\io_iBus_cmd_ready[0:0]
Creating decoders for process `\MuraxMasterArbiter.$proc$../Murax.v:5615$855'.
1/1: $1\_zz_io_masterBus_cmd_payload_mask[3:0]
Creating decoders for process `\MuraxMasterArbiter.$proc$../Murax.v:5605$851'.
1/1: $1\io_masterBus_cmd_valid[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:5502$850'.
1/7: $0\DebugPlugin_disableEbreak[0:0]
2/7: $0\DebugPlugin_debugUsed[0:0]
3/7: $0\DebugPlugin_haltedByBreak[0:0]
4/7: $0\DebugPlugin_godmode[0:0]
5/7: $0\DebugPlugin_stepIt[0:0]
6/7: $0\DebugPlugin_haltIt[0:0]
7/7: $0\DebugPlugin_resetIt[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:5485$847'.
1/2: $0\DebugPlugin_firstCycle[0:0]
2/2: $0\DebugPlugin_busReadDataReg[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:5280$840'.
1/62: $0\CsrPlugin_mip_MSIP[0:0]
2/62: $0\execute_CsrPlugin_csr_834[0:0]
3/62: $0\execute_CsrPlugin_csr_772[0:0]
4/62: $0\execute_CsrPlugin_csr_836[0:0]
5/62: $0\execute_CsrPlugin_csr_768[0:0]
6/62: $0\memory_to_writeBack_MEMORY_READ_DATA[31:0]
7/62: $0\execute_to_memory_BRANCH_CALC[31:0]
8/62: $0\execute_to_memory_BRANCH_DO[0:0]
9/62: $0\memory_to_writeBack_REGFILE_WRITE_DATA[31:0]
10/62: $0\execute_to_memory_REGFILE_WRITE_DATA[31:0]
11/62: $0\memory_to_writeBack_MEMORY_ADDRESS_LOW[1:0]
12/62: $0\execute_to_memory_MEMORY_ADDRESS_LOW[1:0]
13/62: $0\decode_to_execute_DO_EBREAK[0:0]
14/62: $0\decode_to_execute_SRC2[31:0]
15/62: $0\decode_to_execute_SRC1[31:0]
16/62: $0\decode_to_execute_SRC2_FORCE_ZERO[0:0]
17/62: $0\decode_to_execute_RS2[31:0]
18/62: $0\decode_to_execute_RS1[31:0]
19/62: $0\decode_to_execute_BRANCH_CTRL[1:0]
20/62: $0\decode_to_execute_SHIFT_CTRL[1:0]
21/62: $0\decode_to_execute_ALU_BITWISE_CTRL[1:0]
22/62: $0\decode_to_execute_SRC_LESS_UNSIGNED[0:0]
23/62: $0\decode_to_execute_ALU_CTRL[1:0]
24/62: $0\memory_to_writeBack_ENV_CTRL[0:0]
25/62: $0\execute_to_memory_ENV_CTRL[0:0]
26/62: $0\decode_to_execute_ENV_CTRL[0:0]
27/62: $0\decode_to_execute_IS_CSR[0:0]
28/62: $0\execute_to_memory_MEMORY_STORE[0:0]
29/62: $0\decode_to_execute_MEMORY_STORE[0:0]
30/62: $0\execute_to_memory_BYPASSABLE_MEMORY_STAGE[0:0]
31/62: $0\decode_to_execute_BYPASSABLE_MEMORY_STAGE[0:0]
32/62: $0\decode_to_execute_BYPASSABLE_EXECUTE_STAGE[0:0]
33/62: $0\memory_to_writeBack_REGFILE_WRITE_VALID[0:0]
34/62: $0\execute_to_memory_REGFILE_WRITE_VALID[0:0]
35/62: $0\decode_to_execute_REGFILE_WRITE_VALID[0:0]
36/62: $0\memory_to_writeBack_MEMORY_ENABLE[0:0]
37/62: $0\execute_to_memory_MEMORY_ENABLE[0:0]
38/62: $0\decode_to_execute_MEMORY_ENABLE[0:0]
39/62: $0\decode_to_execute_SRC_USE_SUB_LESS[0:0]
40/62: $0\decode_to_execute_CSR_READ_OPCODE[0:0]
41/62: $0\decode_to_execute_CSR_WRITE_OPCODE[0:0]
42/62: $0\memory_to_writeBack_FORMAL_PC_NEXT[31:0]
43/62: $0\execute_to_memory_FORMAL_PC_NEXT[31:0]
44/62: $0\decode_to_execute_FORMAL_PC_NEXT[31:0]
45/62: $0\memory_to_writeBack_INSTRUCTION[31:0]
46/62: $0\execute_to_memory_INSTRUCTION[31:0]
47/62: $0\decode_to_execute_INSTRUCTION[31:0]
48/62: $0\memory_to_writeBack_PC[31:0]
49/62: $0\execute_to_memory_PC[31:0]
50/62: $0\decode_to_execute_PC[31:0]
51/62: $0\execute_LightShifterPlugin_amplitudeReg[4:0]
52/62: $0\CsrPlugin_interrupt_targetPrivilege[1:0]
53/62: $0\CsrPlugin_interrupt_code[3:0]
54/62: $0\CsrPlugin_mcause_exceptionCode[3:0]
55/62: $0\CsrPlugin_mcause_interrupt[0:0]
56/62: $0\CsrPlugin_mepc[31:0]
57/62: $0\IBusSimplePlugin_injector_formal_rawInDecode[31:0]
58/62: $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc[0:0]
59/62: $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0]
60/62: $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error[0:0]
61/62: $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:0]
62/62: $0\_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:5018$829'.
1/36: $0\HazardSimplePlugin_writeBackBuffer_valid[0:0]
2/36: $0\_zz_2[0:0]
3/36: $0\execute_CsrPlugin_wfiWake[0:0]
4/36: $0\CsrPlugin_hadException[0:0]
5/36: $0\CsrPlugin_interrupt_valid[0:0]
6/36: $0\CsrPlugin_mcycle[63:0]
7/36: $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0]
8/36: $0\IBusSimplePlugin_pending_value[2:0]
9/36: $0\IBusSimplePlugin_fetchPc_booted[0:0]
10/36: $0\switch_Fetcher_l362[2:0]
11/36: $0\execute_LightShifterPlugin_isActive[0:0]
12/36: $0\CsrPlugin_pipelineLiberator_pcValids_2[0:0]
13/36: $0\CsrPlugin_pipelineLiberator_pcValids_1[0:0]
14/36: $0\CsrPlugin_pipelineLiberator_pcValids_0[0:0]
15/36: $0\CsrPlugin_minstret[63:0]
16/36: $0\CsrPlugin_mie_MSIE[0:0]
17/36: $0\CsrPlugin_mie_MTIE[0:0]
18/36: $0\CsrPlugin_mie_MEIE[0:0]
19/36: $0\CsrPlugin_mstatus_MPP[1:0]
20/36: $0\CsrPlugin_mstatus_MPIE[0:0]
21/36: $0\CsrPlugin_mstatus_MIE[0:0]
22/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_5[0:0]
23/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_4[0:0]
24/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_3[0:0]
25/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_2[0:0]
26/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_1[0:0]
27/36: $0\IBusSimplePlugin_injector_nextPcCalc_valids_0[0:0]
28/36: $0\_zz_IBusSimplePlugin_injector_decodeInput_valid[0:0]
29/36: $0\_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid[0:0]
30/36: $0\_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2[0:0]
31/36: $0\IBusSimplePlugin_fetchPc_inc[0:0]
32/36: $0\IBusSimplePlugin_fetchPc_correctionReg[0:0]
33/36: $0\IBusSimplePlugin_fetchPc_pcReg[31:0]
34/36: $0\writeBack_arbitration_isValid[0:0]
35/36: $0\memory_arbitration_isValid[0:0]
36/36: $0\execute_arbitration_isValid[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:5007$821'.
1/2: $1\_zz_CsrPlugin_csrMapping_readDataInit_3[3:0]
2/2: $2\_zz_CsrPlugin_csrMapping_readDataInit_3[31:31]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4998$820'.
1/3: $1\_zz_CsrPlugin_csrMapping_readDataInit_2[3:3]
2/3: $2\_zz_CsrPlugin_csrMapping_readDataInit_2[7:7]
3/3: $3\_zz_CsrPlugin_csrMapping_readDataInit_2[11:11]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4989$819'.
1/3: $1\_zz_CsrPlugin_csrMapping_readDataInit_1[3:3]
2/3: $2\_zz_CsrPlugin_csrMapping_readDataInit_1[7:7]
3/3: $3\_zz_CsrPlugin_csrMapping_readDataInit_1[11:11]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4980$818'.
1/3: $1\_zz_CsrPlugin_csrMapping_readDataInit[3:3]
2/3: $2\_zz_CsrPlugin_csrMapping_readDataInit[7:7]
3/3: $3\_zz_CsrPlugin_csrMapping_readDataInit[12:11]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4963$811'.
1/1: $1\IBusSimplePlugin_injectionPort_ready[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4841$690'.
1/3: $3\IBusSimplePlugin_injectionPort_valid[0:0]
2/3: $2\IBusSimplePlugin_injectionPort_valid[0:0]
3/3: $1\IBusSimplePlugin_injectionPort_valid[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4829$688'.
1/5: $1\debug_bus_rsp_data[4:0] [4]
2/5: $1\debug_bus_rsp_data[4:0] [2]
3/5: $1\debug_bus_rsp_data[4:0] [1]
4/5: $1\debug_bus_rsp_data[4:0] [0]
5/5: $1\debug_bus_rsp_data[4:0] [3]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4814$687'.
1/3: $3\debug_bus_cmd_ready[0:0]
2/3: $2\debug_bus_cmd_ready[0:0]
3/3: $1\debug_bus_cmd_ready[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4794$679'.
1/1: $1\_zz_execute_BranchPlugin_branch_src2_6[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4772$678'.
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4748$677'.
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4733$676'.
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4714$673'.
1/1: $1\_zz_execute_BRANCH_DO_1[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4697$670'.
1/1: $1\_zz_execute_BRANCH_DO[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4642$648'.
1/12: $12\HazardSimplePlugin_src1Hazard[0:0]
2/12: $11\HazardSimplePlugin_src1Hazard[0:0]
3/12: $10\HazardSimplePlugin_src1Hazard[0:0]
4/12: $9\HazardSimplePlugin_src1Hazard[0:0]
5/12: $8\HazardSimplePlugin_src1Hazard[0:0]
6/12: $7\HazardSimplePlugin_src1Hazard[0:0]
7/12: $6\HazardSimplePlugin_src1Hazard[0:0]
8/12: $5\HazardSimplePlugin_src1Hazard[0:0]
9/12: $4\HazardSimplePlugin_src1Hazard[0:0]
10/12: $3\HazardSimplePlugin_src1Hazard[0:0]
11/12: $2\HazardSimplePlugin_src1Hazard[0:0]
12/12: $1\HazardSimplePlugin_src1Hazard[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4609$647'.
1/12: $12\HazardSimplePlugin_src0Hazard[0:0]
2/12: $11\HazardSimplePlugin_src0Hazard[0:0]
3/12: $10\HazardSimplePlugin_src0Hazard[0:0]
4/12: $9\HazardSimplePlugin_src0Hazard[0:0]
5/12: $8\HazardSimplePlugin_src0Hazard[0:0]
6/12: $7\HazardSimplePlugin_src0Hazard[0:0]
7/12: $6\HazardSimplePlugin_src0Hazard[0:0]
8/12: $5\HazardSimplePlugin_src0Hazard[0:0]
9/12: $4\HazardSimplePlugin_src0Hazard[0:0]
10/12: $3\HazardSimplePlugin_src0Hazard[0:0]
11/12: $2\HazardSimplePlugin_src0Hazard[0:0]
12/12: $1\HazardSimplePlugin_src0Hazard[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4596$643'.
1/1: $1\_zz_execute_to_memory_REGFILE_WRITE_DATA_1[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4583$632'.
1/1: $1\execute_SrcPlugin_addSub[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4566$631'.
1/1: $1\_zz_decode_SRC2_6[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4543$630'.
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4519$629'.
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4501$628'.
1/1: $1\_zz_decode_SRC1_1[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4487$627'.
1/1: $1\_zz_execute_REGFILE_WRITE_DATA[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4473$623'.
1/1: $1\execute_IntAluPlugin_bitwise[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4466$622'.
1/1: $1\lastStageRegFileWrite_payload_data[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4459$621'.
1/1: $1\lastStageRegFileWrite_payload_address[4:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4452$619'.
1/1: $1\lastStageRegFileWrite_valid[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4411$589'.
1/1: $1\_zz_CsrPlugin_csrMapping_writeDataSignal[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4399$581'.
1/1: $1\execute_CsrPlugin_readInstruction[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4392$578'.
1/1: $1\execute_CsrPlugin_writeInstruction[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4381$574'.
1/2: $2\execute_CsrPlugin_illegalInstruction[0:0]
2/2: $1\execute_CsrPlugin_illegalInstruction[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4354$573'.
1/8: $8\execute_CsrPlugin_illegalAccess[0:0]
2/8: $7\execute_CsrPlugin_illegalAccess[0:0]
3/8: $6\execute_CsrPlugin_illegalAccess[0:0]
4/8: $5\execute_CsrPlugin_illegalAccess[0:0]
5/8: $4\execute_CsrPlugin_illegalAccess[0:0]
6/8: $3\execute_CsrPlugin_illegalAccess[0:0]
7/8: $2\execute_CsrPlugin_illegalAccess[0:0]
8/8: $1\execute_CsrPlugin_illegalAccess[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4337$560'.
1/1: $1\CsrPlugin_xtvec_base[29:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4326$559'.
1/1: $1\CsrPlugin_xtvec_mode[1:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4316$556'.
1/1: $1\CsrPlugin_pipelineLiberator_done[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4291$537'.
1/1: $1\CsrPlugin_privilege[1:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4276$535'.
1/1: $1\writeBack_DBusSimplePlugin_rspFormated[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4256$534'.
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4227$531'.
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4208$528'.
1/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [15:8]
2/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [7:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4191$520'.
1/1: $1\_zz_execute_DBusSimplePlugin_formalMask[3:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4175$512'.
1/1: $1\_zz_dBus_cmd_payload_data[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4165$502'.
1/1: $1\execute_DBusSimplePlugin_skipCmd[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4138$493'.
1/1: $1\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4102$477'.
1/1: $1\decode_arbitration_isValid[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4073$461'.
1/2: $2\IBusSimplePlugin_iBusRsp_readyForError[0:0]
2/2: $1\IBusSimplePlugin_iBusRsp_readyForError[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4045$447'.
1/1: $1\IBusSimplePlugin_iBusRsp_stages_1_halt[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4026$438'.
1/1: $1\IBusSimplePlugin_fetchPc_flushed[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4017$436'.
1/1: $1\IBusSimplePlugin_fetchPc_pc[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:4007$431'.
1/1: $1\IBusSimplePlugin_fetchPc_pcRegPropagate[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3998$428'.
1/1: $1\IBusSimplePlugin_fetchPc_correction[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3987$424'.
1/1: $1\CsrPlugin_allowEbreakException[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3980$423'.
1/1: $1\CsrPlugin_allowException[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3973$422'.
1/1: $1\CsrPlugin_allowInterrupts[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3966$421'.
1/1: $1\CsrPlugin_forceMachineWire[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3950$420'.
1/3: $3\CsrPlugin_jumpInterface_payload[31:0]
2/3: $2\CsrPlugin_jumpInterface_payload[31:0]
3/3: $1\CsrPlugin_jumpInterface_payload[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3940$419'.
1/2: $2\CsrPlugin_jumpInterface_valid[0:0]
2/2: $1\CsrPlugin_jumpInterface_valid[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3933$418'.
1/1: $1\CsrPlugin_thirdPartyWake[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3920$417'.
1/2: $2\IBusSimplePlugin_incomingInstruction[0:0]
2/2: $1\IBusSimplePlugin_incomingInstruction[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3899$416'.
1/6: $6\IBusSimplePlugin_fetcherHalt[0:0]
2/6: $5\IBusSimplePlugin_fetcherHalt[0:0]
3/6: $4\IBusSimplePlugin_fetcherHalt[0:0]
4/6: $3\IBusSimplePlugin_fetcherHalt[0:0]
5/6: $2\IBusSimplePlugin_fetcherHalt[0:0]
6/6: $1\IBusSimplePlugin_fetcherHalt[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3885$415'.
1/2: $2\writeBack_arbitration_flushNext[0:0]
2/2: $1\writeBack_arbitration_flushNext[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3877$414'.
1/1: $1\writeBack_arbitration_removeIt[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3868$413'.
1/1: $1\memory_arbitration_flushNext[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3860$412'.
1/1: $1\memory_arbitration_removeIt[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3852$411'.
1/1: $1\memory_arbitration_haltItself[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3843$410'.
1/2: $2\execute_arbitration_flushNext[0:0]
2/2: $1\execute_arbitration_flushNext[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3834$409'.
1/2: $2\execute_arbitration_flushIt[0:0]
2/2: $1\execute_arbitration_flushIt[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3827$408'.
1/1: $1\execute_arbitration_removeIt[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3820$407'.
1/1: $1\execute_arbitration_haltByOther[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3803$406'.
1/5: $5\execute_arbitration_haltItself[0:0]
2/5: $4\execute_arbitration_haltItself[0:0]
3/5: $3\execute_arbitration_haltItself[0:0]
4/5: $2\execute_arbitration_haltItself[0:0]
5/5: $1\execute_arbitration_haltItself[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3794$405'.
1/1: $1\decode_arbitration_removeIt[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3781$404'.
1/3: $3\decode_arbitration_haltByOther[0:0]
2/3: $2\decode_arbitration_haltByOther[0:0]
3/3: $1\decode_arbitration_haltByOther[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3770$403'.
1/1: $1\decode_arbitration_haltItself[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3759$402'.
1/1: $1\_zz_memory_to_writeBack_FORMAL_PC_NEXT[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3741$401'.
1/1: $1\_zz_lastStageRegFileWrite_payload_data[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3724$400'.
1/2: $2\_zz_execute_to_memory_REGFILE_WRITE_DATA[31:0]
2/2: $1\_zz_execute_to_memory_REGFILE_WRITE_DATA[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3717$399'.
1/1: $1\decode_REGFILE_WRITE_VALID[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3709$397'.
1/1: $1\_zz_1[0:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3102$374'.
1/3: $1$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$380
2/3: $1$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_DATA[31:0]$379
3/3: $1$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_ADDR[4:0]$378
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3096$372'.
1/1: $0\_zz_RegFilePlugin_regFile_port1[31:0]
Creating decoders for process `\VexRiscv.$proc$../Murax.v:3090$370'.
1/1: $0\_zz_RegFilePlugin_regFile_port0[31:0]
Creating decoders for process `\JtagBridge.$proc$../Murax.v:2092$262'.
Creating decoders for process `\JtagBridge.$proc$../Murax.v:2050$256'.
1/4: $0\jtag_readArea_full_shifter[33:0]
2/4: $0\jtag_idcodeArea_shifter[31:0]
3/4: $0\jtag_tap_instructionShift[3:0]
4/4: $0\jtag_tap_instruction[3:0]
Creating decoders for process `\JtagBridge.$proc$../Murax.v:2039$255'.
1/3: $0\system_rsp_payload_data[31:0]
2/3: $0\system_rsp_payload_error[0:0]
3/3: $0\system_rsp_valid[0:0]
Creating decoders for process `\JtagBridge.$proc$../Murax.v:1995$235'.
1/3: $3\jtag_tap_tdoDr[0:0]
2/3: $2\jtag_tap_tdoDr[0:0]
3/3: $1\jtag_tap_tdoDr[0:0]
Creating decoders for process `\JtagBridge.$proc$../Murax.v:1977$234'.
1/2: $2\jtag_tap_tdoUnbufferd[0:0]
2/2: $1\jtag_tap_tdoUnbufferd[0:0]
Creating decoders for process `\JtagBridge.$proc$../Murax.v:1923$217'.
1/1: $1\_zz_jtag_tap_fsm_stateNext[3:0]
Creating decoders for process `\SystemDebugger.$proc$../Murax.v:1718$213'.
1/2: $0\dispatcher_headerShifter[7:0]
2/2: $0\dispatcher_dataShifter[66:0]
Creating decoders for process `\SystemDebugger.$proc$../Murax.v:1692$211'.
1/3: $0\dispatcher_counter[2:0]
2/3: $0\dispatcher_headerLoaded[0:0]
3/3: $0\dispatcher_dataLoaded[0:0]
Creating decoders for process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1633$198'.
1/1: $0\_zz_io_bus_rsp_valid[0:0]
Creating decoders for process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
1/12: $1$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$195
2/12: $1$memwr$\ram_symbol3$../Murax.v:1623$156_DATA[7:0]$194
3/12: $1$memwr$\ram_symbol3$../Murax.v:1623$156_ADDR[10:0]$193
4/12: $1$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$190
5/12: $1$memwr$\ram_symbol2$../Murax.v:1620$155_DATA[7:0]$189
6/12: $1$memwr$\ram_symbol2$../Murax.v:1620$155_ADDR[10:0]$188
7/12: $1$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$185
8/12: $1$memwr$\ram_symbol1$../Murax.v:1617$154_DATA[7:0]$184
9/12: $1$memwr$\ram_symbol1$../Murax.v:1617$154_ADDR[10:0]$183
10/12: $1$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$180
11/12: $1$memwr$\ram_symbol0$../Murax.v:1614$153_DATA[7:0]$179
12/12: $1$memwr$\ram_symbol0$../Murax.v:1614$153_ADDR[10:0]$178
Creating decoders for process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'.
1/4: $0\_zz_ramsymbol_read_3[7:0]
2/4: $0\_zz_ramsymbol_read_2[7:0]
3/4: $0\_zz_ramsymbol_read_1[7:0]
4/4: $0\_zz_ramsymbol_read[7:0]
Creating decoders for process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1600$157'.
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'.
1/4: $0\io_pipelinedMemoryBus_cmd_rData_mask[3:0]
2/4: $0\io_pipelinedMemoryBus_cmd_rData_data[31:0]
3/4: $0\io_pipelinedMemoryBus_cmd_rData_address[31:0]
4/4: $0\io_pipelinedMemoryBus_cmd_rData_write[0:0]
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'.
1/3: $0\pipelinedMemoryBusStage_rsp_regNext_valid[0:0]
2/3: $0\state[0:0]
3/3: $0\io_pipelinedMemoryBus_cmd_rValid[0:0]
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1523$147'.
1/2: $2\pipelinedMemoryBusStage_rsp_valid[0:0]
2/2: $1\pipelinedMemoryBusStage_rsp_valid[0:0]
Creating decoders for process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1509$145'.
1/2: $2\pipelinedMemoryBusStage_cmd_ready[0:0]
2/2: $1\pipelinedMemoryBusStage_cmd_ready[0:0]
Creating decoders for process `\Apb3Gpio.$proc$../Murax.v:1433$142'.
1/1: $0\io_gpio_write_driver[31:0]
Creating decoders for process `\Apb3Gpio.$proc$../Murax.v:1417$141'.
1/1: $0\io_gpio_writeEnable_driver[31:0]
Creating decoders for process `\Apb3Gpio.$proc$../Murax.v:1393$128'.
1/1: $1\io_apb_PRDATA[31:0]
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1353$127'.
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'.
1/6: $0\bridge_misc_doBreak[0:0]
2/6: $0\bridge_misc_breakDetected[0:0]
3/6: $0\bridge_misc_readOverflowError[0:0]
4/6: $0\bridge_misc_readError[0:0]
5/6: $0\bridge_interruptCtrl_readIntEnable[0:0]
6/6: $0\bridge_interruptCtrl_writeIntEnable[0:0]
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1282$125'.
1/2: $2\when_BusSlaveFactory_l335_3[0:0]
2/2: $1\when_BusSlaveFactory_l335_3[0:0]
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1268$124'.
1/2: $2\when_BusSlaveFactory_l366[0:0]
2/2: $1\when_BusSlaveFactory_l366[0:0]
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1254$123'.
1/2: $2\when_BusSlaveFactory_l335_2[0:0]
2/2: $1\when_BusSlaveFactory_l335_2[0:0]
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1238$118'.
1/2: $2\when_BusSlaveFactory_l335_1[0:0]
2/2: $1\when_BusSlaveFactory_l335_1[0:0]
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1224$117'.
1/2: $2\when_BusSlaveFactory_l335[0:0]
2/2: $1\when_BusSlaveFactory_l335[0:0]
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1208$112'.
1/2: $2\bridge_read_streamBreaked_ready[0:0]
2/2: $1\bridge_read_streamBreaked_ready[0:0]
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1200$111'.
1/1: $1\uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready[0:0]
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1193$110'.
1/1: $1\bridge_read_streamBreaked_valid[0:0]
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1177$109'.
1/2: $2\_zz_bridge_write_streamUnbuffered_valid[0:0]
2/2: $1\_zz_bridge_write_streamUnbuffered_valid[0:0]
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1173$108'.
Creating decoders for process `\Apb3UartCtrl.$proc$../Murax.v:1141$94'.
1/9: $2\io_apb_PRDATA[20:15] [5:2]
2/9: $1\io_apb_PRDATA[9:0] [7:2]
3/9: $2\io_apb_PRDATA[20:15] [1]
4/9: $1\io_apb_PRDATA[9:0] [8]
5/9: $2\io_apb_PRDATA[20:15] [0]
6/9: $1\io_apb_PRDATA[9:0] [1]
7/9: $3\io_apb_PRDATA[28:24]
8/9: $1\io_apb_PRDATA[9:0] [9]
9/9: $1\io_apb_PRDATA[9:0] [0]
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:952$91'.
1/3: $0\timerB_io_limit_driver[15:0]
2/3: $0\timerA_io_limit_driver[15:0]
3/3: $0\_zz_io_limit[15:0]
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:920$90'.
1/5: $0\interruptCtrl_1_io_masks_driver[1:0]
2/5: $0\timerBBridge_clearsEnable[0:0]
3/5: $0\timerBBridge_ticksEnable[1:0]
4/5: $0\timerABridge_clearsEnable[0:0]
5/5: $0\timerABridge_ticksEnable[1:0]
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:914$88'.
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:901$87'.
1/2: $2\interruptCtrl_1_io_clears[1:0]
2/2: $1\interruptCtrl_1_io_clears[1:0]
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:886$81'.
1/2: $2\when_Timer_l44_1[0:0]
2/2: $1\when_Timer_l44_1[0:0]
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:873$80'.
1/2: $2\when_Timer_l40_1[0:0]
2/2: $1\when_Timer_l40_1[0:0]
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:863$79'.
1/2: $2\timerBBridge_busClearing[0:0]
2/2: $1\timerBBridge_busClearing[0:0]
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:848$73'.
1/2: $2\when_Timer_l44[0:0]
2/2: $1\when_Timer_l44[0:0]
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:835$72'.
1/2: $2\when_Timer_l40[0:0]
2/2: $1\when_Timer_l40[0:0]
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:825$71'.
1/2: $2\timerABridge_busClearing[0:0]
2/2: $1\timerABridge_busClearing[0:0]
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:812$70'.
1/2: $2\_zz_io_clear[0:0]
2/2: $1\_zz_io_clear[0:0]
Creating decoders for process `\MuraxApb3Timer.$proc$../Murax.v:770$57'.
1/3: $1\io_apb_PRDATA[16:0] [16]
2/3: $1\io_apb_PRDATA[16:0] [15:2]
3/3: $1\io_apb_PRDATA[16:0] [1:0]
Creating decoders for process `\Apb3Decoder.$proc$../Murax.v:679$54'.
1/1: $1\io_input_PSLVERROR[0:0]
Creating decoders for process `\Apb3Decoder.$proc$../Murax.v:671$53'.
1/1: $1\io_input_PREADY[0:0]
Creating decoders for process `\Apb3Decoder.$proc$../Murax.v:665$43'.
Creating decoders for process `\Apb3Router.$proc$../Murax.v:633$42'.
Creating decoders for process `\Apb3Router.$proc$../Murax.v:593$41'.
1/3: $1\_zz_io_input_PSLVERROR[0:0]
2/3: $1\_zz_io_input_PRDATA[31:0]
3/3: $1\_zz_io_input_PREADY[0:0]
Creating decoders for process `\Murax.$proc$../Murax.v:0$40'.
Creating decoders for process `\Murax.$proc$../Murax.v:538$39'.
1/1: $0\system_cpu_debug_bus_cmd_fire_regNext[0:0]
Creating decoders for process `\Murax.$proc$../Murax.v:534$38'.
Creating decoders for process `\Murax.$proc$../Murax.v:522$37'.
1/5: $0\system_mainBusDecoder_logic_rspSourceId[0:0]
2/5: $0\system_cpu_dBus_cmd_rData_size[1:0]
3/5: $0\system_cpu_dBus_cmd_rData_data[31:0]
4/5: $0\system_cpu_dBus_cmd_rData_address[31:0]
5/5: $0\system_cpu_dBus_cmd_rData_wr[0:0]
Creating decoders for process `\Murax.$proc$../Murax.v:497$36'.
1/3: $0\system_mainBusDecoder_logic_rspNoHit[0:0]
2/3: $0\system_mainBusDecoder_logic_rspPending[0:0]
3/3: $0\system_cpu_dBus_cmd_rValid[0:0]
Creating decoders for process `\Murax.$proc$../Murax.v:489$35'.
1/1: $0\resetCtrl_systemReset[0:0]
Creating decoders for process `\Murax.$proc$../Murax.v:480$33'.
1/1: $0\resetCtrl_systemClkResetCounter[5:0]
Creating decoders for process `\Murax.$proc$../Murax.v:467$19'.
1/1: $1\system_mainBusDecoder_logic_masterPipelined_cmd_ready[0:0]
Creating decoders for process `\Murax.$proc$../Murax.v:458$15'.
1/1: $1\system_apbBridge_io_pipelinedMemoryBus_cmd_valid[0:0]
Creating decoders for process `\Murax.$proc$../Murax.v:449$11'.
1/1: $1\system_ram_io_bus_cmd_valid[0:0]
Creating decoders for process `\Murax.$proc$../Murax.v:419$5'.
1/1: $1\system_externalInterrupt[0:0]
Creating decoders for process `\Murax.$proc$../Murax.v:412$4'.
1/1: $1\system_timerInterrupt[0:0]
Creating decoders for process `\Murax.$proc$../Murax.v:402$2'.
1/1: $1\resetCtrl_mainClkResetUnbuffered[0:0]
Creating decoders for process `\Murax.$proc$../Murax.v:395$1'.
1/1: $1\_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31:0]
3.1.7. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\UartCtrlTx.\io_write_ready' from process `\UartCtrlTx.$proc$../Murax.v:6688$1027'.
No latch inferred for signal `\UartCtrlTx.\stateMachine_txd' from process `\UartCtrlTx.$proc$../Murax.v:6669$1025'.
No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_valueNext' from process `\UartCtrlTx.$proc$../Murax.v:6658$1023'.
No latch inferred for signal `\UartCtrlTx.\clockDivider_counter_willIncrement' from process `\UartCtrlTx.$proc$../Murax.v:6648$1020'.
No latch inferred for signal `\UartCtrlRx.\bitTimer_tick' from process `\UartCtrlRx.$proc$../Murax.v:6418$970'.
No latch inferred for signal `\UartCtrlRx.\io_error' from process `\UartCtrlRx.$proc$../Murax.v:6389$968'.
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_inst' from process `\StreamFifoLowLatency.$proc$../Murax.v:6259$959'.
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_payload_error' from process `\StreamFifoLowLatency.$proc$../Murax.v:6251$958'.
No latch inferred for signal `\StreamFifoLowLatency.\io_pop_valid' from process `\StreamFifoLowLatency.$proc$../Murax.v:6243$957'.
No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willClear' from process `\StreamFifoLowLatency.$proc$../Murax.v:6224$948'.
No latch inferred for signal `\StreamFifoLowLatency.\popPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$../Murax.v:6217$947'.
No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willClear' from process `\StreamFifoLowLatency.$proc$../Murax.v:6208$945'.
No latch inferred for signal `\StreamFifoLowLatency.\pushPtr_willIncrement' from process `\StreamFifoLowLatency.$proc$../Murax.v:6201$944'.
No latch inferred for signal `\StreamFifoLowLatency.\when_Phase_l623' from process `\StreamFifoLowLatency.$proc$../Murax.v:6194$943'.
No latch inferred for signal `\UartCtrl.\io_write_ready' from process `\UartCtrl.$proc$../Murax.v:6035$933'.
No latch inferred for signal `\UartCtrl.\io_write_thrown_valid' from process `\UartCtrl.$proc$../Murax.v:6028$932'.
No latch inferred for signal `\StreamFifo.\logic_popPtr_valueNext' from process `\StreamFifo.$proc$../Murax.v:5895$910'.
No latch inferred for signal `\StreamFifo.\logic_popPtr_willClear' from process `\StreamFifo.$proc$../Murax.v:5886$907'.
No latch inferred for signal `\StreamFifo.\logic_popPtr_willIncrement' from process `\StreamFifo.$proc$../Murax.v:5879$906'.
No latch inferred for signal `\StreamFifo.\logic_pushPtr_valueNext' from process `\StreamFifo.$proc$../Murax.v:5872$904'.
No latch inferred for signal `\StreamFifo.\logic_pushPtr_willClear' from process `\StreamFifo.$proc$../Murax.v:5863$901'.
No latch inferred for signal `\StreamFifo.\logic_pushPtr_willIncrement' from process `\StreamFifo.$proc$../Murax.v:5856$900'.
No latch inferred for signal `\StreamFifo.\_zz_1' from process `\StreamFifo.$proc$../Murax.v:5849$899'.
No latch inferred for signal `\MuraxMasterArbiter.\io_dBus_cmd_ready' from process `\MuraxMasterArbiter.$proc$../Murax.v:5637$860'.
No latch inferred for signal `\MuraxMasterArbiter.\io_iBus_cmd_ready' from process `\MuraxMasterArbiter.$proc$../Murax.v:5630$857'.
No latch inferred for signal `\MuraxMasterArbiter.\_zz_io_masterBus_cmd_payload_mask' from process `\MuraxMasterArbiter.$proc$../Murax.v:5615$855'.
No latch inferred for signal `\MuraxMasterArbiter.\io_masterBus_cmd_valid' from process `\MuraxMasterArbiter.$proc$../Murax.v:5605$851'.
No latch inferred for signal `\VexRiscv.\_zz_CsrPlugin_csrMapping_readDataInit_3' from process `\VexRiscv.$proc$../Murax.v:5007$821'.
No latch inferred for signal `\VexRiscv.\_zz_CsrPlugin_csrMapping_readDataInit_2' from process `\VexRiscv.$proc$../Murax.v:4998$820'.
No latch inferred for signal `\VexRiscv.\_zz_CsrPlugin_csrMapping_readDataInit_1' from process `\VexRiscv.$proc$../Murax.v:4989$819'.
No latch inferred for signal `\VexRiscv.\_zz_CsrPlugin_csrMapping_readDataInit' from process `\VexRiscv.$proc$../Murax.v:4980$818'.
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_ready' from process `\VexRiscv.$proc$../Murax.v:4963$811'.
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_injectionPort_valid' from process `\VexRiscv.$proc$../Murax.v:4841$690'.
No latch inferred for signal `\VexRiscv.\debug_bus_rsp_data' from process `\VexRiscv.$proc$../Murax.v:4829$688'.
No latch inferred for signal `\VexRiscv.\debug_bus_cmd_ready' from process `\VexRiscv.$proc$../Murax.v:4814$687'.
No latch inferred for signal `\VexRiscv.\_zz_execute_BranchPlugin_branch_src2_6' from process `\VexRiscv.$proc$../Murax.v:4794$679'.
No latch inferred for signal `\VexRiscv.\_zz_execute_BranchPlugin_branch_src2_5' from process `\VexRiscv.$proc$../Murax.v:4772$678'.
No latch inferred for signal `\VexRiscv.\_zz_execute_BranchPlugin_branch_src2_3' from process `\VexRiscv.$proc$../Murax.v:4748$677'.
No latch inferred for signal `\VexRiscv.\_zz_execute_BranchPlugin_branch_src2_1' from process `\VexRiscv.$proc$../Murax.v:4733$676'.
No latch inferred for signal `\VexRiscv.\_zz_execute_BRANCH_DO_1' from process `\VexRiscv.$proc$../Murax.v:4714$673'.
No latch inferred for signal `\VexRiscv.\_zz_execute_BRANCH_DO' from process `\VexRiscv.$proc$../Murax.v:4697$670'.
No latch inferred for signal `\VexRiscv.\HazardSimplePlugin_src1Hazard' from process `\VexRiscv.$proc$../Murax.v:4642$648'.
No latch inferred for signal `\VexRiscv.\HazardSimplePlugin_src0Hazard' from process `\VexRiscv.$proc$../Murax.v:4609$647'.
No latch inferred for signal `\VexRiscv.\_zz_execute_to_memory_REGFILE_WRITE_DATA_1' from process `\VexRiscv.$proc$../Murax.v:4596$643'.
No latch inferred for signal `\VexRiscv.\execute_SrcPlugin_addSub' from process `\VexRiscv.$proc$../Murax.v:4583$632'.
No latch inferred for signal `\VexRiscv.\_zz_decode_SRC2_6' from process `\VexRiscv.$proc$../Murax.v:4566$631'.
No latch inferred for signal `\VexRiscv.\_zz_decode_SRC2_5' from process `\VexRiscv.$proc$../Murax.v:4543$630'.
No latch inferred for signal `\VexRiscv.\_zz_decode_SRC2_3' from process `\VexRiscv.$proc$../Murax.v:4519$629'.
No latch inferred for signal `\VexRiscv.\_zz_decode_SRC1_1' from process `\VexRiscv.$proc$../Murax.v:4501$628'.
No latch inferred for signal `\VexRiscv.\_zz_execute_REGFILE_WRITE_DATA' from process `\VexRiscv.$proc$../Murax.v:4487$627'.
No latch inferred for signal `\VexRiscv.\execute_IntAluPlugin_bitwise' from process `\VexRiscv.$proc$../Murax.v:4473$623'.
No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_payload_data' from process `\VexRiscv.$proc$../Murax.v:4466$622'.
No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_payload_address' from process `\VexRiscv.$proc$../Murax.v:4459$621'.
No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_valid' from process `\VexRiscv.$proc$../Murax.v:4452$619'.
No latch inferred for signal `\VexRiscv.\_zz_CsrPlugin_csrMapping_writeDataSignal' from process `\VexRiscv.$proc$../Murax.v:4411$589'.
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_readInstruction' from process `\VexRiscv.$proc$../Murax.v:4399$581'.
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_writeInstruction' from process `\VexRiscv.$proc$../Murax.v:4392$578'.
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalInstruction' from process `\VexRiscv.$proc$../Murax.v:4381$574'.
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalAccess' from process `\VexRiscv.$proc$../Murax.v:4354$573'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_base' from process `\VexRiscv.$proc$../Murax.v:4337$560'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_mode' from process `\VexRiscv.$proc$../Murax.v:4326$559'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_done' from process `\VexRiscv.$proc$../Murax.v:4316$556'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_privilege' from process `\VexRiscv.$proc$../Murax.v:4291$537'.
No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspFormated' from process `\VexRiscv.$proc$../Murax.v:4276$535'.
No latch inferred for signal `\VexRiscv.\_zz_writeBack_DBusSimplePlugin_rspFormated_3' from process `\VexRiscv.$proc$../Murax.v:4256$534'.
No latch inferred for signal `\VexRiscv.\_zz_writeBack_DBusSimplePlugin_rspFormated_1' from process `\VexRiscv.$proc$../Murax.v:4227$531'.
No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspShifted' from process `\VexRiscv.$proc$../Murax.v:4208$528'.
No latch inferred for signal `\VexRiscv.\_zz_execute_DBusSimplePlugin_formalMask' from process `\VexRiscv.$proc$../Murax.v:4191$520'.
No latch inferred for signal `\VexRiscv.\_zz_dBus_cmd_payload_data' from process `\VexRiscv.$proc$../Murax.v:4175$512'.
No latch inferred for signal `\VexRiscv.\execute_DBusSimplePlugin_skipCmd' from process `\VexRiscv.$proc$../Murax.v:4165$502'.
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_fetchRsp_rsp_error' from process `\VexRiscv.$proc$../Murax.v:4138$493'.
No latch inferred for signal `\VexRiscv.\decode_arbitration_isValid' from process `\VexRiscv.$proc$../Murax.v:4102$477'.
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_readyForError' from process `\VexRiscv.$proc$../Murax.v:4073$461'.
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_iBusRsp_stages_1_halt' from process `\VexRiscv.$proc$../Murax.v:4045$447'.
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_flushed' from process `\VexRiscv.$proc$../Murax.v:4026$438'.
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pc' from process `\VexRiscv.$proc$../Murax.v:4017$436'.
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcRegPropagate' from process `\VexRiscv.$proc$../Murax.v:4007$431'.
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correction' from process `\VexRiscv.$proc$../Murax.v:3998$428'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_allowEbreakException' from process `\VexRiscv.$proc$../Murax.v:3987$424'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_allowException' from process `\VexRiscv.$proc$../Murax.v:3980$423'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_allowInterrupts' from process `\VexRiscv.$proc$../Murax.v:3973$422'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_forceMachineWire' from process `\VexRiscv.$proc$../Murax.v:3966$421'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_payload' from process `\VexRiscv.$proc$../Murax.v:3950$420'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_valid' from process `\VexRiscv.$proc$../Murax.v:3940$419'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_thirdPartyWake' from process `\VexRiscv.$proc$../Murax.v:3933$418'.
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_incomingInstruction' from process `\VexRiscv.$proc$../Murax.v:3920$417'.
No latch inferred for signal `\VexRiscv.\IBusSimplePlugin_fetcherHalt' from process `\VexRiscv.$proc$../Murax.v:3899$416'.
No latch inferred for signal `\VexRiscv.\writeBack_arbitration_flushNext' from process `\VexRiscv.$proc$../Murax.v:3885$415'.
No latch inferred for signal `\VexRiscv.\writeBack_arbitration_removeIt' from process `\VexRiscv.$proc$../Murax.v:3877$414'.
No latch inferred for signal `\VexRiscv.\memory_arbitration_flushNext' from process `\VexRiscv.$proc$../Murax.v:3868$413'.
No latch inferred for signal `\VexRiscv.\memory_arbitration_removeIt' from process `\VexRiscv.$proc$../Murax.v:3860$412'.
No latch inferred for signal `\VexRiscv.\memory_arbitration_haltItself' from process `\VexRiscv.$proc$../Murax.v:3852$411'.
No latch inferred for signal `\VexRiscv.\execute_arbitration_flushNext' from process `\VexRiscv.$proc$../Murax.v:3843$410'.
No latch inferred for signal `\VexRiscv.\execute_arbitration_flushIt' from process `\VexRiscv.$proc$../Murax.v:3834$409'.
No latch inferred for signal `\VexRiscv.\execute_arbitration_removeIt' from process `\VexRiscv.$proc$../Murax.v:3827$408'.
No latch inferred for signal `\VexRiscv.\execute_arbitration_haltByOther' from process `\VexRiscv.$proc$../Murax.v:3820$407'.
No latch inferred for signal `\VexRiscv.\execute_arbitration_haltItself' from process `\VexRiscv.$proc$../Murax.v:3803$406'.
No latch inferred for signal `\VexRiscv.\decode_arbitration_removeIt' from process `\VexRiscv.$proc$../Murax.v:3794$405'.
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltByOther' from process `\VexRiscv.$proc$../Murax.v:3781$404'.
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltItself' from process `\VexRiscv.$proc$../Murax.v:3770$403'.
No latch inferred for signal `\VexRiscv.\_zz_memory_to_writeBack_FORMAL_PC_NEXT' from process `\VexRiscv.$proc$../Murax.v:3759$402'.
No latch inferred for signal `\VexRiscv.\_zz_lastStageRegFileWrite_payload_data' from process `\VexRiscv.$proc$../Murax.v:3741$401'.
No latch inferred for signal `\VexRiscv.\_zz_execute_to_memory_REGFILE_WRITE_DATA' from process `\VexRiscv.$proc$../Murax.v:3724$400'.
No latch inferred for signal `\VexRiscv.\decode_REGFILE_WRITE_VALID' from process `\VexRiscv.$proc$../Murax.v:3717$399'.
No latch inferred for signal `\VexRiscv.\_zz_1' from process `\VexRiscv.$proc$../Murax.v:3709$397'.
No latch inferred for signal `\JtagBridge.\jtag_tap_tdoDr' from process `\JtagBridge.$proc$../Murax.v:1995$235'.
No latch inferred for signal `\JtagBridge.\jtag_tap_tdoUnbufferd' from process `\JtagBridge.$proc$../Murax.v:1977$234'.
No latch inferred for signal `\JtagBridge.\_zz_jtag_tap_fsm_stateNext' from process `\JtagBridge.$proc$../Murax.v:1923$217'.
No latch inferred for signal `\MuraxPipelinedMemoryBusRam.\_zz_ram_port0' from process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1600$157'.
No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_valid' from process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1523$147'.
No latch inferred for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_cmd_ready' from process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1509$145'.
No latch inferred for signal `\Apb3Gpio.\io_apb_PRDATA' from process `\Apb3Gpio.$proc$../Murax.v:1393$128'.
No latch inferred for signal `\Apb3UartCtrl.\when_BusSlaveFactory_l335_3' from process `\Apb3UartCtrl.$proc$../Murax.v:1282$125'.
No latch inferred for signal `\Apb3UartCtrl.\when_BusSlaveFactory_l366' from process `\Apb3UartCtrl.$proc$../Murax.v:1268$124'.
No latch inferred for signal `\Apb3UartCtrl.\when_BusSlaveFactory_l335_2' from process `\Apb3UartCtrl.$proc$../Murax.v:1254$123'.
No latch inferred for signal `\Apb3UartCtrl.\when_BusSlaveFactory_l335_1' from process `\Apb3UartCtrl.$proc$../Murax.v:1238$118'.
No latch inferred for signal `\Apb3UartCtrl.\when_BusSlaveFactory_l335' from process `\Apb3UartCtrl.$proc$../Murax.v:1224$117'.
No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_ready' from process `\Apb3UartCtrl.$proc$../Murax.v:1208$112'.
No latch inferred for signal `\Apb3UartCtrl.\uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready' from process `\Apb3UartCtrl.$proc$../Murax.v:1200$111'.
No latch inferred for signal `\Apb3UartCtrl.\bridge_read_streamBreaked_valid' from process `\Apb3UartCtrl.$proc$../Murax.v:1193$110'.
No latch inferred for signal `\Apb3UartCtrl.\_zz_bridge_write_streamUnbuffered_valid' from process `\Apb3UartCtrl.$proc$../Murax.v:1177$109'.
No latch inferred for signal `\Apb3UartCtrl.\bridge_uartConfigReg_clockDivider' from process `\Apb3UartCtrl.$proc$../Murax.v:1173$108'.
No latch inferred for signal `\Apb3UartCtrl.\io_apb_PRDATA' from process `\Apb3UartCtrl.$proc$../Murax.v:1141$94'.
No latch inferred for signal `\MuraxApb3Timer.\interruptCtrl_1_io_inputs' from process `\MuraxApb3Timer.$proc$../Murax.v:914$88'.
No latch inferred for signal `\MuraxApb3Timer.\interruptCtrl_1_io_clears' from process `\MuraxApb3Timer.$proc$../Murax.v:901$87'.
No latch inferred for signal `\MuraxApb3Timer.\when_Timer_l44_1' from process `\MuraxApb3Timer.$proc$../Murax.v:886$81'.
No latch inferred for signal `\MuraxApb3Timer.\when_Timer_l40_1' from process `\MuraxApb3Timer.$proc$../Murax.v:873$80'.
No latch inferred for signal `\MuraxApb3Timer.\timerBBridge_busClearing' from process `\MuraxApb3Timer.$proc$../Murax.v:863$79'.
No latch inferred for signal `\MuraxApb3Timer.\when_Timer_l44' from process `\MuraxApb3Timer.$proc$../Murax.v:848$73'.
No latch inferred for signal `\MuraxApb3Timer.\when_Timer_l40' from process `\MuraxApb3Timer.$proc$../Murax.v:835$72'.
No latch inferred for signal `\MuraxApb3Timer.\timerABridge_busClearing' from process `\MuraxApb3Timer.$proc$../Murax.v:825$71'.
No latch inferred for signal `\MuraxApb3Timer.\_zz_io_clear' from process `\MuraxApb3Timer.$proc$../Murax.v:812$70'.
No latch inferred for signal `\MuraxApb3Timer.\io_apb_PRDATA' from process `\MuraxApb3Timer.$proc$../Murax.v:770$57'.
No latch inferred for signal `\Apb3Decoder.\io_input_PSLVERROR' from process `\Apb3Decoder.$proc$../Murax.v:679$54'.
No latch inferred for signal `\Apb3Decoder.\io_input_PREADY' from process `\Apb3Decoder.$proc$../Murax.v:671$53'.
No latch inferred for signal `\Apb3Decoder.\io_output_PSEL' from process `\Apb3Decoder.$proc$../Murax.v:665$43'.
No latch inferred for signal `\Apb3Router.\_zz_io_input_PREADY' from process `\Apb3Router.$proc$../Murax.v:593$41'.
No latch inferred for signal `\Apb3Router.\_zz_io_input_PRDATA' from process `\Apb3Router.$proc$../Murax.v:593$41'.
No latch inferred for signal `\Apb3Router.\_zz_io_input_PSLVERROR' from process `\Apb3Router.$proc$../Murax.v:593$41'.
No latch inferred for signal `\Murax.\system_mainBusDecoder_logic_masterPipelined_cmd_ready' from process `\Murax.$proc$../Murax.v:467$19'.
No latch inferred for signal `\Murax.\system_apbBridge_io_pipelinedMemoryBus_cmd_valid' from process `\Murax.$proc$../Murax.v:458$15'.
No latch inferred for signal `\Murax.\system_ram_io_bus_cmd_valid' from process `\Murax.$proc$../Murax.v:449$11'.
No latch inferred for signal `\Murax.\system_externalInterrupt' from process `\Murax.$proc$../Murax.v:419$5'.
No latch inferred for signal `\Murax.\system_timerInterrupt' from process `\Murax.$proc$../Murax.v:412$4'.
No latch inferred for signal `\Murax.\resetCtrl_mainClkResetUnbuffered' from process `\Murax.$proc$../Murax.v:402$2'.
No latch inferred for signal `\Murax.\_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data' from process `\Murax.$proc$../Murax.v:395$1'.
3.1.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\BufferCC.\buffers_0' using process `\BufferCC.$proc$../Murax.v:6826$1043'.
created $adff cell `$procdff$2879' with positive edge clock and positive level reset.
Creating register for signal `\BufferCC.\buffers_1' using process `\BufferCC.$proc$../Murax.v:6826$1043'.
created $adff cell `$procdff$2880' with positive edge clock and positive level reset.
Creating register for signal `\BufferCC_1.\buffers_0' using process `\BufferCC_1.$proc$../Murax.v:6807$1042'.
created $dff cell `$procdff$2881' with positive edge clock.
Creating register for signal `\BufferCC_1.\buffers_1' using process `\BufferCC_1.$proc$../Murax.v:6807$1042'.
created $dff cell `$procdff$2882' with positive edge clock.
Creating register for signal `\UartCtrlTx.\stateMachine_parity' using process `\UartCtrlTx.$proc$../Murax.v:6760$1038'.
created $dff cell `$procdff$2883' with positive edge clock.
Creating register for signal `\UartCtrlTx.\tickCounter_value' using process `\UartCtrlTx.$proc$../Murax.v:6760$1038'.
created $dff cell `$procdff$2884' with positive edge clock.
Creating register for signal `\UartCtrlTx.\stateMachine_state' using process `\UartCtrlTx.$proc$../Murax.v:6714$1034'.
created $adff cell `$procdff$2885' with positive edge clock and positive level reset.
Creating register for signal `\UartCtrlTx.\clockDivider_counter_value' using process `\UartCtrlTx.$proc$../Murax.v:6714$1034'.
created $adff cell `$procdff$2886' with positive edge clock and positive level reset.
Creating register for signal `\UartCtrlTx.\_zz_io_txd' using process `\UartCtrlTx.$proc$../Murax.v:6714$1034'.
created $adff cell `$procdff$2887' with positive edge clock and positive level reset.
Creating register for signal `\UartCtrlRx.\bitTimer_counter' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'.
created $dff cell `$procdff$2888' with positive edge clock.
Creating register for signal `\UartCtrlRx.\bitCounter_value' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'.
created $dff cell `$procdff$2889' with positive edge clock.
Creating register for signal `\UartCtrlRx.\stateMachine_parity' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'.
created $dff cell `$procdff$2890' with positive edge clock.
Creating register for signal `\UartCtrlRx.\stateMachine_shifter' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'.
created $dff cell `$procdff$2891' with positive edge clock.
Creating register for signal `\UartCtrlRx.$bitselwrite$mask$../Murax.v:6546$964' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'.
created $dff cell `$procdff$2892' with positive edge clock.
Creating register for signal `\UartCtrlRx.$bitselwrite$data$../Murax.v:6546$965' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'.
created $dff cell `$procdff$2893' with positive edge clock.
Creating register for signal `\UartCtrlRx.$lookahead\stateMachine_shifter$997' using process `\UartCtrlRx.$proc$../Murax.v:6519$998'.
created $dff cell `$procdff$2894' with positive edge clock.
Creating register for signal `\UartCtrlRx.\_zz_io_rts' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'.
created $adff cell `$procdff$2895' with positive edge clock and positive level reset.
Creating register for signal `\UartCtrlRx.\sampler_samples_1' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'.
created $adff cell `$procdff$2896' with positive edge clock and positive level reset.
Creating register for signal `\UartCtrlRx.\sampler_samples_2' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'.
created $adff cell `$procdff$2897' with positive edge clock and positive level reset.
Creating register for signal `\UartCtrlRx.\sampler_value' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'.
created $adff cell `$procdff$2898' with positive edge clock and positive level reset.
Creating register for signal `\UartCtrlRx.\sampler_tick' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'.
created $adff cell `$procdff$2899' with positive edge clock and positive level reset.
Creating register for signal `\UartCtrlRx.\break_counter' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'.
created $adff cell `$procdff$2900' with positive edge clock and positive level reset.
Creating register for signal `\UartCtrlRx.\stateMachine_state' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'.
created $adff cell `$procdff$2901' with positive edge clock and positive level reset.
Creating register for signal `\UartCtrlRx.\stateMachine_validReg' using process `\UartCtrlRx.$proc$../Murax.v:6440$985'.
created $adff cell `$procdff$2902' with positive edge clock and positive level reset.
Creating register for signal `\StreamFifoLowLatency.\_zz_readed_error_2' using process `\StreamFifoLowLatency.$proc$../Murax.v:6283$963'.
created $dff cell `$procdff$2903' with positive edge clock.
Creating register for signal `\StreamFifoLowLatency.\risingOccupancy' using process `\StreamFifoLowLatency.$proc$../Murax.v:6270$962'.
created $adff cell `$procdff$2904' with positive edge clock and positive level reset.
Creating register for signal `\FlowCCByToggle.\outputArea_flow_m2sPipe_valid' using process `\FlowCCByToggle.$proc$../Murax.v:6145$941'.
created $adff cell `$procdff$2905' with positive edge clock and positive level reset.
Creating register for signal `\FlowCCByToggle.\outputArea_hit' using process `\FlowCCByToggle.$proc$../Murax.v:6137$940'.
created $dff cell `$procdff$2906' with positive edge clock.
Creating register for signal `\FlowCCByToggle.\outputArea_flow_m2sPipe_payload_last' using process `\FlowCCByToggle.$proc$../Murax.v:6137$940'.
created $dff cell `$procdff$2907' with positive edge clock.
Creating register for signal `\FlowCCByToggle.\outputArea_flow_m2sPipe_payload_fragment' using process `\FlowCCByToggle.$proc$../Murax.v:6137$940'.
created $dff cell `$procdff$2908' with positive edge clock.
Creating register for signal `\FlowCCByToggle.\inputArea_target' using process `\FlowCCByToggle.$proc$../Murax.v:6129$938'.
created $dff cell `$procdff$2909' with positive edge clock.
Creating register for signal `\FlowCCByToggle.\inputArea_data_last' using process `\FlowCCByToggle.$proc$../Murax.v:6129$938'.
created $dff cell `$procdff$2910' with positive edge clock.
Creating register for signal `\FlowCCByToggle.\inputArea_data_fragment' using process `\FlowCCByToggle.$proc$../Murax.v:6129$938'.
created $dff cell `$procdff$2911' with positive edge clock.
Creating register for signal `\BufferCC_2.\buffers_0' using process `\BufferCC_2.$proc$../Murax.v:6076$936'.
created $dff cell `$procdff$2912' with positive edge clock.
Creating register for signal `\BufferCC_2.\buffers_1' using process `\BufferCC_2.$proc$../Murax.v:6076$936'.
created $dff cell `$procdff$2913' with positive edge clock.
Creating register for signal `\UartCtrl.\clockDivider_counter' using process `\UartCtrl.$proc$../Murax.v:6049$934'.
created $adff cell `$procdff$2914' with positive edge clock and positive level reset.
Creating register for signal `\UartCtrl.\clockDivider_tickReg' using process `\UartCtrl.$proc$../Murax.v:6049$934'.
created $adff cell `$procdff$2915' with positive edge clock and positive level reset.
Creating register for signal `\StreamFifo.\logic_pushPtr_value' using process `\StreamFifo.$proc$../Murax.v:5914$929'.
created $adff cell `$procdff$2916' with positive edge clock and positive level reset.
Creating register for signal `\StreamFifo.\logic_popPtr_value' using process `\StreamFifo.$proc$../Murax.v:5914$929'.
created $adff cell `$procdff$2917' with positive edge clock and positive level reset.
Creating register for signal `\StreamFifo.\logic_risingOccupancy' using process `\StreamFifo.$proc$../Murax.v:5914$929'.
created $adff cell `$procdff$2918' with positive edge clock and positive level reset.
Creating register for signal `\StreamFifo.\_zz_io_pop_valid' using process `\StreamFifo.$proc$../Murax.v:5914$929'.
created $adff cell `$procdff$2919' with positive edge clock and positive level reset.
Creating register for signal `\StreamFifo.$memwr$\logic_ram$../Murax.v:5845$888_ADDR' using process `\StreamFifo.$proc$../Murax.v:5843$892'.
created $dff cell `$procdff$2920' with positive edge clock.
Creating register for signal `\StreamFifo.$memwr$\logic_ram$../Murax.v:5845$888_DATA' using process `\StreamFifo.$proc$../Murax.v:5843$892'.
created $dff cell `$procdff$2921' with positive edge clock.
Creating register for signal `\StreamFifo.$memwr$\logic_ram$../Murax.v:5845$888_EN' using process `\StreamFifo.$proc$../Murax.v:5843$892'.
created $dff cell `$procdff$2922' with positive edge clock.
Creating register for signal `\StreamFifo.\_zz_logic_ram_port0' using process `\StreamFifo.$proc$../Murax.v:5837$890'.
created $dff cell `$procdff$2923' with positive edge clock.
Creating register for signal `\Prescaler.\counter' using process `\Prescaler.$proc$../Murax.v:5773$886'.
created $dff cell `$procdff$2924' with positive edge clock.
Creating register for signal `\Timer.\counter' using process `\Timer.$proc$../Murax.v:5748$882'.
created $dff cell `$procdff$2925' with positive edge clock.
Creating register for signal `\Timer.\inhibitFull' using process `\Timer.$proc$../Murax.v:5735$881'.
created $adff cell `$procdff$2926' with positive edge clock and positive level reset.
Creating register for signal `\InterruptCtrl.\pendings' using process `\InterruptCtrl.$proc$../Murax.v:5701$872'.
created $adff cell `$procdff$2927' with positive edge clock and positive level reset.
Creating register for signal `\BufferCC_3.\buffers_0' using process `\BufferCC_3.$proc$../Murax.v:5681$870'.
created $dff cell `$procdff$2928' with positive edge clock.
Creating register for signal `\BufferCC_3.\buffers_1' using process `\BufferCC_3.$proc$../Murax.v:5681$870'.
created $dff cell `$procdff$2929' with positive edge clock.
Creating register for signal `\MuraxMasterArbiter.\rspPending' using process `\MuraxMasterArbiter.$proc$../Murax.v:5653$869'.
created $adff cell `$procdff$2930' with positive edge clock and positive level reset.
Creating register for signal `\MuraxMasterArbiter.\rspTarget' using process `\MuraxMasterArbiter.$proc$../Murax.v:5653$869'.
created $adff cell `$procdff$2931' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\DebugPlugin_resetIt' using process `\VexRiscv.$proc$../Murax.v:5502$850'.
created $adff cell `$procdff$2932' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\DebugPlugin_haltIt' using process `\VexRiscv.$proc$../Murax.v:5502$850'.
created $adff cell `$procdff$2933' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\DebugPlugin_stepIt' using process `\VexRiscv.$proc$../Murax.v:5502$850'.
created $adff cell `$procdff$2934' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\DebugPlugin_godmode' using process `\VexRiscv.$proc$../Murax.v:5502$850'.
created $adff cell `$procdff$2935' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\DebugPlugin_haltedByBreak' using process `\VexRiscv.$proc$../Murax.v:5502$850'.
created $adff cell `$procdff$2936' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\DebugPlugin_debugUsed' using process `\VexRiscv.$proc$../Murax.v:5502$850'.
created $adff cell `$procdff$2937' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\DebugPlugin_disableEbreak' using process `\VexRiscv.$proc$../Murax.v:5502$850'.
created $adff cell `$procdff$2938' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\DebugPlugin_firstCycle' using process `\VexRiscv.$proc$../Murax.v:5485$847'.
created $dff cell `$procdff$2939' with positive edge clock.
Creating register for signal `\VexRiscv.\DebugPlugin_secondCycle' using process `\VexRiscv.$proc$../Murax.v:5485$847'.
created $dff cell `$procdff$2940' with positive edge clock.
Creating register for signal `\VexRiscv.\DebugPlugin_isPipBusy' using process `\VexRiscv.$proc$../Murax.v:5485$847'.
created $dff cell `$procdff$2941' with positive edge clock.
Creating register for signal `\VexRiscv.\DebugPlugin_busReadDataReg' using process `\VexRiscv.$proc$../Murax.v:5485$847'.
created $dff cell `$procdff$2942' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_when_DebugPlugin_l244' using process `\VexRiscv.$proc$../Murax.v:5485$847'.
created $dff cell `$procdff$2943' with positive edge clock.
Creating register for signal `\VexRiscv.\DebugPlugin_resetIt_regNext' using process `\VexRiscv.$proc$../Murax.v:5485$847'.
created $dff cell `$procdff$2944' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2945' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_injector_decodeInput_payload_pc' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2946' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2947' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2948' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2949' with positive edge clock.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_formal_rawInDecode' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2950' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mepc' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2951' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MEIP' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2952' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MTIP' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2953' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MSIP' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2954' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_interrupt' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2955' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_exceptionCode' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2956' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_code' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2957' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_targetPrivilege' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2958' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_LightShifterPlugin_amplitudeReg' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2959' with positive edge clock.
Creating register for signal `\VexRiscv.\HazardSimplePlugin_writeBackBuffer_payload_address' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2960' with positive edge clock.
Creating register for signal `\VexRiscv.\HazardSimplePlugin_writeBackBuffer_payload_data' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2961' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_PC' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2962' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_PC' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2963' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_PC' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2964' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_INSTRUCTION' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2965' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_INSTRUCTION' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2966' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_INSTRUCTION' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2967' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2968' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2969' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2970' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_WRITE_OPCODE' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2971' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_READ_OPCODE' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2972' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_USE_SUB_LESS' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2973' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_ENABLE' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2974' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ENABLE' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2975' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ENABLE' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2976' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2977' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2978' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2979' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_EXECUTE_STAGE' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2980' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2981' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2982' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_STORE' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2983' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_STORE' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2984' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_IS_CSR' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2985' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_ENV_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2986' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_ENV_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2987' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_ENV_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2988' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2989' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_LESS_UNSIGNED' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2990' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_BITWISE_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2991' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SHIFT_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2992' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_BRANCH_CTRL' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2993' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_RS1' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2994' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_RS2' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2995' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2_FORCE_ZERO' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2996' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SRC1' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2997' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2998' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_DO_EBREAK' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$2999' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$3000' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$3001' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$3002' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$3003' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_DO' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$3004' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_CALC' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$3005' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_READ_DATA' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$3006' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_768' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$3007' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_836' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$3008' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_772' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$3009' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_834' using process `\VexRiscv.$proc$../Murax.v:5280$840'.
created $dff cell `$procdff$3010' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_arbitration_isValid' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3011' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\memory_arbitration_isValid' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3012' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\writeBack_arbitration_isValid' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3013' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_pcReg' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3014' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_correctionReg' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3015' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_booted' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3016' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_fetchPc_inc' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3017' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3018' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3019' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\_zz_IBusSimplePlugin_injector_decodeInput_valid' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3020' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_0' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3021' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_1' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3022' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_2' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3023' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_3' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3024' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_4' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3025' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_injector_nextPcCalc_valids_5' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3026' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_pending_value' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3027' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3028' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MIE' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3029' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPIE' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3030' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPP' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3031' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MEIE' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3032' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MTIE' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3033' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MSIE' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3034' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mcycle' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3035' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_minstret' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3036' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_valid' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3037' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_0' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3038' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_1' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3039' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_2' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3040' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_hadException' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3041' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_wfiWake' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3042' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\_zz_2' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3043' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\execute_LightShifterPlugin_isActive' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3044' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\HazardSimplePlugin_writeBackBuffer_valid' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3045' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\switch_Fetcher_l362' using process `\VexRiscv.$proc$../Murax.v:5018$829'.
created $adff cell `$procdff$3046' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_ADDR' using process `\VexRiscv.$proc$../Murax.v:3102$374'.
created $dff cell `$procdff$3047' with positive edge clock.
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_DATA' using process `\VexRiscv.$proc$../Murax.v:3102$374'.
created $dff cell `$procdff$3048' with positive edge clock.
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN' using process `\VexRiscv.$proc$../Murax.v:3102$374'.
created $dff cell `$procdff$3049' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_RegFilePlugin_regFile_port1' using process `\VexRiscv.$proc$../Murax.v:3096$372'.
created $dff cell `$procdff$3050' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_RegFilePlugin_regFile_port0' using process `\VexRiscv.$proc$../Murax.v:3090$370'.
created $dff cell `$procdff$3051' with positive edge clock.
Creating register for signal `\JtagBridge.\jtag_tap_tdoUnbufferd_regNext' using process `\JtagBridge.$proc$../Murax.v:2092$262'.
created $dff cell `$procdff$3052' with negative edge clock.
Creating register for signal `\JtagBridge.\jtag_tap_fsm_state' using process `\JtagBridge.$proc$../Murax.v:2050$256'.
created $dff cell `$procdff$3053' with positive edge clock.
Creating register for signal `\JtagBridge.\jtag_tap_instruction' using process `\JtagBridge.$proc$../Murax.v:2050$256'.
created $dff cell `$procdff$3054' with positive edge clock.
Creating register for signal `\JtagBridge.\jtag_tap_instructionShift' using process `\JtagBridge.$proc$../Murax.v:2050$256'.
created $dff cell `$procdff$3055' with positive edge clock.
Creating register for signal `\JtagBridge.\jtag_tap_bypass' using process `\JtagBridge.$proc$../Murax.v:2050$256'.
created $dff cell `$procdff$3056' with positive edge clock.
Creating register for signal `\JtagBridge.\jtag_idcodeArea_shifter' using process `\JtagBridge.$proc$../Murax.v:2050$256'.
created $dff cell `$procdff$3057' with positive edge clock.
Creating register for signal `\JtagBridge.\jtag_writeArea_valid' using process `\JtagBridge.$proc$../Murax.v:2050$256'.
created $dff cell `$procdff$3058' with positive edge clock.
Creating register for signal `\JtagBridge.\jtag_writeArea_data' using process `\JtagBridge.$proc$../Murax.v:2050$256'.
created $dff cell `$procdff$3059' with positive edge clock.
Creating register for signal `\JtagBridge.\jtag_readArea_full_shifter' using process `\JtagBridge.$proc$../Murax.v:2050$256'.
created $dff cell `$procdff$3060' with positive edge clock.
Creating register for signal `\JtagBridge.\system_rsp_valid' using process `\JtagBridge.$proc$../Murax.v:2039$255'.
created $dff cell `$procdff$3061' with positive edge clock.
Creating register for signal `\JtagBridge.\system_rsp_payload_error' using process `\JtagBridge.$proc$../Murax.v:2039$255'.
created $dff cell `$procdff$3062' with positive edge clock.
Creating register for signal `\JtagBridge.\system_rsp_payload_data' using process `\JtagBridge.$proc$../Murax.v:2039$255'.
created $dff cell `$procdff$3063' with positive edge clock.
Creating register for signal `\SystemDebugger.\dispatcher_dataShifter' using process `\SystemDebugger.$proc$../Murax.v:1718$213'.
created $dff cell `$procdff$3064' with positive edge clock.
Creating register for signal `\SystemDebugger.\dispatcher_headerShifter' using process `\SystemDebugger.$proc$../Murax.v:1718$213'.
created $dff cell `$procdff$3065' with positive edge clock.
Creating register for signal `\SystemDebugger.\dispatcher_dataLoaded' using process `\SystemDebugger.$proc$../Murax.v:1692$211'.
created $adff cell `$procdff$3066' with positive edge clock and positive level reset.
Creating register for signal `\SystemDebugger.\dispatcher_headerLoaded' using process `\SystemDebugger.$proc$../Murax.v:1692$211'.
created $adff cell `$procdff$3067' with positive edge clock and positive level reset.
Creating register for signal `\SystemDebugger.\dispatcher_counter' using process `\SystemDebugger.$proc$../Murax.v:1692$211'.
created $adff cell `$procdff$3068' with positive edge clock and positive level reset.
Creating register for signal `\MuraxPipelinedMemoryBusRam.\_zz_io_bus_rsp_valid' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1633$198'.
created $adff cell `$procdff$3069' with positive edge clock and positive level reset.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol0$../Murax.v:1614$153_ADDR' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3070' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol0$../Murax.v:1614$153_DATA' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3071' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol0$../Murax.v:1614$153_EN' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3072' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol1$../Murax.v:1617$154_ADDR' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3073' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol1$../Murax.v:1617$154_DATA' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3074' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol1$../Murax.v:1617$154_EN' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3075' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol2$../Murax.v:1620$155_ADDR' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3076' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol2$../Murax.v:1620$155_DATA' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3077' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol2$../Murax.v:1620$155_EN' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3078' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol3$../Murax.v:1623$156_ADDR' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3079' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol3$../Murax.v:1623$156_DATA' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3080' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.$memwr$\ram_symbol3$../Murax.v:1623$156_EN' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
created $dff cell `$procdff$3081' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.\_zz_ramsymbol_read' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'.
created $dff cell `$procdff$3082' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.\_zz_ramsymbol_read_1' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'.
created $dff cell `$procdff$3083' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.\_zz_ramsymbol_read_2' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'.
created $dff cell `$procdff$3084' with positive edge clock.
Creating register for signal `\MuraxPipelinedMemoryBusRam.\_zz_ramsymbol_read_3' using process `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'.
created $dff cell `$procdff$3085' with positive edge clock.
Creating register for signal `\PipelinedMemoryBusToApbBridge.\io_pipelinedMemoryBus_cmd_rData_write' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'.
created $dff cell `$procdff$3086' with positive edge clock.
Creating register for signal `\PipelinedMemoryBusToApbBridge.\io_pipelinedMemoryBus_cmd_rData_address' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'.
created $dff cell `$procdff$3087' with positive edge clock.
Creating register for signal `\PipelinedMemoryBusToApbBridge.\io_pipelinedMemoryBus_cmd_rData_data' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'.
created $dff cell `$procdff$3088' with positive edge clock.
Creating register for signal `\PipelinedMemoryBusToApbBridge.\io_pipelinedMemoryBus_cmd_rData_mask' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'.
created $dff cell `$procdff$3089' with positive edge clock.
Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_payload_data' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'.
created $dff cell `$procdff$3090' with positive edge clock.
Creating register for signal `\PipelinedMemoryBusToApbBridge.\io_pipelinedMemoryBus_cmd_rValid' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'.
created $adff cell `$procdff$3091' with positive edge clock and positive level reset.
Creating register for signal `\PipelinedMemoryBusToApbBridge.\pipelinedMemoryBusStage_rsp_regNext_valid' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'.
created $adff cell `$procdff$3092' with positive edge clock and positive level reset.
Creating register for signal `\PipelinedMemoryBusToApbBridge.\state' using process `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'.
created $adff cell `$procdff$3093' with positive edge clock and positive level reset.
Creating register for signal `\Apb3Gpio.\io_gpio_write_driver' using process `\Apb3Gpio.$proc$../Murax.v:1433$142'.
created $dff cell `$procdff$3094' with positive edge clock.
Creating register for signal `\Apb3Gpio.\io_gpio_writeEnable_driver' using process `\Apb3Gpio.$proc$../Murax.v:1417$141'.
created $adff cell `$procdff$3095' with positive edge clock and positive level reset.
Creating register for signal `\Apb3UartCtrl.\uartCtrl_1_io_readBreak_regNext' using process `\Apb3UartCtrl.$proc$../Murax.v:1353$127'.
created $dff cell `$procdff$3096' with positive edge clock.
Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_writeIntEnable' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'.
created $adff cell `$procdff$3097' with positive edge clock and positive level reset.
Creating register for signal `\Apb3UartCtrl.\bridge_interruptCtrl_readIntEnable' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'.
created $adff cell `$procdff$3098' with positive edge clock and positive level reset.
Creating register for signal `\Apb3UartCtrl.\bridge_misc_readError' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'.
created $adff cell `$procdff$3099' with positive edge clock and positive level reset.
Creating register for signal `\Apb3UartCtrl.\bridge_misc_readOverflowError' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'.
created $adff cell `$procdff$3100' with positive edge clock and positive level reset.
Creating register for signal `\Apb3UartCtrl.\bridge_misc_breakDetected' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'.
created $adff cell `$procdff$3101' with positive edge clock and positive level reset.
Creating register for signal `\Apb3UartCtrl.\bridge_misc_doBreak' using process `\Apb3UartCtrl.$proc$../Murax.v:1297$126'.
created $adff cell `$procdff$3102' with positive edge clock and positive level reset.
Creating register for signal `\MuraxApb3Timer.\_zz_io_limit' using process `\MuraxApb3Timer.$proc$../Murax.v:952$91'.
created $dff cell `$procdff$3103' with positive edge clock.
Creating register for signal `\MuraxApb3Timer.\timerA_io_limit_driver' using process `\MuraxApb3Timer.$proc$../Murax.v:952$91'.
created $dff cell `$procdff$3104' with positive edge clock.
Creating register for signal `\MuraxApb3Timer.\timerB_io_limit_driver' using process `\MuraxApb3Timer.$proc$../Murax.v:952$91'.
created $dff cell `$procdff$3105' with positive edge clock.
Creating register for signal `\MuraxApb3Timer.\timerABridge_ticksEnable' using process `\MuraxApb3Timer.$proc$../Murax.v:920$90'.
created $adff cell `$procdff$3106' with positive edge clock and positive level reset.
Creating register for signal `\MuraxApb3Timer.\timerABridge_clearsEnable' using process `\MuraxApb3Timer.$proc$../Murax.v:920$90'.
created $adff cell `$procdff$3107' with positive edge clock and positive level reset.
Creating register for signal `\MuraxApb3Timer.\timerBBridge_ticksEnable' using process `\MuraxApb3Timer.$proc$../Murax.v:920$90'.
created $adff cell `$procdff$3108' with positive edge clock and positive level reset.
Creating register for signal `\MuraxApb3Timer.\timerBBridge_clearsEnable' using process `\MuraxApb3Timer.$proc$../Murax.v:920$90'.
created $adff cell `$procdff$3109' with positive edge clock and positive level reset.
Creating register for signal `\MuraxApb3Timer.\interruptCtrl_1_io_masks_driver' using process `\MuraxApb3Timer.$proc$../Murax.v:920$90'.
created $adff cell `$procdff$3110' with positive edge clock and positive level reset.
Creating register for signal `\Apb3Router.\selIndex' using process `\Apb3Router.$proc$../Murax.v:633$42'.
created $dff cell `$procdff$3111' with positive edge clock.
Creating register for signal `\Murax.\system_cpu_debug_bus_cmd_fire_regNext' using process `\Murax.$proc$../Murax.v:538$39'.
created $adff cell `$procdff$3112' with positive edge clock and positive level reset.
Creating register for signal `\Murax.\system_cpu_debug_resetOut_regNext' using process `\Murax.$proc$../Murax.v:534$38'.
created $dff cell `$procdff$3113' with positive edge clock.
Creating register for signal `\Murax.\system_cpu_dBus_cmd_rData_wr' using process `\Murax.$proc$../Murax.v:522$37'.
created $dff cell `$procdff$3114' with positive edge clock.
Creating register for signal `\Murax.\system_cpu_dBus_cmd_rData_address' using process `\Murax.$proc$../Murax.v:522$37'.
created $dff cell `$procdff$3115' with positive edge clock.
Creating register for signal `\Murax.\system_cpu_dBus_cmd_rData_data' using process `\Murax.$proc$../Murax.v:522$37'.
created $dff cell `$procdff$3116' with positive edge clock.
Creating register for signal `\Murax.\system_cpu_dBus_cmd_rData_size' using process `\Murax.$proc$../Murax.v:522$37'.
created $dff cell `$procdff$3117' with positive edge clock.
Creating register for signal `\Murax.\system_mainBusDecoder_logic_rspSourceId' using process `\Murax.$proc$../Murax.v:522$37'.
created $dff cell `$procdff$3118' with positive edge clock.
Creating register for signal `\Murax.\system_cpu_dBus_cmd_rValid' using process `\Murax.$proc$../Murax.v:497$36'.
created $adff cell `$procdff$3119' with positive edge clock and positive level reset.
Creating register for signal `\Murax.\system_mainBusDecoder_logic_rspPending' using process `\Murax.$proc$../Murax.v:497$36'.
created $adff cell `$procdff$3120' with positive edge clock and positive level reset.
Creating register for signal `\Murax.\system_mainBusDecoder_logic_rspNoHit' using process `\Murax.$proc$../Murax.v:497$36'.
created $adff cell `$procdff$3121' with positive edge clock and positive level reset.
Creating register for signal `\Murax.\resetCtrl_mainClkReset' using process `\Murax.$proc$../Murax.v:489$35'.
created $dff cell `$procdff$3122' with positive edge clock.
Creating register for signal `\Murax.\resetCtrl_systemReset' using process `\Murax.$proc$../Murax.v:489$35'.
created $dff cell `$procdff$3123' with positive edge clock.
Creating register for signal `\Murax.\resetCtrl_systemClkResetCounter' using process `\Murax.$proc$../Murax.v:480$33'.
created $dff cell `$procdff$3124' with positive edge clock.
3.1.9. Executing PROC_MEMWR pass (convert process memory writes to cells).
3.1.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `BufferCC.$proc$../Murax.v:6826$1043'.
Removing empty process `BufferCC_1.$proc$../Murax.v:6807$1042'.
Found and cleaned up 7 empty switches in `\UartCtrlTx.$proc$../Murax.v:6760$1038'.
Removing empty process `UartCtrlTx.$proc$../Murax.v:6760$1038'.
Found and cleaned up 9 empty switches in `\UartCtrlTx.$proc$../Murax.v:6714$1034'.
Removing empty process `UartCtrlTx.$proc$../Murax.v:6714$1034'.
Found and cleaned up 3 empty switches in `\UartCtrlTx.$proc$../Murax.v:6688$1027'.
Removing empty process `UartCtrlTx.$proc$../Murax.v:6688$1027'.
Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$../Murax.v:6669$1025'.
Removing empty process `UartCtrlTx.$proc$../Murax.v:6669$1025'.
Found and cleaned up 2 empty switches in `\UartCtrlTx.$proc$../Murax.v:6658$1023'.
Removing empty process `UartCtrlTx.$proc$../Murax.v:6658$1023'.
Found and cleaned up 1 empty switch in `\UartCtrlTx.$proc$../Murax.v:6648$1020'.
Removing empty process `UartCtrlTx.$proc$../Murax.v:6648$1020'.
Found and cleaned up 10 empty switches in `\UartCtrlRx.$proc$../Murax.v:6519$998'.
Removing empty process `UartCtrlRx.$proc$../Murax.v:6519$998'.
Found and cleaned up 16 empty switches in `\UartCtrlRx.$proc$../Murax.v:6440$985'.
Removing empty process `UartCtrlRx.$proc$../Murax.v:6440$985'.
Found and cleaned up 2 empty switches in `\UartCtrlRx.$proc$../Murax.v:6418$970'.
Removing empty process `UartCtrlRx.$proc$../Murax.v:6418$970'.
Found and cleaned up 5 empty switches in `\UartCtrlRx.$proc$../Murax.v:6389$968'.
Removing empty process `UartCtrlRx.$proc$../Murax.v:6389$968'.
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6283$963'.
Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6283$963'.
Found and cleaned up 2 empty switches in `\StreamFifoLowLatency.$proc$../Murax.v:6270$962'.
Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6270$962'.
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6259$959'.
Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6259$959'.
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6251$958'.
Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6251$958'.
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6243$957'.
Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6243$957'.
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6224$948'.
Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6224$948'.
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6217$947'.
Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6217$947'.
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6208$945'.
Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6208$945'.
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6201$944'.
Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6201$944'.
Found and cleaned up 1 empty switch in `\StreamFifoLowLatency.$proc$../Murax.v:6194$943'.
Removing empty process `StreamFifoLowLatency.$proc$../Murax.v:6194$943'.
Removing empty process `FlowCCByToggle.$proc$../Murax.v:6145$941'.
Found and cleaned up 1 empty switch in `\FlowCCByToggle.$proc$../Murax.v:6137$940'.
Removing empty process `FlowCCByToggle.$proc$../Murax.v:6137$940'.
Found and cleaned up 1 empty switch in `\FlowCCByToggle.$proc$../Murax.v:6129$938'.
Removing empty process `FlowCCByToggle.$proc$../Murax.v:6129$938'.
Removing empty process `BufferCC_2.$proc$../Murax.v:6076$936'.
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$../Murax.v:6049$934'.
Removing empty process `UartCtrl.$proc$../Murax.v:6049$934'.
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$../Murax.v:6035$933'.
Removing empty process `UartCtrl.$proc$../Murax.v:6035$933'.
Found and cleaned up 1 empty switch in `\UartCtrl.$proc$../Murax.v:6028$932'.
Removing empty process `UartCtrl.$proc$../Murax.v:6028$932'.
Found and cleaned up 2 empty switches in `\StreamFifo.$proc$../Murax.v:5914$929'.
Removing empty process `StreamFifo.$proc$../Murax.v:5914$929'.
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5895$910'.
Removing empty process `StreamFifo.$proc$../Murax.v:5895$910'.
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5886$907'.
Removing empty process `StreamFifo.$proc$../Murax.v:5886$907'.
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5879$906'.
Removing empty process `StreamFifo.$proc$../Murax.v:5879$906'.
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5872$904'.
Removing empty process `StreamFifo.$proc$../Murax.v:5872$904'.
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5863$901'.
Removing empty process `StreamFifo.$proc$../Murax.v:5863$901'.
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5856$900'.
Removing empty process `StreamFifo.$proc$../Murax.v:5856$900'.
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5849$899'.
Removing empty process `StreamFifo.$proc$../Murax.v:5849$899'.
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5843$892'.
Removing empty process `StreamFifo.$proc$../Murax.v:5843$892'.
Found and cleaned up 1 empty switch in `\StreamFifo.$proc$../Murax.v:5837$890'.
Removing empty process `StreamFifo.$proc$../Murax.v:5837$890'.
Found and cleaned up 1 empty switch in `\Prescaler.$proc$../Murax.v:5773$886'.
Removing empty process `Prescaler.$proc$../Murax.v:5773$886'.
Found and cleaned up 2 empty switches in `\Timer.$proc$../Murax.v:5748$882'.
Removing empty process `Timer.$proc$../Murax.v:5748$882'.
Found and cleaned up 2 empty switches in `\Timer.$proc$../Murax.v:5735$881'.
Removing empty process `Timer.$proc$../Murax.v:5735$881'.
Removing empty process `InterruptCtrl.$proc$../Murax.v:5701$872'.
Removing empty process `BufferCC_3.$proc$../Murax.v:5681$870'.
Found and cleaned up 2 empty switches in `\MuraxMasterArbiter.$proc$../Murax.v:5653$869'.
Removing empty process `MuraxMasterArbiter.$proc$../Murax.v:5653$869'.
Found and cleaned up 1 empty switch in `\MuraxMasterArbiter.$proc$../Murax.v:5637$860'.
Removing empty process `MuraxMasterArbiter.$proc$../Murax.v:5637$860'.
Found and cleaned up 1 empty switch in `\MuraxMasterArbiter.$proc$../Murax.v:5630$857'.
Removing empty process `MuraxMasterArbiter.$proc$../Murax.v:5630$857'.
Found and cleaned up 1 empty switch in `\MuraxMasterArbiter.$proc$../Murax.v:5615$855'.
Removing empty process `MuraxMasterArbiter.$proc$../Murax.v:5615$855'.
Found and cleaned up 1 empty switch in `\MuraxMasterArbiter.$proc$../Murax.v:5605$851'.
Removing empty process `MuraxMasterArbiter.$proc$../Murax.v:5605$851'.
Found and cleaned up 17 empty switches in `\VexRiscv.$proc$../Murax.v:5502$850'.
Removing empty process `VexRiscv.$proc$../Murax.v:5502$850'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$../Murax.v:5485$847'.
Removing empty process `VexRiscv.$proc$../Murax.v:5485$847'.
Found and cleaned up 63 empty switches in `\VexRiscv.$proc$../Murax.v:5280$840'.
Removing empty process `VexRiscv.$proc$../Murax.v:5280$840'.
Found and cleaned up 62 empty switches in `\VexRiscv.$proc$../Murax.v:5018$829'.
Removing empty process `VexRiscv.$proc$../Murax.v:5018$829'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:5007$821'.
Removing empty process `VexRiscv.$proc$../Murax.v:5007$821'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4998$820'.
Removing empty process `VexRiscv.$proc$../Murax.v:4998$820'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4989$819'.
Removing empty process `VexRiscv.$proc$../Murax.v:4989$819'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4980$818'.
Removing empty process `VexRiscv.$proc$../Murax.v:4980$818'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4963$811'.
Removing empty process `VexRiscv.$proc$../Murax.v:4963$811'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$../Murax.v:4841$690'.
Removing empty process `VexRiscv.$proc$../Murax.v:4841$690'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4829$688'.
Removing empty process `VexRiscv.$proc$../Murax.v:4829$688'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$../Murax.v:4814$687'.
Removing empty process `VexRiscv.$proc$../Murax.v:4814$687'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4794$679'.
Removing empty process `VexRiscv.$proc$../Murax.v:4794$679'.
Removing empty process `VexRiscv.$proc$../Murax.v:4772$678'.
Removing empty process `VexRiscv.$proc$../Murax.v:4748$677'.
Removing empty process `VexRiscv.$proc$../Murax.v:4733$676'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4714$673'.
Removing empty process `VexRiscv.$proc$../Murax.v:4714$673'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4697$670'.
Removing empty process `VexRiscv.$proc$../Murax.v:4697$670'.
Found and cleaned up 12 empty switches in `\VexRiscv.$proc$../Murax.v:4642$648'.
Removing empty process `VexRiscv.$proc$../Murax.v:4642$648'.
Found and cleaned up 12 empty switches in `\VexRiscv.$proc$../Murax.v:4609$647'.
Removing empty process `VexRiscv.$proc$../Murax.v:4609$647'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4596$643'.
Removing empty process `VexRiscv.$proc$../Murax.v:4596$643'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4583$632'.
Removing empty process `VexRiscv.$proc$../Murax.v:4583$632'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4566$631'.
Removing empty process `VexRiscv.$proc$../Murax.v:4566$631'.
Removing empty process `VexRiscv.$proc$../Murax.v:4543$630'.
Removing empty process `VexRiscv.$proc$../Murax.v:4519$629'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4501$628'.
Removing empty process `VexRiscv.$proc$../Murax.v:4501$628'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4487$627'.
Removing empty process `VexRiscv.$proc$../Murax.v:4487$627'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4473$623'.
Removing empty process `VexRiscv.$proc$../Murax.v:4473$623'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4466$622'.
Removing empty process `VexRiscv.$proc$../Murax.v:4466$622'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4459$621'.
Removing empty process `VexRiscv.$proc$../Murax.v:4459$621'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4452$619'.
Removing empty process `VexRiscv.$proc$../Murax.v:4452$619'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4411$589'.
Removing empty process `VexRiscv.$proc$../Murax.v:4411$589'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4399$581'.
Removing empty process `VexRiscv.$proc$../Murax.v:4399$581'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4392$578'.
Removing empty process `VexRiscv.$proc$../Murax.v:4392$578'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:4381$574'.
Removing empty process `VexRiscv.$proc$../Murax.v:4381$574'.
Found and cleaned up 8 empty switches in `\VexRiscv.$proc$../Murax.v:4354$573'.
Removing empty process `VexRiscv.$proc$../Murax.v:4354$573'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4337$560'.
Removing empty process `VexRiscv.$proc$../Murax.v:4337$560'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4326$559'.
Removing empty process `VexRiscv.$proc$../Murax.v:4326$559'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4316$556'.
Removing empty process `VexRiscv.$proc$../Murax.v:4316$556'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4291$537'.
Removing empty process `VexRiscv.$proc$../Murax.v:4291$537'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4276$535'.
Removing empty process `VexRiscv.$proc$../Murax.v:4276$535'.
Removing empty process `VexRiscv.$proc$../Murax.v:4256$534'.
Removing empty process `VexRiscv.$proc$../Murax.v:4227$531'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4208$528'.
Removing empty process `VexRiscv.$proc$../Murax.v:4208$528'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4191$520'.
Removing empty process `VexRiscv.$proc$../Murax.v:4191$520'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4175$512'.
Removing empty process `VexRiscv.$proc$../Murax.v:4175$512'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4165$502'.
Removing empty process `VexRiscv.$proc$../Murax.v:4165$502'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4138$493'.
Removing empty process `VexRiscv.$proc$../Murax.v:4138$493'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4102$477'.
Removing empty process `VexRiscv.$proc$../Murax.v:4102$477'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:4073$461'.
Removing empty process `VexRiscv.$proc$../Murax.v:4073$461'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4045$447'.
Removing empty process `VexRiscv.$proc$../Murax.v:4045$447'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4026$438'.
Removing empty process `VexRiscv.$proc$../Murax.v:4026$438'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4017$436'.
Removing empty process `VexRiscv.$proc$../Murax.v:4017$436'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:4007$431'.
Removing empty process `VexRiscv.$proc$../Murax.v:4007$431'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3998$428'.
Removing empty process `VexRiscv.$proc$../Murax.v:3998$428'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3987$424'.
Removing empty process `VexRiscv.$proc$../Murax.v:3987$424'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3980$423'.
Removing empty process `VexRiscv.$proc$../Murax.v:3980$423'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3973$422'.
Removing empty process `VexRiscv.$proc$../Murax.v:3973$422'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3966$421'.
Removing empty process `VexRiscv.$proc$../Murax.v:3966$421'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$../Murax.v:3950$420'.
Removing empty process `VexRiscv.$proc$../Murax.v:3950$420'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3940$419'.
Removing empty process `VexRiscv.$proc$../Murax.v:3940$419'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3933$418'.
Removing empty process `VexRiscv.$proc$../Murax.v:3933$418'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3920$417'.
Removing empty process `VexRiscv.$proc$../Murax.v:3920$417'.
Found and cleaned up 6 empty switches in `\VexRiscv.$proc$../Murax.v:3899$416'.
Removing empty process `VexRiscv.$proc$../Murax.v:3899$416'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3885$415'.
Removing empty process `VexRiscv.$proc$../Murax.v:3885$415'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3877$414'.
Removing empty process `VexRiscv.$proc$../Murax.v:3877$414'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3868$413'.
Removing empty process `VexRiscv.$proc$../Murax.v:3868$413'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3860$412'.
Removing empty process `VexRiscv.$proc$../Murax.v:3860$412'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3852$411'.
Removing empty process `VexRiscv.$proc$../Murax.v:3852$411'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3843$410'.
Removing empty process `VexRiscv.$proc$../Murax.v:3843$410'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3834$409'.
Removing empty process `VexRiscv.$proc$../Murax.v:3834$409'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3827$408'.
Removing empty process `VexRiscv.$proc$../Murax.v:3827$408'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3820$407'.
Removing empty process `VexRiscv.$proc$../Murax.v:3820$407'.
Found and cleaned up 5 empty switches in `\VexRiscv.$proc$../Murax.v:3803$406'.
Removing empty process `VexRiscv.$proc$../Murax.v:3803$406'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3794$405'.
Removing empty process `VexRiscv.$proc$../Murax.v:3794$405'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$../Murax.v:3781$404'.
Removing empty process `VexRiscv.$proc$../Murax.v:3781$404'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3770$403'.
Removing empty process `VexRiscv.$proc$../Murax.v:3770$403'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3759$402'.
Removing empty process `VexRiscv.$proc$../Murax.v:3759$402'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3741$401'.
Removing empty process `VexRiscv.$proc$../Murax.v:3741$401'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$../Murax.v:3724$400'.
Removing empty process `VexRiscv.$proc$../Murax.v:3724$400'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3717$399'.
Removing empty process `VexRiscv.$proc$../Murax.v:3717$399'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3709$397'.
Removing empty process `VexRiscv.$proc$../Murax.v:3709$397'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3102$374'.
Removing empty process `VexRiscv.$proc$../Murax.v:3102$374'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3096$372'.
Removing empty process `VexRiscv.$proc$../Murax.v:3096$372'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$../Murax.v:3090$370'.
Removing empty process `VexRiscv.$proc$../Murax.v:3090$370'.
Removing empty process `JtagBridge.$proc$../Murax.v:2092$262'.
Found and cleaned up 8 empty switches in `\JtagBridge.$proc$../Murax.v:2050$256'.
Removing empty process `JtagBridge.$proc$../Murax.v:2050$256'.
Found and cleaned up 2 empty switches in `\JtagBridge.$proc$../Murax.v:2039$255'.
Removing empty process `JtagBridge.$proc$../Murax.v:2039$255'.
Found and cleaned up 3 empty switches in `\JtagBridge.$proc$../Murax.v:1995$235'.
Removing empty process `JtagBridge.$proc$../Murax.v:1995$235'.
Found and cleaned up 2 empty switches in `\JtagBridge.$proc$../Murax.v:1977$234'.
Removing empty process `JtagBridge.$proc$../Murax.v:1977$234'.
Found and cleaned up 1 empty switch in `\JtagBridge.$proc$../Murax.v:1923$217'.
Removing empty process `JtagBridge.$proc$../Murax.v:1923$217'.
Found and cleaned up 2 empty switches in `\SystemDebugger.$proc$../Murax.v:1718$213'.
Removing empty process `SystemDebugger.$proc$../Murax.v:1718$213'.
Found and cleaned up 5 empty switches in `\SystemDebugger.$proc$../Murax.v:1692$211'.
Removing empty process `SystemDebugger.$proc$../Murax.v:1692$211'.
Removing empty process `MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1633$198'.
Found and cleaned up 4 empty switches in `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
Removing empty process `MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1612$163'.
Found and cleaned up 1 empty switch in `\MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'.
Removing empty process `MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1603$158'.
Removing empty process `MuraxPipelinedMemoryBusRam.$proc$../Murax.v:1600$157'.
Found and cleaned up 1 empty switch in `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'.
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1557$152'.
Found and cleaned up 4 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'.
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1534$151'.
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1523$147'.
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1523$147'.
Found and cleaned up 2 empty switches in `\PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1509$145'.
Removing empty process `PipelinedMemoryBusToApbBridge.$proc$../Murax.v:1509$145'.
Found and cleaned up 2 empty switches in `\Apb3Gpio.$proc$../Murax.v:1433$142'.
Removing empty process `Apb3Gpio.$proc$../Murax.v:1433$142'.
Found and cleaned up 2 empty switches in `\Apb3Gpio.$proc$../Murax.v:1417$141'.
Removing empty process `Apb3Gpio.$proc$../Murax.v:1417$141'.
Found and cleaned up 1 empty switch in `\Apb3Gpio.$proc$../Murax.v:1393$128'.
Removing empty process `Apb3Gpio.$proc$../Murax.v:1393$128'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1353$127'.
Found and cleaned up 15 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1297$126'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1297$126'.
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1282$125'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1282$125'.
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1268$124'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1268$124'.
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1254$123'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1254$123'.
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1238$118'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1238$118'.
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1224$117'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1224$117'.
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1208$112'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1208$112'.
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$../Murax.v:1200$111'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1200$111'.
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$../Murax.v:1193$110'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1193$110'.
Found and cleaned up 2 empty switches in `\Apb3UartCtrl.$proc$../Murax.v:1177$109'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1177$109'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1173$108'.
Found and cleaned up 1 empty switch in `\Apb3UartCtrl.$proc$../Murax.v:1141$94'.
Removing empty process `Apb3UartCtrl.$proc$../Murax.v:1141$94'.
Found and cleaned up 4 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:952$91'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:952$91'.
Found and cleaned up 4 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:920$90'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:920$90'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:914$88'.
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:901$87'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:901$87'.
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:886$81'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:886$81'.
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:873$80'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:873$80'.
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:863$79'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:863$79'.
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:848$73'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:848$73'.
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:835$72'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:835$72'.
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:825$71'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:825$71'.
Found and cleaned up 2 empty switches in `\MuraxApb3Timer.$proc$../Murax.v:812$70'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:812$70'.
Found and cleaned up 1 empty switch in `\MuraxApb3Timer.$proc$../Murax.v:770$57'.
Removing empty process `MuraxApb3Timer.$proc$../Murax.v:770$57'.
Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$../Murax.v:679$54'.
Removing empty process `Apb3Decoder.$proc$../Murax.v:679$54'.
Found and cleaned up 1 empty switch in `\Apb3Decoder.$proc$../Murax.v:671$53'.
Removing empty process `Apb3Decoder.$proc$../Murax.v:671$53'.
Removing empty process `Apb3Decoder.$proc$../Murax.v:665$43'.
Removing empty process `Apb3Router.$proc$../Murax.v:633$42'.
Found and cleaned up 1 empty switch in `\Apb3Router.$proc$../Murax.v:593$41'.
Removing empty process `Apb3Router.$proc$../Murax.v:593$41'.
Removing empty process `Murax.$proc$../Murax.v:0$40'.
Removing empty process `Murax.$proc$../Murax.v:538$39'.
Removing empty process `Murax.$proc$../Murax.v:534$38'.
Found and cleaned up 2 empty switches in `\Murax.$proc$../Murax.v:522$37'.
Removing empty process `Murax.$proc$../Murax.v:522$37'.
Found and cleaned up 5 empty switches in `\Murax.$proc$../Murax.v:497$36'.
Removing empty process `Murax.$proc$../Murax.v:497$36'.
Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:489$35'.
Removing empty process `Murax.$proc$../Murax.v:489$35'.
Found and cleaned up 2 empty switches in `\Murax.$proc$../Murax.v:480$33'.
Removing empty process `Murax.$proc$../Murax.v:480$33'.
Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:467$19'.
Removing empty process `Murax.$proc$../Murax.v:467$19'.
Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:458$15'.
Removing empty process `Murax.$proc$../Murax.v:458$15'.
Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:449$11'.
Removing empty process `Murax.$proc$../Murax.v:449$11'.
Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:419$5'.
Removing empty process `Murax.$proc$../Murax.v:419$5'.
Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:412$4'.
Removing empty process `Murax.$proc$../Murax.v:412$4'.
Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:402$2'.
Removing empty process `Murax.$proc$../Murax.v:402$2'.
Found and cleaned up 1 empty switch in `\Murax.$proc$../Murax.v:395$1'.
Removing empty process `Murax.$proc$../Murax.v:395$1'.
Cleaned up 486 empty switches.
3.1.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module UartCtrlTx.
<suppressed ~5 debug messages>
Optimizing module UartCtrlRx.
<suppressed ~18 debug messages>
Optimizing module StreamFifoLowLatency.
<suppressed ~6 debug messages>
Optimizing module FlowCCByToggle.
Optimizing module BufferCC_2.
Optimizing module UartCtrl.
<suppressed ~1 debug messages>
Optimizing module StreamFifo.
<suppressed ~1 debug messages>
Optimizing module Prescaler.
Optimizing module Timer.
Optimizing module InterruptCtrl.
Optimizing module BufferCC_3.
Optimizing module MuraxMasterArbiter.
<suppressed ~1 debug messages>
Optimizing module VexRiscv.
<suppressed ~236 debug messages>
Optimizing module JtagBridge.
<suppressed ~9 debug messages>
Optimizing module SystemDebugger.
<suppressed ~8 debug messages>
Optimizing module MuraxPipelinedMemoryBusRam.
<suppressed ~2 debug messages>
Optimizing module PipelinedMemoryBusToApbBridge.
<suppressed ~7 debug messages>
Optimizing module Apb3Gpio.
<suppressed ~3 debug messages>
Optimizing module Apb3UartCtrl.
<suppressed ~11 debug messages>
Optimizing module MuraxApb3Timer.
<suppressed ~9 debug messages>
Optimizing module Apb3Decoder.
<suppressed ~2 debug messages>
Optimizing module Apb3Router.
<suppressed ~3 debug messages>
Optimizing module Murax.
<suppressed ~10 debug messages>
3.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module UartCtrlTx.
Optimizing module UartCtrlRx.
Optimizing module StreamFifoLowLatency.
Optimizing module FlowCCByToggle.
Optimizing module BufferCC_2.
Optimizing module UartCtrl.
Optimizing module StreamFifo.
Optimizing module Prescaler.
Optimizing module Timer.
Optimizing module InterruptCtrl.
Optimizing module BufferCC_3.
Optimizing module MuraxMasterArbiter.
Optimizing module VexRiscv.
Optimizing module JtagBridge.
Optimizing module SystemDebugger.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Apb3Gpio.
Optimizing module Apb3UartCtrl.
Optimizing module MuraxApb3Timer.
Optimizing module Apb3Decoder.
Optimizing module Apb3Router.
Optimizing module Murax.
3.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \VexRiscv..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Murax..
Removed 275 unused cells and 2158 unused wires.
<suppressed ~454 debug messages>
3.4. Executing CHECK pass (checking for obvious problems).
Checking module Apb3Decoder...
Checking module Apb3Gpio...
Checking module Apb3Router...
Checking module Apb3UartCtrl...
Checking module BufferCC...
Checking module BufferCC_1...
Checking module BufferCC_2...
Checking module BufferCC_3...
Checking module FlowCCByToggle...
Checking module InterruptCtrl...
Checking module JtagBridge...
Checking module Murax...
Warning: Wire Murax.\io_gpioA_read [31] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [30] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [29] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [28] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [27] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [26] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [25] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [24] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [23] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [22] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [21] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [20] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [19] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [18] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [17] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [16] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [15] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [14] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [13] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [12] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [11] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [10] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [9] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [8] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [7] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [6] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [5] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [4] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [3] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [2] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [1] is used but has no driver.
Warning: Wire Murax.\io_gpioA_read [0] is used but has no driver.
Checking module MuraxApb3Timer...
Checking module MuraxMasterArbiter...
Checking module MuraxPipelinedMemoryBusRam...
Checking module PipelinedMemoryBusToApbBridge...
Checking module Prescaler...
Checking module StreamFifo...
Checking module StreamFifoLowLatency...
Checking module SystemDebugger...
Checking module Timer...
Checking module UartCtrl...
Checking module UartCtrlRx...
Checking module UartCtrlTx...
Checking module VexRiscv...
Found and reported 32 problems.
3.5. Executing OPT pass (performing simple optimizations).
3.5.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
3.5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
<suppressed ~6 debug messages>
Finding identical cells in module `\Apb3Gpio'.
<suppressed ~6 debug messages>
Finding identical cells in module `\Apb3Router'.
<suppressed ~12 debug messages>
Finding identical cells in module `\Apb3UartCtrl'.
<suppressed ~90 debug messages>
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
<suppressed ~42 debug messages>
Finding identical cells in module `\Murax'.
<suppressed ~3 debug messages>
Finding identical cells in module `\MuraxApb3Timer'.
<suppressed ~81 debug messages>
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
<suppressed ~12 debug messages>
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
<suppressed ~72 debug messages>
Finding identical cells in module `\UartCtrlTx'.
<suppressed ~30 debug messages>
Finding identical cells in module `\VexRiscv'.
<suppressed ~150 debug messages>
Removed a total of 168 cells.
3.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $procmux$2574.
dead port 2/2 on $mux $procmux$2583.
dead port 2/2 on $mux $procmux$2592.
dead port 2/2 on $mux $procmux$2601.
dead port 2/2 on $mux $procmux$2610.
dead port 2/2 on $mux $procmux$2619.
dead port 2/2 on $mux $procmux$2634.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $procmux$2389.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $procmux$2724.
dead port 2/2 on $mux $procmux$2733.
dead port 2/2 on $mux $procmux$2742.
dead port 2/2 on $mux $procmux$2757.
dead port 2/2 on $mux $procmux$2766.
dead port 2/2 on $mux $procmux$2781.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Replacing known input bits on port A of cell $procmux$2496: \state -> 1'1
Analyzing evaluation results.
dead port 2/2 on $mux $procmux$2509.
dead port 2/2 on $mux $procmux$2518.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Replacing known input bits on port B of cell $procmux$2430: \dispatcher_headerLoaded -> 1'1
Replacing known input bits on port A of cell $procmux$2428: \dispatcher_headerLoaded -> 1'0
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $procmux$1129.
dead port 2/2 on $mux $procmux$1254.
dead port 2/2 on $mux $procmux$1263.
dead port 1/5 on $pmux $procmux$1266.
dead port 2/5 on $pmux $procmux$1266.
dead port 3/5 on $pmux $procmux$1266.
dead port 4/5 on $pmux $procmux$1266.
dead port 1/5 on $pmux $procmux$1275.
dead port 2/5 on $pmux $procmux$1275.
dead port 3/5 on $pmux $procmux$1275.
dead port 4/5 on $pmux $procmux$1275.
dead port 2/2 on $mux $procmux$1285.
dead port 2/2 on $mux $procmux$1287.
dead port 2/2 on $mux $procmux$1293.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $procmux$1095.
dead port 2/2 on $mux $procmux$1097.
dead port 2/2 on $mux $procmux$1104.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
dead port 2/2 on $mux $procmux$1845.
dead port 2/2 on $mux $procmux$1847.
dead port 2/2 on $mux $procmux$1853.
dead port 2/2 on $mux $procmux$1878.
dead port 2/2 on $mux $procmux$1880.
dead port 2/2 on $mux $procmux$1886.
dead port 2/2 on $mux $procmux$1915.
dead port 2/2 on $mux $procmux$1921.
dead port 2/2 on $mux $procmux$1933.
dead port 2/2 on $mux $procmux$1939.
dead port 2/2 on $mux $procmux$1951.
dead port 2/2 on $mux $procmux$1957.
dead port 2/2 on $mux $procmux$1966.
dead port 2/2 on $mux $procmux$1981.
dead port 2/2 on $mux $procmux$1987.
dead port 2/2 on $mux $procmux$1999.
dead port 2/2 on $mux $procmux$2005.
dead port 2/2 on $mux $procmux$2017.
dead port 2/2 on $mux $procmux$2023.
dead port 2/2 on $mux $procmux$2032.
dead port 2/2 on $mux $procmux$2194.
dead port 2/2 on $mux $procmux$2227.
dead port 2/2 on $mux $procmux$2260.
dead port 2/2 on $mux $procmux$2269.
dead port 2/2 on $mux $procmux$2284.
dead port 2/2 on $mux $procmux$2293.
Removed 59 multiplexer ports.
<suppressed ~318 debug messages>
3.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
New ctrl vector for $pmux cell $procmux$2359: { $procmux$2362_CMP $auto$opt_reduce.cc:134:opt_pmux$3132 }
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Consolidated identical input bits for $mux cell $procmux$2445:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175
New ports: A=1'0, B=1'1, Y=$0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0]
New connections: $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [7:1] = { $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] $0$memwr$\ram_symbol3$../Murax.v:1623$156_EN[7:0]$175 [0] }
Consolidated identical input bits for $mux cell $procmux$2454:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172
New ports: A=1'0, B=1'1, Y=$0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0]
New connections: $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [7:1] = { $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] $0$memwr$\ram_symbol2$../Murax.v:1620$155_EN[7:0]$172 [0] }
Consolidated identical input bits for $mux cell $procmux$2463:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169
New ports: A=1'0, B=1'1, Y=$0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0]
New connections: $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [7:1] = { $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] $0$memwr$\ram_symbol1$../Murax.v:1617$154_EN[7:0]$169 [0] }
Consolidated identical input bits for $mux cell $procmux$2472:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166
New ports: A=1'0, B=1'1, Y=$0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0]
New connections: $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [7:1] = { $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] $0$memwr$\ram_symbol0$../Murax.v:1614$153_EN[7:0]$166 [0] }
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Consolidated identical input bits for $mux cell $procmux$1375:
Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895
New ports: A=1'0, B=1'1, Y=$0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0]
New connections: $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [7:1] = { $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] $0$memwr$\logic_ram$../Murax.v:5845$888_EN[7:0]$895 [0] }
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
New ctrl vector for $pmux cell $procmux$1296: { $auto$opt_reduce.cc:134:opt_pmux$3134 $procmux$1172_CMP }
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
New ctrl vector for $pmux cell $procmux$1896: { $procmux$1899_CMP $auto$opt_reduce.cc:134:opt_pmux$3136 }
New ctrl vector for $pmux cell $procmux$2154: $auto$opt_reduce.cc:134:opt_pmux$3138
Consolidated identical input bits for $mux cell $procmux$2335:
Old ports: A=0, B=32'11111111111111111111111111111111, Y=$0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377
New ports: A=1'0, B=1'1, Y=$0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0]
New connections: $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [31:1] = { $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] $0$memwr$\RegFilePlugin_regFile$../Murax.v:3104$264_EN[31:0]$377 [0] }
Optimizing cells in module \VexRiscv.
Performed a total of 10 changes.
3.5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
<suppressed ~27 debug messages>
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
<suppressed ~12 debug messages>
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
<suppressed ~12 debug messages>
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
<suppressed ~6 debug messages>
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
<suppressed ~3 debug messages>
Finding identical cells in module `\UartCtrlTx'.
<suppressed ~3 debug messages>
Finding identical cells in module `\VexRiscv'.
<suppressed ~21 debug messages>
Removed a total of 28 cells.
3.5.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $procdff$3041 ($adff) from module VexRiscv.
3.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
Removed 0 unused cells and 250 unused wires.
<suppressed ~31 debug messages>
3.5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
<suppressed ~3 debug messages>
3.5.9. Rerunning OPT passes. (Maybe there is more to do..)
3.5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~310 debug messages>
3.5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
New ctrl vector for $pmux cell $procmux$2396: { $procmux$2410_CMP $auto$opt_reduce.cc:134:opt_pmux$3144 $procmux$2407_CMP $procmux$2406_CMP $procmux$2405_CMP $procmux$2403_CMP $auto$opt_reduce.cc:134:opt_pmux$3142 $procmux$2400_CMP $procmux$2399_CMP $procmux$2398_CMP $auto$opt_reduce.cc:134:opt_pmux$3140 }
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
New ctrl vector for $pmux cell $procmux$1171: { $procmux$1130_CMP $auto$opt_reduce.cc:134:opt_pmux$3146 }
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
New ctrl vector for $pmux cell $procmux$1048: { $procmux$1054_CMP $auto$opt_reduce.cc:134:opt_pmux$3148 }
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Performed a total of 3 changes.
3.5.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
3.5.13. Executing OPT_DFF pass (perform DFF optimizations).
3.5.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>
3.5.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
3.5.16. Rerunning OPT passes. (Maybe there is more to do..)
3.5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~310 debug messages>
3.5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Performed a total of 0 changes.
3.5.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
3.5.20. Executing OPT_DFF pass (perform DFF optimizations).
3.5.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
3.5.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
3.5.23. Finished OPT passes. (There is nothing left to do.)
3.6. Executing FSM pass (extract and optimize FSM).
3.6.1. Executing FSM_DETECT pass (finding FSMs in design).
Found FSM state register JtagBridge.jtag_tap_fsm_state.
Found FSM state register UartCtrlRx.stateMachine_state.
Found FSM state register UartCtrlTx.stateMachine_state.
Not marking VexRiscv.CsrPlugin_interrupt_code as FSM state register:
Users of register don't seem to benefit from recoding.
Found FSM state register VexRiscv.CsrPlugin_interrupt_targetPrivilege.
Not marking VexRiscv.switch_Fetcher_l362 as FSM state register:
Users of register don't seem to benefit from recoding.
3.6.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\jtag_tap_fsm_state' from module `\JtagBridge'.
found $dff cell for state register: $procdff$3053
root of input selection tree: \_zz_jtag_tap_fsm_stateNext
found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$3140
found ctrl input: $procmux$2398_CMP
found ctrl input: $procmux$2399_CMP
found ctrl input: $procmux$2400_CMP
found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$3142
found ctrl input: $procmux$2403_CMP
found ctrl input: $procmux$2405_CMP
found ctrl input: $procmux$2406_CMP
found ctrl input: $procmux$2407_CMP
found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$3144
found ctrl input: $procmux$2410_CMP
found ctrl input: \io_jtag_tms
found state code: 4'0001
found state code: 4'0000
found state code: 4'1001
found state code: 4'1011
found state code: 4'1111
found state code: 4'1101
found state code: 4'1110
found state code: 4'1100
found state code: 4'1010
found state code: 4'0010
found state code: 4'0100
found state code: 4'1000
found state code: 4'0110
found state code: 4'0111
found state code: 4'0101
found state code: 4'0011
found ctrl output: \jtag_idcodeArea_ctrl_capture
found ctrl output: \jtag_idcodeArea_ctrl_shift
found ctrl output: \when_JtagTap_l120
found ctrl output: $procmux$2361_CMP
found ctrl output: $procmux$2362_CMP
found ctrl output: $procmux$2365_CMP
found ctrl output: $procmux$2397_CMP
found ctrl output: $procmux$2398_CMP
found ctrl output: $procmux$2399_CMP
found ctrl output: $procmux$2400_CMP
found ctrl output: $procmux$2403_CMP
found ctrl output: $procmux$2405_CMP
found ctrl output: $procmux$2406_CMP
found ctrl output: $procmux$2407_CMP
found ctrl output: $procmux$2410_CMP
found ctrl output: $procmux$2411_CMP
ctrl inputs: { $auto$opt_reduce.cc:134:opt_pmux$3140 $auto$opt_reduce.cc:134:opt_pmux$3144 $auto$opt_reduce.cc:134:opt_pmux$3142 \io_jtag_tms }
ctrl outputs: { $procmux$2411_CMP $procmux$2410_CMP $procmux$2407_CMP $procmux$2406_CMP $procmux$2405_CMP $procmux$2403_CMP $procmux$2400_CMP $procmux$2399_CMP $procmux$2398_CMP $procmux$2397_CMP $procmux$2365_CMP $procmux$2362_CMP $procmux$2361_CMP \when_JtagTap_l120 \jtag_idcodeArea_ctrl_shift \jtag_idcodeArea_ctrl_capture \_zz_jtag_tap_fsm_stateNext }
transition: 4'0000 4'---0 -> 4'0001 20'00000000000001000001
transition: 4'0000 4'---1 -> 4'0000 20'00000000000001000000
transition: 4'1000 4'-000 -> 4'0001 20'00000000001000000001
transition: 4'1000 4'-001 -> 4'1001 20'00000000001000001001
transition: 4'0100 4'---0 -> 4'0100 20'00000000000010000100
transition: 4'0100 4'---1 -> 4'0101 20'00000000000010000101
transition: 4'1100 4'---0 -> 4'1101 20'00000010000000001101
transition: 4'1100 4'---1 -> 4'1111 20'00000010000000001111
transition: 4'0010 4'---0 -> 4'0011 20'01000000000000000011
transition: 4'0010 4'---1 -> 4'0000 20'01000000000000000000
transition: 4'1010 4'-0-0 -> 4'1011 20'00000000000000011011
transition: 4'1010 4'-0-1 -> 4'1100 20'00000000000000011100
transition: 4'0110 4'---0 -> 4'0110 20'00010000000000000110
transition: 4'0110 4'---1 -> 4'0111 20'00010000000000000111
transition: 4'1110 4'---0 -> 4'1011 20'00000000100000001011
transition: 4'1110 4'---1 -> 4'1111 20'00000000100000001111
transition: 4'0001 4'-000 -> 4'0001 20'10000000000000000001
transition: 4'0001 4'-001 -> 4'1001 20'10000000000000001001
transition: 4'1001 4'---0 -> 4'1010 20'00000100000000001010
transition: 4'1001 4'---1 -> 4'0010 20'00000100000000000010
transition: 4'0101 4'---0 -> 4'0110 20'00100000000000000110
transition: 4'0101 4'---1 -> 4'1000 20'00100000000000001000
transition: 4'1101 4'---0 -> 4'1101 20'00000001000000001101
transition: 4'1101 4'---1 -> 4'1110 20'00000001000000001110
transition: 4'0011 4'---0 -> 4'0100 20'00000000000100000100
transition: 4'0011 4'---1 -> 4'0101 20'00000000000100000101
transition: 4'1011 4'-0-0 -> 4'1011 20'00000000000000101011
transition: 4'1011 4'-0-1 -> 4'1100 20'00000000000000101100
transition: 4'0111 4'---0 -> 4'0100 20'00001000000000000100
transition: 4'0111 4'---1 -> 4'1000 20'00001000000000001000
transition: 4'1111 4'-000 -> 4'0001 20'00000000010000000001
transition: 4'1111 4'-001 -> 4'1001 20'00000000010000001001
Extracting FSM `\stateMachine_state' from module `\UartCtrlRx'.
found $adff cell for state register: $procdff$2901
root of input selection tree: $0\stateMachine_state[2:0]
found reset state: 3'000 (from async reset)
found ctrl input: $procmux$1172_CMP
found ctrl input: $procmux$1130_CMP
found ctrl input: $procmux$1165_CMP
found ctrl input: $procmux$1193_CMP
found ctrl input: \bitTimer_tick
found ctrl input: \sampler_value
found ctrl input: \when_UartCtrlRx_l139
found ctrl input: \when_UartCtrlRx_l125
found state code: 3'100
found ctrl input: \when_UartCtrlRx_l111
found ctrl input: \when_UartCtrlRx_l113
found state code: 3'011
found state code: 3'010
found ctrl input: \when_UartCtrlRx_l93
found state code: 3'001
found ctrl output: $procmux$1130_CMP
found ctrl output: $procmux$1165_CMP
found ctrl output: $procmux$1172_CMP
found ctrl output: $procmux$1193_CMP
ctrl inputs: { \when_UartCtrlRx_l139 \when_UartCtrlRx_l125 \when_UartCtrlRx_l113 \when_UartCtrlRx_l111 \when_UartCtrlRx_l93 \bitTimer_tick \sampler_value }
ctrl outputs: { $procmux$1193_CMP $procmux$1172_CMP $procmux$1165_CMP $procmux$1130_CMP $0\stateMachine_state[2:0] }
transition: 3'000 7'----0-- -> 3'000 7'1000000
transition: 3'000 7'----1-- -> 3'001 7'1000001
transition: 3'100 7'-----0- -> 3'100 7'0000100
transition: 3'100 7'-----10 -> 3'000 7'0000000
transition: 3'100 7'0----11 -> 3'100 7'0000100
transition: 3'100 7'1----11 -> 3'000 7'0000000
transition: 3'010 7'-----0- -> 3'010 7'0001010
transition: 3'010 7'---0-1- -> 3'010 7'0001010
transition: 3'010 7'--01-1- -> 3'011 7'0001011
transition: 3'010 7'--11-1- -> 3'100 7'0001100
transition: 3'001 7'-----0- -> 3'001 7'0010001
transition: 3'001 7'-----10 -> 3'010 7'0010010
transition: 3'001 7'-----11 -> 3'000 7'0010000
transition: 3'011 7'-----0- -> 3'011 7'0100011
transition: 3'011 7'-0---1- -> 3'000 7'0100000
transition: 3'011 7'-1---1- -> 3'100 7'0100100
Extracting FSM `\stateMachine_state' from module `\UartCtrlTx'.
found $adff cell for state register: $procdff$2885
root of input selection tree: $0\stateMachine_state[2:0]
found reset state: 3'000 (from async reset)
found ctrl input: $procmux$1049_CMP
found ctrl input: $procmux$1054_CMP
found ctrl input: $procmux$1057_CMP
found ctrl input: $procmux$1088_CMP
found ctrl input: \clockDivider_counter_willOverflow
found ctrl input: \when_UartCtrlTx_l93
found ctrl input: \io_write_valid
found state code: 3'001
found state code: 3'100
found ctrl input: \when_UartCtrlTx_l73
found ctrl input: \when_UartCtrlTx_l76
found state code: 3'011
found state code: 3'010
found ctrl input: \when_UartCtrlTx_l58
found ctrl output: $procmux$1049_CMP
found ctrl output: $procmux$1054_CMP
found ctrl output: $procmux$1057_CMP
found ctrl output: $procmux$1088_CMP
ctrl inputs: { \when_UartCtrlTx_l93 \when_UartCtrlTx_l76 \when_UartCtrlTx_l73 \when_UartCtrlTx_l58 \clockDivider_counter_willOverflow \io_write_valid }
ctrl outputs: { $procmux$1088_CMP $procmux$1057_CMP $procmux$1054_CMP $procmux$1049_CMP $0\stateMachine_state[2:0] }
transition: 3'000 6'---0-- -> 3'000 7'1000000
transition: 3'000 6'---1-- -> 3'001 7'1000001
transition: 3'100 6'----0- -> 3'100 7'0000100
transition: 3'100 6'0---1- -> 3'100 7'0000100
transition: 3'100 6'1---10 -> 3'000 7'0000000
transition: 3'100 6'1---11 -> 3'001 7'0000001
transition: 3'010 6'----0- -> 3'010 7'0010010
transition: 3'010 6'--0-1- -> 3'010 7'0010010
transition: 3'010 6'-01-1- -> 3'011 7'0010011
transition: 3'010 6'-11-1- -> 3'100 7'0010100
transition: 3'001 6'----0- -> 3'001 7'0100001
transition: 3'001 6'----1- -> 3'010 7'0100010
transition: 3'011 6'----0- -> 3'011 7'0001011
transition: 3'011 6'----1- -> 3'100 7'0001100
Extracting FSM `\CsrPlugin_interrupt_targetPrivilege' from module `\VexRiscv'.
found $dff cell for state register: $procdff$2958
root of input selection tree: $0\CsrPlugin_interrupt_targetPrivilege[1:0]
found ctrl input: \CsrPlugin_mstatus_MIE
found ctrl input: \_zz_when_CsrPlugin_l952_2
found ctrl input: \_zz_when_CsrPlugin_l952_1
found ctrl input: \_zz_when_CsrPlugin_l952
found state code: 2'11
fsm extraction failed: at least two states are required.
3.6.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\jtag_tap_fsm_state$3149' from module `\JtagBridge'.
Removing unused input signal $auto$opt_reduce.cc:134:opt_pmux$3140.
Optimizing FSM `$fsm$\stateMachine_state$3167' from module `\UartCtrlRx'.
Optimizing FSM `$fsm$\stateMachine_state$3173' from module `\UartCtrlTx'.
3.6.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
Removed 63 unused cells and 63 unused wires.
<suppressed ~66 debug messages>
3.6.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\jtag_tap_fsm_state$3149' from module `\JtagBridge'.
Removing unused output signal \_zz_jtag_tap_fsm_stateNext [0].
Removing unused output signal \_zz_jtag_tap_fsm_stateNext [1].
Removing unused output signal \_zz_jtag_tap_fsm_stateNext [2].
Removing unused output signal \_zz_jtag_tap_fsm_stateNext [3].
Removing unused output signal $procmux$2397_CMP.
Removing unused output signal $procmux$2398_CMP.
Removing unused output signal $procmux$2399_CMP.
Removing unused output signal $procmux$2400_CMP.
Removing unused output signal $procmux$2403_CMP.
Removing unused output signal $procmux$2405_CMP.
Removing unused output signal $procmux$2406_CMP.
Removing unused output signal $procmux$2407_CMP.
Removing unused output signal $procmux$2410_CMP.
Removing unused output signal $procmux$2411_CMP.
Optimizing FSM `$fsm$\stateMachine_state$3167' from module `\UartCtrlRx'.
Removing unused output signal $0\stateMachine_state[2:0] [0].
Removing unused output signal $0\stateMachine_state[2:0] [1].
Removing unused output signal $0\stateMachine_state[2:0] [2].
Optimizing FSM `$fsm$\stateMachine_state$3173' from module `\UartCtrlTx'.
Removing unused output signal $0\stateMachine_state[2:0] [0].
Removing unused output signal $0\stateMachine_state[2:0] [1].
Removing unused output signal $0\stateMachine_state[2:0] [2].
Removing unused output signal $procmux$1088_CMP.
3.6.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\jtag_tap_fsm_state$3149' from module `\JtagBridge' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
0000 -> ---------------1
1000 -> --------------1-
0100 -> -------------1--
1100 -> ------------1---
0010 -> -----------1----
1010 -> ----------1-----
0110 -> ---------1------
1110 -> --------1-------
0001 -> -------1--------
1001 -> ------1---------
0101 -> -----1----------
1101 -> ----1-----------
0011 -> ---1------------
1011 -> --1-------------
0111 -> -1--------------
1111 -> 1---------------
Recoding FSM `$fsm$\stateMachine_state$3167' from module `\UartCtrlRx' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
000 -> ----1
100 -> ---1-
010 -> --1--
001 -> -1---
011 -> 1----
Recoding FSM `$fsm$\stateMachine_state$3173' from module `\UartCtrlTx' using `auto' encoding:
mapping auto encoding to `one-hot` for this FSM.
000 -> ----1
100 -> ---1-
010 -> --1--
001 -> -1---
011 -> 1----
3.6.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
FSM `$fsm$\jtag_tap_fsm_state$3149' from module `JtagBridge':
-------------------------------------
Information on FSM $fsm$\jtag_tap_fsm_state$3149 (\jtag_tap_fsm_state):
Number of input signals: 3
Number of output signals: 6
Number of state bits: 16
Input signals:
0: \io_jtag_tms
1: $auto$opt_reduce.cc:134:opt_pmux$3142
2: $auto$opt_reduce.cc:134:opt_pmux$3144
Output signals:
0: \jtag_idcodeArea_ctrl_capture
1: \jtag_idcodeArea_ctrl_shift
2: \when_JtagTap_l120
3: $procmux$2361_CMP
4: $procmux$2362_CMP
5: $procmux$2365_CMP
State encoding:
0: 16'---------------1
1: 16'--------------1-
2: 16'-------------1--
3: 16'------------1---
4: 16'-----------1----
5: 16'----------1-----
6: 16'---------1------
7: 16'--------1-------
8: 16'-------1--------
9: 16'------1---------
10: 16'-----1----------
11: 16'----1-----------
12: 16'---1------------
13: 16'--1-------------
14: 16'-1--------------
15: 16'1---------------
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 3'--1 -> 0 6'000100
1: 0 3'--0 -> 8 6'000100
2: 1 3'000 -> 8 6'100000
3: 1 3'001 -> 9 6'100000
4: 2 3'--0 -> 2 6'001000
5: 2 3'--1 -> 10 6'001000
6: 3 3'--0 -> 11 6'000000
7: 3 3'--1 -> 15 6'000000
8: 4 3'--1 -> 0 6'000000
9: 4 3'--0 -> 12 6'000000
10: 5 3'0-1 -> 3 6'000001
11: 5 3'0-0 -> 13 6'000001
12: 6 3'--0 -> 6 6'000000
13: 6 3'--1 -> 14 6'000000
14: 7 3'--0 -> 13 6'000000
15: 7 3'--1 -> 15 6'000000
16: 8 3'000 -> 8 6'000000
17: 8 3'001 -> 9 6'000000
18: 9 3'--1 -> 4 6'000000
19: 9 3'--0 -> 5 6'000000
20: 10 3'--1 -> 1 6'000000
21: 10 3'--0 -> 6 6'000000
22: 11 3'--1 -> 7 6'000000
23: 11 3'--0 -> 11 6'000000
24: 12 3'--0 -> 2 6'010000
25: 12 3'--1 -> 10 6'010000
26: 13 3'0-1 -> 3 6'000010
27: 13 3'0-0 -> 13 6'000010
28: 14 3'--1 -> 1 6'000000
29: 14 3'--0 -> 2 6'000000
30: 15 3'000 -> 8 6'000000
31: 15 3'001 -> 9 6'000000
-------------------------------------
FSM `$fsm$\stateMachine_state$3167' from module `UartCtrlRx':
-------------------------------------
Information on FSM $fsm$\stateMachine_state$3167 (\stateMachine_state):
Number of input signals: 7
Number of output signals: 4
Number of state bits: 5
Input signals:
0: \sampler_value
1: \bitTimer_tick
2: \when_UartCtrlRx_l93
3: \when_UartCtrlRx_l111
4: \when_UartCtrlRx_l113
5: \when_UartCtrlRx_l125
6: \when_UartCtrlRx_l139
Output signals:
0: $procmux$1130_CMP
1: $procmux$1165_CMP
2: $procmux$1172_CMP
3: $procmux$1193_CMP
State encoding:
0: 5'----1 <RESET STATE>
1: 5'---1-
2: 5'--1--
3: 5'-1---
4: 5'1----
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 7'----0-- -> 0 4'1000
1: 0 7'----1-- -> 3 4'1000
2: 1 7'-----10 -> 0 4'0000
3: 1 7'1----11 -> 0 4'0000
4: 1 7'0----11 -> 1 4'0000
5: 1 7'-----0- -> 1 4'0000
6: 2 7'--11-1- -> 1 4'0001
7: 2 7'-----0- -> 2 4'0001
8: 2 7'---0-1- -> 2 4'0001
9: 2 7'--01-1- -> 4 4'0001
10: 3 7'-----11 -> 0 4'0010
11: 3 7'-----10 -> 2 4'0010
12: 3 7'-----0- -> 3 4'0010
13: 4 7'-0---1- -> 0 4'0100
14: 4 7'-1---1- -> 1 4'0100
15: 4 7'-----0- -> 4 4'0100
-------------------------------------
FSM `$fsm$\stateMachine_state$3173' from module `UartCtrlTx':
-------------------------------------
Information on FSM $fsm$\stateMachine_state$3173 (\stateMachine_state):
Number of input signals: 6
Number of output signals: 3
Number of state bits: 5
Input signals:
0: \io_write_valid
1: \clockDivider_counter_willOverflow
2: \when_UartCtrlTx_l58
3: \when_UartCtrlTx_l73
4: \when_UartCtrlTx_l76
5: \when_UartCtrlTx_l93
Output signals:
0: $procmux$1049_CMP
1: $procmux$1054_CMP
2: $procmux$1057_CMP
State encoding:
0: 5'----1 <RESET STATE>
1: 5'---1-
2: 5'--1--
3: 5'-1---
4: 5'1----
Transition Table (state_in, ctrl_in, state_out, ctrl_out):
0: 0 6'---0-- -> 0 3'000
1: 0 6'---1-- -> 3 3'000
2: 1 6'1---10 -> 0 3'000
3: 1 6'----0- -> 1 3'000
4: 1 6'0---1- -> 1 3'000
5: 1 6'1---11 -> 3 3'000
6: 2 6'-11-1- -> 1 3'010
7: 2 6'----0- -> 2 3'010
8: 2 6'--0-1- -> 2 3'010
9: 2 6'-01-1- -> 4 3'010
10: 3 6'----1- -> 2 3'100
11: 3 6'----0- -> 3 3'100
12: 4 6'----1- -> 1 3'001
13: 4 6'----0- -> 4 3'001
-------------------------------------
3.6.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\jtag_tap_fsm_state$3149' from module `\JtagBridge'.
Mapping FSM `$fsm$\stateMachine_state$3167' from module `\UartCtrlRx'.
Mapping FSM `$fsm$\stateMachine_state$3173' from module `\UartCtrlTx'.
3.7. Executing OPT pass (performing simple optimizations).
3.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
<suppressed ~16 debug messages>
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
<suppressed ~6 debug messages>
Optimizing module UartCtrlTx.
<suppressed ~8 debug messages>
Optimizing module VexRiscv.
3.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
<suppressed ~30 debug messages>
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
<suppressed ~12 debug messages>
Finding identical cells in module `\UartCtrlTx'.
<suppressed ~9 debug messages>
Finding identical cells in module `\VexRiscv'.
Removed a total of 17 cells.
3.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~307 debug messages>
3.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Performed a total of 0 changes.
3.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
3.7.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $procdff$3095 ($adff) from module Apb3Gpio (D = \io_apb_PWDATA, Q = \io_gpio_writeEnable_driver).
Adding EN signal on $procdff$3094 ($dff) from module Apb3Gpio (D = \io_apb_PWDATA, Q = \io_gpio_write_driver).
Adding EN signal on $procdff$3100 ($adff) from module Apb3UartCtrl (D = $0\bridge_misc_readOverflowError[0:0], Q = \bridge_misc_readOverflowError).
Adding EN signal on $procdff$3099 ($adff) from module Apb3UartCtrl (D = $0\bridge_misc_readError[0:0], Q = \bridge_misc_readError).
Adding EN signal on $procdff$3098 ($adff) from module Apb3UartCtrl (D = \io_apb_PWDATA [1], Q = \bridge_interruptCtrl_readIntEnable).
Adding EN signal on $procdff$3097 ($adff) from module Apb3UartCtrl (D = \io_apb_PWDATA [0], Q = \bridge_interruptCtrl_writeIntEnable).
Adding EN signal on $procdff$2911 ($dff) from module FlowCCByToggle (D = \io_input_payload_fragment, Q = \inputArea_data_fragment).
Adding EN signal on $procdff$2910 ($dff) from module FlowCCByToggle (D = \io_input_payload_last, Q = \inputArea_data_last).
Adding EN signal on $procdff$2909 ($dff) from module FlowCCByToggle (D = $logic_not$../Murax.v:6131$939_Y, Q = \inputArea_target).
Adding EN signal on $procdff$2908 ($dff) from module FlowCCByToggle (D = \inputArea_data_fragment, Q = \outputArea_flow_m2sPipe_payload_fragment).
Adding EN signal on $procdff$2907 ($dff) from module FlowCCByToggle (D = \inputArea_data_last, Q = \outputArea_flow_m2sPipe_payload_last).
Adding EN signal on $procdff$3063 ($dff) from module JtagBridge (D = \io_remote_rsp_payload_data, Q = \system_rsp_payload_data).
Adding EN signal on $procdff$3062 ($dff) from module JtagBridge (D = \io_remote_rsp_payload_error, Q = \system_rsp_payload_error).
Adding SRST signal on $procdff$3061 ($dff) from module JtagBridge (D = $procmux$2372_Y, Q = \system_rsp_valid, rval = 1'1).
Adding EN signal on $auto$ff.cc:262:slice$3450 ($sdff) from module JtagBridge (D = 1'0, Q = \system_rsp_valid).
Adding EN signal on $procdff$3060 ($dff) from module JtagBridge (D = $procmux$2349_Y, Q = \jtag_readArea_full_shifter).
Adding SRST signal on $procdff$3057 ($dff) from module JtagBridge (D = $procmux$2355_Y, Q = \jtag_idcodeArea_shifter, rval = 268443647).
Adding EN signal on $auto$ff.cc:262:slice$3457 ($sdff) from module JtagBridge (D = { \io_jtag_tdi \jtag_idcodeArea_shifter [31:1] }, Q = \jtag_idcodeArea_shifter).
Adding EN signal on $procdff$3055 ($dff) from module JtagBridge (D = $0\jtag_tap_instructionShift[3:0], Q = \jtag_tap_instructionShift).
Adding SRST signal on $procdff$3054 ($dff) from module JtagBridge (D = $procmux$2364_Y, Q = \jtag_tap_instruction, rval = 4'0001).
Adding EN signal on $auto$ff.cc:262:slice$3464 ($sdff) from module JtagBridge (D = \jtag_tap_instructionShift, Q = \jtag_tap_instruction).
Adding SRST signal on $procdff$3124 ($dff) from module Murax (D = $procmux$2854_Y, Q = \resetCtrl_systemClkResetCounter, rval = 6'000000).
Adding EN signal on $auto$ff.cc:262:slice$3466 ($sdff) from module Murax (D = $add$../Murax.v:482$34_Y, Q = \resetCtrl_systemClkResetCounter).
Adding SRST signal on $procdff$3123 ($dff) from module Murax (D = \resetCtrl_mainClkResetUnbuffered, Q = \resetCtrl_systemReset, rval = 1'1).
Adding EN signal on $procdff$3120 ($adff) from module Murax (D = $0\system_mainBusDecoder_logic_rspPending[0:0], Q = \system_mainBusDecoder_logic_rspPending).
Adding EN signal on $procdff$3119 ($adff) from module Murax (D = $0\system_cpu_dBus_cmd_rValid[0:0], Q = \system_cpu_dBus_cmd_rValid).
Adding EN signal on $procdff$3118 ($dff) from module Murax (D = \system_mainBusDecoder_logic_hits_1, Q = \system_mainBusDecoder_logic_rspSourceId).
Adding EN signal on $procdff$3117 ($dff) from module Murax (D = \system_cpu_dBus_cmd_payload_size, Q = \system_cpu_dBus_cmd_rData_size).
Adding EN signal on $procdff$3116 ($dff) from module Murax (D = \system_cpu_dBus_cmd_payload_data, Q = \system_cpu_dBus_cmd_rData_data).
Adding EN signal on $procdff$3115 ($dff) from module Murax (D = \system_cpu_dBus_cmd_payload_address, Q = \system_cpu_dBus_cmd_rData_address).
Adding EN signal on $procdff$3114 ($dff) from module Murax (D = \system_cpu_dBus_cmd_payload_wr, Q = \system_cpu_dBus_cmd_rData_wr).
Adding EN signal on $procdff$3110 ($adff) from module MuraxApb3Timer (D = \io_apb_PWDATA [1:0], Q = \interruptCtrl_1_io_masks_driver).
Adding EN signal on $procdff$3109 ($adff) from module MuraxApb3Timer (D = \io_apb_PWDATA [16], Q = \timerBBridge_clearsEnable).
Adding EN signal on $procdff$3108 ($adff) from module MuraxApb3Timer (D = \io_apb_PWDATA [1:0], Q = \timerBBridge_ticksEnable).
Adding EN signal on $procdff$3107 ($adff) from module MuraxApb3Timer (D = \io_apb_PWDATA [16], Q = \timerABridge_clearsEnable).
Adding EN signal on $procdff$3106 ($adff) from module MuraxApb3Timer (D = \io_apb_PWDATA [1:0], Q = \timerABridge_ticksEnable).
Adding EN signal on $procdff$3105 ($dff) from module MuraxApb3Timer (D = \io_apb_PWDATA [15:0], Q = \timerB_io_limit_driver).
Adding EN signal on $procdff$3104 ($dff) from module MuraxApb3Timer (D = \io_apb_PWDATA [15:0], Q = \timerA_io_limit_driver).
Adding EN signal on $procdff$3103 ($dff) from module MuraxApb3Timer (D = \io_apb_PWDATA [15:0], Q = \_zz_io_limit).
Adding EN signal on $procdff$2931 ($adff) from module MuraxMasterArbiter (D = \io_dBus_cmd_valid, Q = \rspTarget).
Adding EN signal on $procdff$2930 ($adff) from module MuraxMasterArbiter (D = $0\rspPending[0:0], Q = \rspPending).
Adding EN signal on $procdff$3085 ($dff) from module MuraxPipelinedMemoryBusRam (D = $memrd$\ram_symbol3$../Murax.v:1608$162_DATA, Q = \_zz_ramsymbol_read_3).
Adding EN signal on $procdff$3084 ($dff) from module MuraxPipelinedMemoryBusRam (D = $memrd$\ram_symbol2$../Murax.v:1607$161_DATA, Q = \_zz_ramsymbol_read_2).
Adding EN signal on $procdff$3083 ($dff) from module MuraxPipelinedMemoryBusRam (D = $memrd$\ram_symbol1$../Murax.v:1606$160_DATA, Q = \_zz_ramsymbol_read_1).
Adding EN signal on $procdff$3082 ($dff) from module MuraxPipelinedMemoryBusRam (D = $memrd$\ram_symbol0$../Murax.v:1605$159_DATA, Q = \_zz_ramsymbol_read).
Adding EN signal on $procdff$3091 ($adff) from module PipelinedMemoryBusToApbBridge (D = $0\io_pipelinedMemoryBus_cmd_rValid[0:0], Q = \io_pipelinedMemoryBus_cmd_rValid).
Adding EN signal on $procdff$3088 ($dff) from module PipelinedMemoryBusToApbBridge (D = \io_pipelinedMemoryBus_cmd_payload_data, Q = \io_pipelinedMemoryBus_cmd_rData_data).
Adding EN signal on $procdff$3087 ($dff) from module PipelinedMemoryBusToApbBridge (D = \io_pipelinedMemoryBus_cmd_payload_address, Q = \io_pipelinedMemoryBus_cmd_rData_address).
Adding EN signal on $procdff$3086 ($dff) from module PipelinedMemoryBusToApbBridge (D = \io_pipelinedMemoryBus_cmd_payload_write, Q = \io_pipelinedMemoryBus_cmd_rData_write).
Adding SRST signal on $procdff$2924 ($dff) from module Prescaler (D = $add$../Murax.v:5774$887_Y, Q = \counter, rval = 16'0000000000000000).
Adding EN signal on $procdff$2918 ($adff) from module StreamFifo (D = $0\logic_risingOccupancy[0:0], Q = \logic_risingOccupancy).
Adding EN signal on $procdff$2904 ($adff) from module StreamFifoLowLatency (D = $0\risingOccupancy[0:0], Q = \risingOccupancy).
Adding EN signal on $procdff$2903 ($dff) from module StreamFifoLowLatency (D = { \io_push_payload_inst \io_push_payload_error }, Q = \_zz_readed_error_2).
Adding EN signal on $procdff$3068 ($adff) from module SystemDebugger (D = $procmux$2424_Y, Q = \dispatcher_counter).
Adding EN signal on $procdff$3067 ($adff) from module SystemDebugger (D = $0\dispatcher_headerLoaded[0:0], Q = \dispatcher_headerLoaded).
Adding EN signal on $procdff$3066 ($adff) from module SystemDebugger (D = $0\dispatcher_dataLoaded[0:0], Q = \dispatcher_dataLoaded).
Adding EN signal on $procdff$3065 ($dff) from module SystemDebugger (D = { \io_remote_cmd_payload_fragment \dispatcher_headerShifter [7:1] }, Q = \dispatcher_headerShifter).
Adding EN signal on $procdff$3064 ($dff) from module SystemDebugger (D = { \io_remote_cmd_payload_fragment \dispatcher_dataShifter [66:1] }, Q = \dispatcher_dataShifter).
Adding EN signal on $procdff$2926 ($adff) from module Timer (D = $0\inhibitFull[0:0], Q = \inhibitFull).
Adding SRST signal on $procdff$2925 ($dff) from module Timer (D = $procmux$1387_Y, Q = \counter, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:262:slice$3552 ($sdff) from module Timer (D = $add$../Murax.v:5750$883_Y, Q = \counter).
Adding EN signal on $procdff$2900 ($adff) from module UartCtrlRx (D = $0\break_counter[6:0], Q = \break_counter).
Adding EN signal on $procdff$2897 ($adff) from module UartCtrlRx (D = \sampler_samples_1, Q = \sampler_samples_2).
Adding EN signal on $procdff$2896 ($adff) from module UartCtrlRx (D = \io_rxd_buffercc_io_dataOut, Q = \sampler_samples_1).
Adding EN signal on $procdff$2891 ($dff) from module UartCtrlRx (D = $or$../Murax.v:0$1017_Y, Q = \stateMachine_shifter).
Adding EN signal on $procdff$3046 ($adff) from module VexRiscv (D = $0\switch_Fetcher_l362[2:0], Q = \switch_Fetcher_l362).
Adding EN signal on $procdff$3044 ($adff) from module VexRiscv (D = $0\execute_LightShifterPlugin_isActive[0:0], Q = \execute_LightShifterPlugin_isActive).
Adding EN signal on $procdff$3040 ($adff) from module VexRiscv (D = $0\CsrPlugin_pipelineLiberator_pcValids_2[0:0], Q = \CsrPlugin_pipelineLiberator_pcValids_2).
Adding EN signal on $procdff$3039 ($adff) from module VexRiscv (D = $0\CsrPlugin_pipelineLiberator_pcValids_1[0:0], Q = \CsrPlugin_pipelineLiberator_pcValids_1).
Adding EN signal on $procdff$3038 ($adff) from module VexRiscv (D = $0\CsrPlugin_pipelineLiberator_pcValids_0[0:0], Q = \CsrPlugin_pipelineLiberator_pcValids_0).
Adding EN signal on $procdff$3034 ($adff) from module VexRiscv (D = \_zz_CsrPlugin_csrMapping_writeDataSignal [3], Q = \CsrPlugin_mie_MSIE).
Adding EN signal on $procdff$3033 ($adff) from module VexRiscv (D = \_zz_CsrPlugin_csrMapping_writeDataSignal [7], Q = \CsrPlugin_mie_MTIE).
Adding EN signal on $procdff$3032 ($adff) from module VexRiscv (D = \_zz_CsrPlugin_csrMapping_writeDataSignal [11], Q = \CsrPlugin_mie_MEIE).
Adding EN signal on $procdff$3020 ($adff) from module VexRiscv (D = $0\_zz_IBusSimplePlugin_injector_decodeInput_valid[0:0], Q = \_zz_IBusSimplePlugin_injector_decodeInput_valid).
Adding EN signal on $procdff$3019 ($adff) from module VexRiscv (D = $0\_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid[0:0], Q = \_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid).
Adding EN signal on $procdff$3018 ($adff) from module VexRiscv (D = $0\_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2[0:0], Q = \_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2).
Adding EN signal on $procdff$3017 ($adff) from module VexRiscv (D = $0\IBusSimplePlugin_fetchPc_inc[0:0], Q = \IBusSimplePlugin_fetchPc_inc).
Adding EN signal on $procdff$3014 ($adff) from module VexRiscv (D = { \IBusSimplePlugin_fetchPc_pc [31:2] 2'00 }, Q = \IBusSimplePlugin_fetchPc_pcReg).
Adding EN signal on $procdff$3012 ($adff) from module VexRiscv (D = $0\memory_arbitration_isValid[0:0], Q = \memory_arbitration_isValid).
Adding EN signal on $procdff$3011 ($adff) from module VexRiscv (D = $0\execute_arbitration_isValid[0:0], Q = \execute_arbitration_isValid).
Adding EN signal on $procdff$3010 ($dff) from module VexRiscv (D = $eq$../Murax.v:5476$846_Y, Q = \execute_CsrPlugin_csr_834).
Adding EN signal on $procdff$3009 ($dff) from module VexRiscv (D = $eq$../Murax.v:5473$845_Y, Q = \execute_CsrPlugin_csr_772).
Adding EN signal on $procdff$3008 ($dff) from module VexRiscv (D = $eq$../Murax.v:5470$844_Y, Q = \execute_CsrPlugin_csr_836).
Adding EN signal on $procdff$3007 ($dff) from module VexRiscv (D = $eq$../Murax.v:5467$843_Y, Q = \execute_CsrPlugin_csr_768).
Adding EN signal on $procdff$3005 ($dff) from module VexRiscv (D = { \execute_BranchPlugin_branchAdder [31:1] 1'0 }, Q = \execute_to_memory_BRANCH_CALC).
Adding EN signal on $procdff$3004 ($dff) from module VexRiscv (D = \_zz_execute_BRANCH_DO_1, Q = \execute_to_memory_BRANCH_DO).
Adding EN signal on $procdff$3002 ($dff) from module VexRiscv (D = \_zz_execute_to_memory_REGFILE_WRITE_DATA, Q = \execute_to_memory_REGFILE_WRITE_DATA).
Adding EN signal on $procdff$3000 ($dff) from module VexRiscv (D = \execute_SrcPlugin_addSub [1:0], Q = \execute_to_memory_MEMORY_ADDRESS_LOW).
Adding EN signal on $procdff$2999 ($dff) from module VexRiscv (D = \decode_DO_EBREAK, Q = \decode_to_execute_DO_EBREAK).
Adding EN signal on $procdff$2998 ($dff) from module VexRiscv (D = \_zz_decode_SRC2_6, Q = \decode_to_execute_SRC2).
Adding EN signal on $procdff$2997 ($dff) from module VexRiscv (D = \_zz_decode_SRC1_1, Q = \decode_to_execute_SRC1).
Adding EN signal on $procdff$2996 ($dff) from module VexRiscv (D = \decode_SRC2_FORCE_ZERO, Q = \decode_to_execute_SRC2_FORCE_ZERO).
Adding EN signal on $procdff$2995 ($dff) from module VexRiscv (D = \_zz_RegFilePlugin_regFile_port1, Q = \decode_to_execute_RS2).
Adding EN signal on $procdff$2994 ($dff) from module VexRiscv (D = \_zz_RegFilePlugin_regFile_port0, Q = \decode_to_execute_RS1).
Adding EN signal on $procdff$2993 ($dff) from module VexRiscv (D = \_zz_decode_BRANCH_CTRL, Q = \decode_to_execute_BRANCH_CTRL).
Adding EN signal on $procdff$2992 ($dff) from module VexRiscv (D = { \_zz__zz_decode_BRANCH_CTRL_2_4 \_zz_decode_BRANCH_CTRL_2 [21] }, Q = \decode_to_execute_SHIFT_CTRL).
Adding EN signal on $procdff$2991 ($dff) from module VexRiscv (D = { \_zz__zz_decode_BRANCH_CTRL_2_13 \_zz__zz_decode_BRANCH_CTRL_2_17 }, Q = \decode_to_execute_ALU_BITWISE_CTRL).
Adding EN signal on $procdff$2990 ($dff) from module VexRiscv (D = \decode_SRC_LESS_UNSIGNED, Q = \decode_to_execute_SRC_LESS_UNSIGNED).
Adding EN signal on $procdff$2989 ($dff) from module VexRiscv (D = { \_zz__zz_decode_BRANCH_CTRL_2_21 \_zz__zz_decode_BRANCH_CTRL_2_26 }, Q = \decode_to_execute_ALU_CTRL).
Adding EN signal on $procdff$2987 ($dff) from module VexRiscv (D = \decode_to_execute_ENV_CTRL, Q = \execute_to_memory_ENV_CTRL).
Adding EN signal on $procdff$2986 ($dff) from module VexRiscv (D = \_zz__zz_decode_BRANCH_CTRL_2_28, Q = \decode_to_execute_ENV_CTRL).
Adding EN signal on $procdff$2985 ($dff) from module VexRiscv (D = \decode_IS_CSR, Q = \decode_to_execute_IS_CSR).
Adding EN signal on $procdff$2984 ($dff) from module VexRiscv (D = \decode_to_execute_MEMORY_STORE, Q = \execute_to_memory_MEMORY_STORE).
Adding EN signal on $procdff$2983 ($dff) from module VexRiscv (D = \_zz__zz_decode_BRANCH_CTRL_2_43, Q = \decode_to_execute_MEMORY_STORE).
Adding EN signal on $procdff$2978 ($dff) from module VexRiscv (D = \decode_to_execute_REGFILE_WRITE_VALID, Q = \execute_to_memory_REGFILE_WRITE_VALID).
Adding EN signal on $procdff$2977 ($dff) from module VexRiscv (D = \decode_REGFILE_WRITE_VALID, Q = \decode_to_execute_REGFILE_WRITE_VALID).
Adding SRST signal on $auto$ff.cc:262:slice$3648 ($dffe) from module VexRiscv (D = \_zz__zz_decode_BRANCH_CTRL_2_47, Q = \decode_to_execute_REGFILE_WRITE_VALID, rval = 1'0).
Adding EN signal on $procdff$2975 ($dff) from module VexRiscv (D = \decode_to_execute_MEMORY_ENABLE, Q = \execute_to_memory_MEMORY_ENABLE).
Adding EN signal on $procdff$2974 ($dff) from module VexRiscv (D = \_zz__zz_decode_BRANCH_CTRL_2_71, Q = \decode_to_execute_MEMORY_ENABLE).
Adding EN signal on $procdff$2973 ($dff) from module VexRiscv (D = \decode_SRC_USE_SUB_LESS, Q = \decode_to_execute_SRC_USE_SUB_LESS).
Adding EN signal on $procdff$2971 ($dff) from module VexRiscv (D = \decode_CSR_WRITE_OPCODE, Q = \decode_to_execute_CSR_WRITE_OPCODE).
Adding EN signal on $procdff$2966 ($dff) from module VexRiscv (D = \decode_to_execute_INSTRUCTION, Q = \execute_to_memory_INSTRUCTION).
Adding EN signal on $procdff$2965 ($dff) from module VexRiscv (D = \_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst, Q = \decode_to_execute_INSTRUCTION).
Adding EN signal on $procdff$2962 ($dff) from module VexRiscv (D = \_zz_IBusSimplePlugin_injector_decodeInput_payload_pc, Q = \decode_to_execute_PC).
Adding EN signal on $procdff$2959 ($dff) from module VexRiscv (D = $sub$../Murax.v:5323$842_Y, Q = \execute_LightShifterPlugin_amplitudeReg).
Adding EN signal on $procdff$2958 ($dff) from module VexRiscv (D = $procmux$1598_Y, Q = \CsrPlugin_interrupt_targetPrivilege).
Adding SRST signal on $auto$ff.cc:262:slice$3662 ($dffe) from module VexRiscv (D = 2'x, Q = \CsrPlugin_interrupt_targetPrivilege, rval = 2'11).
Adding EN signal on $procdff$2957 ($dff) from module VexRiscv (D = $procmux$1606_Y, Q = \CsrPlugin_interrupt_code).
Adding SRST signal on $auto$ff.cc:262:slice$3670 ($dffe) from module VexRiscv (D = 2'x, Q = \CsrPlugin_interrupt_code [1:0], rval = 2'11).
Adding SRST signal on $auto$ff.cc:262:slice$3670 ($dffe) from module VexRiscv (D = $procmux$1602_Y [2], Q = \CsrPlugin_interrupt_code [2], rval = 1'0).
Adding SRST signal on $auto$ff.cc:262:slice$3670 ($dffe) from module VexRiscv (D = $procmux$1604_Y [3], Q = \CsrPlugin_interrupt_code [3], rval = 1'1).
Adding EN signal on $procdff$2956 ($dff) from module VexRiscv (D = \CsrPlugin_interrupt_code, Q = \CsrPlugin_mcause_exceptionCode).
Adding EN signal on $procdff$2955 ($dff) from module VexRiscv (D = 1'1, Q = \CsrPlugin_mcause_interrupt).
Adding EN signal on $procdff$2951 ($dff) from module VexRiscv (D = \_zz_IBusSimplePlugin_injector_decodeInput_payload_pc, Q = \CsrPlugin_mepc).
Adding EN signal on $procdff$2948 ($dff) from module VexRiscv (D = { $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0] [31:25] $0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0] [14:0] }, Q = { \_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst [31:25] \_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst [14:0] }).
Adding EN signal on $procdff$2946 ($dff) from module VexRiscv (D = \_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload, Q = \_zz_IBusSimplePlugin_injector_decodeInput_payload_pc).
Adding EN signal on $procdff$2945 ($dff) from module VexRiscv (D = \IBusSimplePlugin_fetchPc_pcReg, Q = \_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload).
Adding EN signal on $procdff$2942 ($dff) from module VexRiscv (D = $0\DebugPlugin_busReadDataReg[31:0], Q = \DebugPlugin_busReadDataReg).
Adding EN signal on $procdff$2938 ($adff) from module VexRiscv (D = $procmux$1416_Y, Q = \DebugPlugin_disableEbreak).
Adding EN signal on $procdff$2937 ($adff) from module VexRiscv (D = 1'1, Q = \DebugPlugin_debugUsed).
Adding EN signal on $procdff$2934 ($adff) from module VexRiscv (D = \debug_bus_cmd_payload_data [4], Q = \DebugPlugin_stepIt).
Adding EN signal on $procdff$2932 ($adff) from module VexRiscv (D = $procmux$1474_Y, Q = \DebugPlugin_resetIt).
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$3675 ($sdffce) from module VexRiscv.
Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$3675 ($sdffce) from module VexRiscv.
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$3685 ($dffe) from module VexRiscv.
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$3667 ($sdffce) from module VexRiscv.
Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$3667 ($sdffce) from module VexRiscv.
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3627 ($dffe) from module VexRiscv.
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3616 ($adffe) from module VexRiscv.
Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$3616 ($adffe) from module VexRiscv.
3.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
Removed 140 unused cells and 199 unused wires.
<suppressed ~159 debug messages>
3.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
<suppressed ~2 debug messages>
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
<suppressed ~2 debug messages>
Optimizing module Murax.
<suppressed ~2 debug messages>
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
<suppressed ~1 debug messages>
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
<suppressed ~1 debug messages>
Optimizing module Prescaler.
Optimizing module StreamFifo.
<suppressed ~1 debug messages>
Optimizing module StreamFifoLowLatency.
<suppressed ~1 debug messages>
Optimizing module SystemDebugger.
<suppressed ~2 debug messages>
Optimizing module Timer.
<suppressed ~1 debug messages>
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
<suppressed ~1 debug messages>
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
<suppressed ~21 debug messages>
3.7.9. Rerunning OPT passes. (Maybe there is more to do..)
3.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~222 debug messages>
3.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Performed a total of 0 changes.
3.7.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
<suppressed ~3 debug messages>
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
<suppressed ~6 debug messages>
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
<suppressed ~3 debug messages>
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
<suppressed ~15 debug messages>
Removed a total of 9 cells.
3.7.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 1-bit at position 0 on $auto$ff.cc:262:slice$3682 ($dffe) from module VexRiscv.
Setting constant 1-bit at position 1 on $auto$ff.cc:262:slice$3682 ($dffe) from module VexRiscv.
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3696 ($dffe) from module VexRiscv.
Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$3696 ($dffe) from module VexRiscv.
3.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
Removed 0 unused cells and 15 unused wires.
<suppressed ~4 debug messages>
3.7.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
3.7.16. Rerunning OPT passes. (Maybe there is more to do..)
3.7.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~223 debug messages>
3.7.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Performed a total of 0 changes.
3.7.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
3.7.20. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3695 ($dffe) from module VexRiscv.
Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$3695 ($dffe) from module VexRiscv.
3.7.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
3.7.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
3.7.23. Rerunning OPT passes. (Maybe there is more to do..)
3.7.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~223 debug messages>
3.7.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Performed a total of 0 changes.
3.7.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
3.7.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3656 ($dffe) from module VexRiscv.
Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$3656 ($dffe) from module VexRiscv.
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$3688 ($dffe) from module VexRiscv.
Setting constant 0-bit at position 1 on $auto$ff.cc:262:slice$3688 ($dffe) from module VexRiscv.
3.7.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
3.7.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
3.7.30. Rerunning OPT passes. (Maybe there is more to do..)
3.7.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~223 debug messages>
3.7.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Performed a total of 0 changes.
3.7.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
3.7.34. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:262:slice$3697 ($dffe) from module VexRiscv (D = $procmux$1484_Y [1:0], Q = \DebugPlugin_busReadDataReg [1:0], rval = 2'00).
3.7.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
3.7.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
3.7.37. Rerunning OPT passes. (Maybe there is more to do..)
3.7.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~224 debug messages>
3.7.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Performed a total of 0 changes.
3.7.40. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
3.7.41. Executing OPT_DFF pass (perform DFF optimizations).
3.7.42. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
3.7.43. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
3.7.44. Finished OPT passes. (There is nothing left to do.)
3.8. Executing WREDUCE pass (reducing word size of cells).
Removed top 3 bits (of 20) from port B of cell Apb3Decoder.$eq$../Murax.v:667$48 ($eq).
Removed top 2 bits (of 20) from port B of cell Apb3Decoder.$eq$../Murax.v:668$51 ($eq).
Removed top 1 bits (of 4) from port B of cell Apb3Gpio.$procmux$2526_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell Apb3Router.$procmux$2822_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell Apb3UartCtrl.$auto$opt_dff.cc:195:make_patterns_logic$3425 ($ne).
Removed cell Apb3UartCtrl.$procmux$2550 ($mux).
Removed cell Apb3UartCtrl.$procmux$2552 ($mux).
Removed cell Apb3UartCtrl.$procmux$2556 ($mux).
Removed cell Apb3UartCtrl.$procmux$2558 ($mux).
Removed top 2 bits (of 5) from port B of cell Apb3UartCtrl.$procmux$2565_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell JtagBridge.$eq$../Murax.v:2009$236 ($eq).
Removed top 3 bits (of 4) from port B of cell JtagBridge.$eq$../Murax.v:2013$237 ($eq).
Removed top 2 bits (of 4) from port B of cell JtagBridge.$eq$../Murax.v:2027$245 ($eq).
Removed top 2 bits (of 4) from port B of cell JtagBridge.$eq$../Murax.v:2034$250 ($eq).
Removed top 1 bits (of 2) from port B of cell JtagBridge.$auto$fsm_map.cc:77:implement_pattern_cache$3202 ($eq).
Removed top 2 bits (of 3) from port B of cell JtagBridge.$auto$fsm_map.cc:77:implement_pattern_cache$3237 ($eq).
Removed cell JtagBridge.$procmux$2347 ($mux).
Removed top 5 bits (of 6) from port B of cell Murax.$add$../Murax.v:482$34 ($add).
Removed cell Murax.$procmux$2844 ($mux).
Removed cell Murax.$procmux$2848 ($mux).
Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2682_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2687_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2697_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2702_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2713_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2725_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2734_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell MuraxApb3Timer.$procmux$2758_CMP0 ($eq).
Removed cell MuraxMasterArbiter.$procmux$1397 ($mux).
Removed top 1 bits (of 2) from port B of cell MuraxMasterArbiter.$procmux$1409_CMP0 ($eq).
Removed cell MuraxPipelinedMemoryBusRam.$procmux$2448 ($mux).
Removed cell MuraxPipelinedMemoryBusRam.$procmux$2451 ($mux).
Removed cell MuraxPipelinedMemoryBusRam.$procmux$2457 ($mux).
Removed cell MuraxPipelinedMemoryBusRam.$procmux$2460 ($mux).
Removed cell MuraxPipelinedMemoryBusRam.$procmux$2466 ($mux).
Removed cell MuraxPipelinedMemoryBusRam.$procmux$2469 ($mux).
Removed cell MuraxPipelinedMemoryBusRam.$procmux$2475 ($mux).
Removed cell MuraxPipelinedMemoryBusRam.$procmux$2478 ($mux).
Removed cell PipelinedMemoryBusToApbBridge.$procmux$2501 ($mux).
Removed top 12 bits (of 32) from FF cell PipelinedMemoryBusToApbBridge.$auto$ff.cc:262:slice$3516 ($dffe).
Removed top 15 bits (of 16) from port B of cell Prescaler.$add$../Murax.v:5774$887 ($add).
Removed top 3 bits (of 4) from port B of cell StreamFifo.$add$../Murax.v:5873$905 ($add).
Removed top 3 bits (of 4) from port B of cell StreamFifo.$add$../Murax.v:5896$911 ($add).
Removed cell StreamFifo.$procmux$1349 ($mux).
Removed cell StreamFifo.$procmux$1378 ($mux).
Removed cell StreamFifo.$procmux$1381 ($mux).
Removed cell StreamFifoLowLatency.$procmux$1303 ($mux).
Removed top 2 bits (of 3) from port B of cell SystemDebugger.$add$../Murax.v:1700$212 ($add).
Removed top 2 bits (of 3) from port B of cell SystemDebugger.$auto$opt_dff.cc:195:make_patterns_logic$3538 ($ne).
Removed cell SystemDebugger.$procmux$2422 ($mux).
Removed cell SystemDebugger.$procmux$2434 ($mux).
Removed cell SystemDebugger.$procmux$2438 ($mux).
Removed cell SystemDebugger.$procmux$2440 ($mux).
Removed top 15 bits (of 16) from port B of cell Timer.$add$../Murax.v:5750$883 ($add).
Removed cell Timer.$procmux$1391 ($mux).
Removed top 19 bits (of 20) from port B of cell UartCtrl.$sub$../Murax.v:6055$935 ($sub).
Removed top 1 bits (of 2) from port B of cell UartCtrlRx.$auto$fsm_map.cc:77:implement_pattern_cache$3296 ($eq).
Removed top 1 bits (of 3) from port B of cell UartCtrlRx.$auto$fsm_map.cc:77:implement_pattern_cache$3305 ($eq).
Removed top 2 bits (of 3) from port B of cell UartCtrlRx.$eq$../Murax.v:6438$984 ($eq).
Removed top 6 bits (of 7) from port B of cell UartCtrlRx.$add$../Murax.v:6464$996 ($add).
Removed top 2 bits (of 3) from port B of cell UartCtrlRx.$sub$../Murax.v:6521$1002 ($sub).
Removed top 2 bits (of 3) from port B of cell UartCtrlRx.$add$../Murax.v:6527$1003 ($add).
Removed top 7 bits (of 8) from port A of cell UartCtrlRx.$shl$../Murax.v:0$1014 ($shl).
Removed cell UartCtrlRx.$procmux$1241 ($mux).
Removed top 1 bits (of 2) from port B of cell UartCtrlRx.$auto$fsm_map.cc:77:implement_pattern_cache$3330 ($eq).
Removed top 1 bits (of 3) from port B of cell UartCtrlRx.$auto$fsm_map.cc:77:implement_pattern_cache$3348 ($eq).
Removed top 2 bits (of 3) from port B of cell UartCtrlTx.$add$../Murax.v:6662$1024 ($add).
Removed top 2 bits (of 3) from port B of cell UartCtrlTx.$eq$../Murax.v:6712$1033 ($eq).
Removed top 2 bits (of 3) from port B of cell UartCtrlTx.$add$../Murax.v:6762$1039 ($add).
Removed top 1 bits (of 2) from port B of cell UartCtrlTx.$auto$fsm_map.cc:77:implement_pattern_cache$3374 ($eq).
Removed top 1 bits (of 2) from port B of cell UartCtrlTx.$auto$fsm_map.cc:77:implement_pattern_cache$3387 ($eq).
Removed top 1 bits (of 3) from port B of cell UartCtrlTx.$auto$fsm_map.cc:77:implement_pattern_cache$3413 ($eq).
Removed top 1 bits (of 2) from port Y of cell VexRiscv.$and$../Murax.v:2979$266 ($and).
Removed top 1 bits (of 2) from port A of cell VexRiscv.$and$../Murax.v:2979$266 ($and).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$and$../Murax.v:2979$266 ($and).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$sub$../Murax.v:2980$267 ($sub).
Removed top 2 bits (of 3) from port B of cell VexRiscv.$add$../Murax.v:2983$268 ($add).
Removed top 31 bits (of 32) from mux cell VexRiscv.$ternary$../Murax.v:2998$275 ($mux).
Removed top 27 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3007$279 ($and).
Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3009$280 ($and).
Removed top 17 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3011$281 ($and).
Removed top 17 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3011$282 ($eq).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3012$284 ($eq).
Removed top 1 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3012$285 ($and).
Removed top 1 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3012$286 ($eq).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3013$287 ($eq).
Removed top 26 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3013$288 ($eq).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3014$290 ($eq).
Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3018$294 ($and).
Removed top 18 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3020$295 ($and).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3022$296 ($and).
Removed top 18 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3024$297 ($and).
Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3024$298 ($eq).
Removed top 17 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3025$299 ($and).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3025$300 ($eq).
Removed top 18 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3025$301 ($and).
Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3025$302 ($eq).
Removed top 17 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3026$303 ($eq).
Removed top 17 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3026$304 ($eq).
Removed top 17 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3031$309 ($and).
Removed top 17 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3033$310 ($and).
Removed top 11 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3035$311 ($and).
Removed top 25 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3035$312 ($eq).
Removed top 18 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3036$313 ($and).
Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3036$314 ($eq).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3036$315 ($and).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3036$316 ($eq).
Removed top 26 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3037$317 ($eq).
Removed top 26 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3037$318 ($eq).
Removed top 26 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3042$323 ($and).
Removed top 26 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3049$329 ($and).
Removed top 26 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3049$330 ($eq).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3057$336 ($eq).
Removed top 26 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3058$337 ($eq).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3062$341 ($and).
Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3064$343 ($eq).
Removed top 29 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3066$345 ($eq).
Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3067$346 ($and).
Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3070$349 ($and).
Removed top 28 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3076$356 ($and).
Removed top 26 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3078$357 ($and).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3081$359 ($eq).
Removed top 25 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3083$361 ($eq).
Removed top 18 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3084$362 ($and).
Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3084$363 ($eq).
Removed top 1 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3085$364 ($and).
Removed top 1 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3085$365 ($eq).
Removed top 27 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:3086$366 ($and).
Removed top 29 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3086$367 ($eq).
Removed top 29 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:3088$369 ($eq).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$eq$../Murax.v:3669$388 ($eq).
Removed top 29 bits (of 32) from port B of cell VexRiscv.$add$../Murax.v:4018$437 ($add).
Removed top 2 bits (of 3) from port B of cell VexRiscv.$sub$../Murax.v:4119$478 ($sub).
Removed top 17 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4426$597 ($and).
Removed top 17 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4426$598 ($eq).
Removed top 18 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4427$600 ($eq).
Removed top 27 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4428$601 ($and).
Removed top 29 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4429$603 ($and).
Removed top 29 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4429$604 ($eq).
Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4430$605 ($and).
Removed top 27 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4430$606 ($eq).
Removed top 25 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4431$607 ($and).
Removed top 25 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4431$608 ($eq).
Removed top 25 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4432$611 ($eq).
Removed top 29 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4432$613 ($eq).
Removed top 3 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4432$615 ($and).
Removed top 25 bits (of 32) from port B of cell VexRiscv.$eq$../Murax.v:4432$616 ($eq).
Removed top 19 bits (of 32) from port A of cell VexRiscv.$or$../Murax.v:5015$822 ($or).
Removed top 20 bits (of 32) from port B of cell VexRiscv.$or$../Murax.v:5015$822 ($or).
Removed top 19 bits (of 32) from port Y of cell VexRiscv.$or$../Murax.v:5015$822 ($or).
Removed top 20 bits (of 32) from port A of cell VexRiscv.$or$../Murax.v:5015$823 ($or).
Removed top 19 bits (of 32) from port A of cell VexRiscv.$or$../Murax.v:5015$824 ($or).
Removed top 2 bits (of 3) from port B of cell VexRiscv.$sub$../Murax.v:5146$835 ($sub).
Removed top 4 bits (of 5) from port B of cell VexRiscv.$sub$../Murax.v:5323$842 ($sub).
Removed top 2 bits (of 12) from port B of cell VexRiscv.$eq$../Murax.v:5467$843 ($eq).
Removed top 2 bits (of 12) from port B of cell VexRiscv.$eq$../Murax.v:5470$844 ($eq).
Removed top 2 bits (of 12) from port B of cell VexRiscv.$eq$../Murax.v:5473$845 ($eq).
Removed top 2 bits (of 12) from port B of cell VexRiscv.$eq$../Murax.v:5476$846 ($eq).
Removed cell VexRiscv.$procmux$1414 ($mux).
Removed cell VexRiscv.$procmux$1472 ($mux).
Removed cell VexRiscv.$procmux$1484 ($mux).
Removed cell VexRiscv.$procmux$1602 ($mux).
Removed cell VexRiscv.$procmux$1604 ($mux).
Removed top 7 bits (of 32) from mux cell VexRiscv.$procmux$1626 ($mux).
Removed cell VexRiscv.$procmux$1650 ($mux).
Removed top 1 bits (of 3) from port B of cell VexRiscv.$procmux$1652_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell VexRiscv.$procmux$1653_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell VexRiscv.$procmux$1654_CMP0 ($eq).
Removed cell VexRiscv.$procmux$1655 ($mux).
Removed cell VexRiscv.$procmux$1660 ($mux).
Removed cell VexRiscv.$procmux$1662 ($mux).
Removed cell VexRiscv.$procmux$1668 ($mux).
Removed cell VexRiscv.$procmux$1672 ($mux).
Removed cell VexRiscv.$procmux$1674 ($mux).
Removed cell VexRiscv.$procmux$1678 ($mux).
Removed cell VexRiscv.$procmux$1680 ($mux).
Removed cell VexRiscv.$procmux$1768 ($mux).
Removed cell VexRiscv.$procmux$1772 ($mux).
Removed cell VexRiscv.$procmux$1780 ($mux).
Removed cell VexRiscv.$procmux$1796 ($mux).
Removed cell VexRiscv.$procmux$1800 ($mux).
Removed top 5 bits (of 6) from port B of cell VexRiscv.$procmux$1846_CMP0 ($eq).
Removed top 12 bits (of 32) from mux cell VexRiscv.$procmux$1892 ($pmux).
Removed top 2 bits (of 3) from port B of cell VexRiscv.$procmux$1903_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2039_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2046_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2050_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2055_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2059_CMP0 ($eq).
Removed top 19 bits (of 32) from mux cell VexRiscv.$procmux$2071 ($mux).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2128_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2138_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$procmux$2145_CMP0 ($eq).
Removed cell VexRiscv.$procmux$2200 ($mux).
Removed cell VexRiscv.$procmux$2338 ($mux).
Removed cell VexRiscv.$procmux$2341 ($mux).
Removed top 1 bits (of 2) from port B of cell VexRiscv.$auto$opt_dff.cc:195:make_patterns_logic$3693 ($ne).
Removed top 1 bits (of 3) from port B of cell VexRiscv.$auto$opt_dff.cc:195:make_patterns_logic$3583 ($ne).
Removed top 1 bits (of 3) from port B of cell VexRiscv.$auto$opt_dff.cc:195:make_patterns_logic$3590 ($ne).
Removed top 2 bits (of 32) from FF cell VexRiscv.$procdff$2967 ($dff).
Removed top 2 bits (of 32) from FF cell VexRiscv.$auto$ff.cc:262:slice$3654 ($dffe).
Removed top 1 bits (of 2) from port Y of cell VexRiscv.$not$../Murax.v:2979$265 ($not).
Removed top 1 bits (of 2) from port A of cell VexRiscv.$not$../Murax.v:2979$265 ($not).
Removed top 1 bits (of 2) from port Y of cell VexRiscv.$sub$../Murax.v:2980$267 ($sub).
Removed top 1 bits (of 2) from port A of cell VexRiscv.$sub$../Murax.v:2980$267 ($sub).
Removed top 19 bits (of 32) from mux cell VexRiscv.$ternary$../Murax.v:4417$593 ($mux).
Removed top 19 bits (of 32) from port Y of cell VexRiscv.$and$../Murax.v:4417$591 ($and).
Removed top 19 bits (of 32) from port A of cell VexRiscv.$and$../Murax.v:4417$591 ($and).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$and$../Murax.v:4417$591 ($and).
Removed top 19 bits (of 32) from port Y of cell VexRiscv.$or$../Murax.v:4417$592 ($or).
Removed top 19 bits (of 32) from port A of cell VexRiscv.$or$../Murax.v:4417$592 ($or).
Removed top 19 bits (of 32) from port B of cell VexRiscv.$or$../Murax.v:4417$592 ($or).
Removed top 19 bits (of 32) from port Y of cell VexRiscv.$not$../Murax.v:4417$590 ($not).
Removed top 19 bits (of 32) from port A of cell VexRiscv.$not$../Murax.v:4417$590 ($not).
Removed top 19 bits (of 32) from wire VexRiscv.$and$../Murax.v:4417$591_Y.
Removed top 1 bits (of 2) from wire VexRiscv.$not$../Murax.v:2979$265_Y.
Removed top 19 bits (of 32) from wire VexRiscv.$not$../Murax.v:4417$590_Y.
Removed top 19 bits (of 32) from wire VexRiscv.CsrPlugin_csrMapping_writeDataSignal.
Removed top 19 bits (of 32) from wire VexRiscv._zz_CsrPlugin_csrMapping_readDataInit.
Removed top 20 bits (of 32) from wire VexRiscv._zz_CsrPlugin_csrMapping_readDataInit_1.
Removed top 20 bits (of 32) from wire VexRiscv._zz_CsrPlugin_csrMapping_readDataInit_2.
Removed top 19 bits (of 32) from wire VexRiscv._zz_CsrPlugin_csrMapping_writeDataSignal.
Removed top 1 bits (of 2) from wire VexRiscv._zz_IBusSimplePlugin_jump_pcLoad_payload_1.
Removed top 31 bits (of 32) from wire VexRiscv._zz_execute_SrcPlugin_addSub_4.
Removed top 2 bits (of 32) from wire VexRiscv._zz_lastStageRegFileWrite_payload_address.
Removed top 2 bits (of 32) from wire VexRiscv.execute_to_memory_INSTRUCTION.
3.9. Executing PEEPOPT pass (run peephole optimizers).
3.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
Removed 0 unused cells and 61 unused wires.
<suppressed ~12 debug messages>
3.11. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module Apb3Decoder:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module Apb3Gpio:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module Apb3Router:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module Apb3UartCtrl:
creating $macc model for $sub$../Murax.v:1075$93 ($sub).
creating $alu model for $macc $sub$../Murax.v:1075$93.
creating $alu cell for $sub$../Murax.v:1075$93: $auto$alumacc.cc:485:replace_alu$3735
created 1 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module BufferCC:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module BufferCC_1:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module BufferCC_2:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module BufferCC_3:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module FlowCCByToggle:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module InterruptCtrl:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module JtagBridge:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module Murax:
creating $macc model for $add$../Murax.v:482$34 ($add).
creating $alu model for $macc $add$../Murax.v:482$34.
creating $alu cell for $add$../Murax.v:482$34: $auto$alumacc.cc:485:replace_alu$3738
created 1 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module MuraxApb3Timer:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module MuraxMasterArbiter:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module MuraxPipelinedMemoryBusRam:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module PipelinedMemoryBusToApbBridge:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module Prescaler:
creating $macc model for $add$../Murax.v:5774$887 ($add).
creating $alu model for $macc $add$../Murax.v:5774$887.
creating $alu cell for $add$../Murax.v:5774$887: $auto$alumacc.cc:485:replace_alu$3741
created 1 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module StreamFifo:
creating $macc model for $add$../Murax.v:5873$905 ($add).
creating $macc model for $add$../Murax.v:5896$911 ($add).
creating $macc model for $sub$../Murax.v:5835$889 ($sub).
creating $macc model for $sub$../Murax.v:5911$925 ($sub).
creating $alu model for $macc $sub$../Murax.v:5911$925.
creating $alu model for $macc $sub$../Murax.v:5835$889.
creating $alu model for $macc $add$../Murax.v:5896$911.
creating $alu model for $macc $add$../Murax.v:5873$905.
creating $alu model for $eq$../Murax.v:5902$912 ($eq): merged with $sub$../Murax.v:5911$925.
creating $alu cell for $add$../Murax.v:5873$905: $auto$alumacc.cc:485:replace_alu$3744
creating $alu cell for $add$../Murax.v:5896$911: $auto$alumacc.cc:485:replace_alu$3747
creating $alu cell for $sub$../Murax.v:5835$889: $auto$alumacc.cc:485:replace_alu$3750
creating $alu cell for $sub$../Murax.v:5911$925, $eq$../Murax.v:5902$912: $auto$alumacc.cc:485:replace_alu$3753
created 4 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module StreamFifoLowLatency:
created 0 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module SystemDebugger:
creating $macc model for $add$../Murax.v:1700$212 ($add).
creating $alu model for $macc $add$../Murax.v:1700$212.
creating $alu cell for $add$../Murax.v:1700$212: $auto$alumacc.cc:485:replace_alu$3758
created 1 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module Timer:
creating $macc model for $add$../Murax.v:5750$883 ($add).
creating $alu model for $macc $add$../Murax.v:5750$883.
creating $alu cell for $add$../Murax.v:5750$883: $auto$alumacc.cc:485:replace_alu$3761
created 1 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module UartCtrl:
creating $macc model for $sub$../Murax.v:6055$935 ($sub).
creating $alu model for $macc $sub$../Murax.v:6055$935.
creating $alu cell for $sub$../Murax.v:6055$935: $auto$alumacc.cc:485:replace_alu$3764
created 1 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module UartCtrlRx:
creating $macc model for $add$../Murax.v:6464$996 ($add).
creating $macc model for $add$../Murax.v:6527$1003 ($add).
creating $macc model for $sub$../Murax.v:6521$1002 ($sub).
creating $alu model for $macc $sub$../Murax.v:6521$1002.
creating $alu model for $macc $add$../Murax.v:6527$1003.
creating $alu model for $macc $add$../Murax.v:6464$996.
creating $alu cell for $add$../Murax.v:6464$996: $auto$alumacc.cc:485:replace_alu$3767
creating $alu cell for $add$../Murax.v:6527$1003: $auto$alumacc.cc:485:replace_alu$3770
creating $alu cell for $sub$../Murax.v:6521$1002: $auto$alumacc.cc:485:replace_alu$3773
created 3 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module UartCtrlTx:
creating $macc model for $add$../Murax.v:6662$1024 ($add).
creating $macc model for $add$../Murax.v:6762$1039 ($add).
creating $alu model for $macc $add$../Murax.v:6762$1039.
creating $alu model for $macc $add$../Murax.v:6662$1024.
creating $alu cell for $add$../Murax.v:6662$1024: $auto$alumacc.cc:485:replace_alu$3776
creating $alu cell for $add$../Murax.v:6762$1039: $auto$alumacc.cc:485:replace_alu$3779
created 2 $alu and 0 $macc cells.
Extracting $alu and $macc cells in module VexRiscv:
creating $macc model for $add$../Murax.v:2983$268 ($add).
creating $macc model for $add$../Murax.v:2994$271 ($add).
creating $macc model for $add$../Murax.v:2995$272 ($add).
creating $macc model for $add$../Murax.v:4018$437 ($add).
creating $macc model for $add$../Murax.v:4809$680 ($add).
creating $macc model for $sub$../Murax.v:2980$267 ($sub).
creating $macc model for $sub$../Murax.v:4119$478 ($sub).
creating $macc model for $sub$../Murax.v:5146$835 ($sub).
creating $macc model for $sub$../Murax.v:5323$842 ($sub).
merging $macc model for $add$../Murax.v:2983$268 into $sub$../Murax.v:4119$478.
merging $macc model for $add$../Murax.v:2995$272 into $add$../Murax.v:2994$271.
creating $alu model for $macc $sub$../Murax.v:2980$267.
creating $alu model for $macc $add$../Murax.v:4809$680.
creating $alu model for $macc $add$../Murax.v:4018$437.
creating $alu model for $macc $sub$../Murax.v:5323$842.
creating $alu model for $macc $sub$../Murax.v:5146$835.
creating $macc cell for $add$../Murax.v:2994$271: $auto$alumacc.cc:365:replace_macc$3782
creating $macc cell for $sub$../Murax.v:4119$478: $auto$alumacc.cc:365:replace_macc$3783
creating $alu model for $lt$../Murax.v:5016$825 ($lt): new $alu
creating $alu cell for $lt$../Murax.v:5016$825: $auto$alumacc.cc:485:replace_alu$3785
creating $alu cell for $sub$../Murax.v:5146$835: $auto$alumacc.cc:485:replace_alu$3790
creating $alu cell for $sub$../Murax.v:5323$842: $auto$alumacc.cc:485:replace_alu$3793
creating $alu cell for $add$../Murax.v:4018$437: $auto$alumacc.cc:485:replace_alu$3796
creating $alu cell for $add$../Murax.v:4809$680: $auto$alumacc.cc:485:replace_alu$3799
creating $alu cell for $sub$../Murax.v:2980$267: $auto$alumacc.cc:485:replace_alu$3802
created 6 $alu and 2 $macc cells.
3.12. Executing SHARE pass (SAT-based resource sharing).
3.13. Executing OPT pass (performing simple optimizations).
3.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
<suppressed ~1 debug messages>
3.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
3.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~209 debug messages>
3.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Performed a total of 0 changes.
3.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
3.13.6. Executing OPT_DFF pass (perform DFF optimizations).
3.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
Removed 3 unused cells and 5 unused wires.
<suppressed ~8 debug messages>
3.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
3.13.9. Rerunning OPT passes. (Maybe there is more to do..)
3.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~209 debug messages>
3.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Performed a total of 0 changes.
3.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
3.13.13. Executing OPT_DFF pass (perform DFF optimizations).
3.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
3.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
3.13.16. Finished OPT passes. (There is nothing left to do.)
3.14. Executing MEMORY pass.
3.14.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
3.14.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.
3.14.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
Analyzing MuraxPipelinedMemoryBusRam.ram_symbol0 write port 0.
Analyzing MuraxPipelinedMemoryBusRam.ram_symbol1 write port 0.
Analyzing MuraxPipelinedMemoryBusRam.ram_symbol2 write port 0.
Analyzing MuraxPipelinedMemoryBusRam.ram_symbol3 write port 0.
Analyzing StreamFifo.logic_ram write port 0.
Analyzing VexRiscv.RegFilePlugin_regFile write port 0.
3.14.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\ram_symbol0'[0] in module `\MuraxPipelinedMemoryBusRam': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\ram_symbol1'[0] in module `\MuraxPipelinedMemoryBusRam': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\ram_symbol2'[0] in module `\MuraxPipelinedMemoryBusRam': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\ram_symbol3'[0] in module `\MuraxPipelinedMemoryBusRam': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\logic_ram'[0] in module `\StreamFifo': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\RegFilePlugin_regFile'[0] in module `\VexRiscv': merging output FF to cell.
Write port 0: non-transparent.
Checking read port `\RegFilePlugin_regFile'[1] in module `\VexRiscv': merging output FF to cell.
Write port 0: non-transparent.
3.14.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
Removed 7 unused cells and 111 unused wires.
<suppressed ~10 debug messages>
3.14.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory VexRiscv.RegFilePlugin_regFile by address:
3.14.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
3.14.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
3.14.9. Executing MEMORY_COLLECT pass (generating $mem cells).
3.15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
4. Executing OPT pass (performing simple optimizations).
4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
<suppressed ~9 debug messages>
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
<suppressed ~14 debug messages>
Optimizing module MuraxApb3Timer.
<suppressed ~10 debug messages>
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
<suppressed ~278 debug messages>
4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.
4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~207 debug messages>
4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Consolidated identical input bits for $pmux cell $procmux$1408:
Old ports: A=4'1111, B=8'00010011, Y=\_zz_io_masterBus_cmd_payload_mask
New ports: A=2'11, B=4'0001, Y=\_zz_io_masterBus_cmd_payload_mask [2:1]
New connections: { \_zz_io_masterBus_cmd_payload_mask [3] \_zz_io_masterBus_cmd_payload_mask [0] } = { \_zz_io_masterBus_cmd_payload_mask [2] 1'1 }
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Consolidated identical input bits for $mux cell $procmux$1805:
Old ports: A=4'0000, B={ \CsrPlugin_mcause_exceptionCode [3:2] 2'11 }, Y=\_zz_CsrPlugin_csrMapping_readDataInit_3 [3:0]
New ports: A=3'000, B={ \CsrPlugin_mcause_exceptionCode [3:2] 1'1 }, Y={ \_zz_CsrPlugin_csrMapping_readDataInit_3 [3:2] \_zz_CsrPlugin_csrMapping_readDataInit_3 [0] }
New connections: \_zz_CsrPlugin_csrMapping_readDataInit_3 [1] = \_zz_CsrPlugin_csrMapping_readDataInit_3 [0]
Consolidated identical input bits for $pmux cell $procmux$1892:
Old ports: A={ \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [7] \decode_to_execute_INSTRUCTION [30:25] \decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \decode_to_execute_INSTRUCTION [19:12] \decode_to_execute_INSTRUCTION [20] \decode_to_execute_INSTRUCTION [30:21] 1'0 \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31:20] }, Y=\execute_BranchPlugin_branch_src2 [19:0]
New ports: A={ \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [7] \decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \decode_to_execute_INSTRUCTION [19:12] \decode_to_execute_INSTRUCTION [20] \decode_to_execute_INSTRUCTION [24:21] 1'0 \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [31] \decode_to_execute_INSTRUCTION [24:20] }, Y={ \execute_BranchPlugin_branch_src2 [19:11] \execute_BranchPlugin_branch_src2 [4:0] }
New connections: \execute_BranchPlugin_branch_src2 [10:5] = \decode_to_execute_INSTRUCTION [30:25]
Consolidated identical input bits for $pmux cell $procmux$2127:
Old ports: A={ \memory_to_writeBack_MEMORY_READ_DATA [31:16] \_zz_writeBack_DBusSimplePlugin_rspFormated_3 [15:8] \_zz_writeBack_DBusSimplePlugin_rspFormated_1 [7:0] }, B={ \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated_1 [7:0] \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_3 [15:8] \_zz_writeBack_DBusSimplePlugin_rspFormated_1 [7:0] }, Y=\writeBack_DBusSimplePlugin_rspFormated
New ports: A={ \memory_to_writeBack_MEMORY_READ_DATA [31:16] \_zz_writeBack_DBusSimplePlugin_rspFormated_3 [15:8] }, B={ \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_2 \_zz_writeBack_DBusSimplePlugin_rspFormated_3 [15:8] }, Y=\writeBack_DBusSimplePlugin_rspFormated [31:8]
New connections: \writeBack_DBusSimplePlugin_rspFormated [7:0] = \_zz_writeBack_DBusSimplePlugin_rspFormated_1 [7:0]
Consolidated identical input bits for $pmux cell $procmux$2144:
Old ports: A=\decode_to_execute_RS2, B={ \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [15:0] \decode_to_execute_RS2 [15:0] }, Y=\dBus_cmd_payload_data
New ports: A=\decode_to_execute_RS2 [31:8], B={ \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [7:0] \decode_to_execute_RS2 [15:0] \decode_to_execute_RS2 [15:8] }, Y=\dBus_cmd_payload_data [31:8]
New connections: \dBus_cmd_payload_data [7:0] = \decode_to_execute_RS2 [7:0]
Consolidated identical input bits for $mux cell $procmux$2192:
Old ports: A=32'10000000000000000000000000100000, B={ \CsrPlugin_mepc [31:2] 2'00 }, Y=$3\CsrPlugin_jumpInterface_payload[31:0]
New ports: A=30'100000000000000000000000001000, B=\CsrPlugin_mepc [31:2], Y=$3\CsrPlugin_jumpInterface_payload[31:0] [31:2]
New connections: $3\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00
Optimizing cells in module \VexRiscv.
Consolidated identical input bits for $mux cell $procmux$2197:
Old ports: A=32'10000000000000000000000000100000, B=$3\CsrPlugin_jumpInterface_payload[31:0], Y=\CsrPlugin_jumpInterface_payload
New ports: A=30'100000000000000000000000001000, B=$3\CsrPlugin_jumpInterface_payload[31:0] [31:2], Y=\CsrPlugin_jumpInterface_payload [31:2]
New connections: \CsrPlugin_jumpInterface_payload [1:0] = 2'00
Optimizing cells in module \VexRiscv.
Consolidated identical input bits for $mux cell $ternary$../Murax.v:3997$427:
Old ports: A={ \execute_to_memory_BRANCH_CALC [31:1] 1'0 }, B=\CsrPlugin_jumpInterface_payload, Y=\IBusSimplePlugin_jump_pcLoad_payload
New ports: A=\execute_to_memory_BRANCH_CALC [31:1], B={ \CsrPlugin_jumpInterface_payload [31:2] 1'0 }, Y=\IBusSimplePlugin_jump_pcLoad_payload [31:1]
New connections: \IBusSimplePlugin_jump_pcLoad_payload [0] = 1'0
Optimizing cells in module \VexRiscv.
Consolidated identical input bits for $mux cell $procmux$2170:
Old ports: A=$add$../Murax.v:4018$437_Y, B=\IBusSimplePlugin_jump_pcLoad_payload, Y={ \IBusSimplePlugin_fetchPc_pc [31:2] $1\IBusSimplePlugin_fetchPc_pc[31:0] [1:0] }
New ports: A={ $add$../Murax.v:4018$437_Y [31:2] 1'0 }, B=\IBusSimplePlugin_jump_pcLoad_payload [31:1], Y={ \IBusSimplePlugin_fetchPc_pc [31:2] $1\IBusSimplePlugin_fetchPc_pc[31:0] [1] }
New connections: $1\IBusSimplePlugin_fetchPc_pc[31:0] [0] = 1'0
Optimizing cells in module \VexRiscv.
Performed a total of 9 changes.
4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
4.6. Executing OPT_DFF pass (perform DFF optimizations).
4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
Removed 2 unused cells and 117 unused wires.
<suppressed ~6 debug messages>
4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
<suppressed ~3 debug messages>
4.9. Rerunning OPT passes. (Maybe there is more to do..)
4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Apb3Decoder..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Gpio..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3Router..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Apb3UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \BufferCC..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_1..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_2..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \BufferCC_3..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \FlowCCByToggle..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \InterruptCtrl..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \JtagBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxApb3Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxMasterArbiter..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \MuraxPipelinedMemoryBusRam..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \PipelinedMemoryBusToApbBridge..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Prescaler..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \StreamFifo..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \StreamFifoLowLatency..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \SystemDebugger..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \Timer..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrl..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlRx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \UartCtrlTx..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \VexRiscv..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~207 debug messages>
4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Apb3Decoder.
Optimizing cells in module \Apb3Gpio.
Optimizing cells in module \Apb3Router.
Optimizing cells in module \Apb3UartCtrl.
Optimizing cells in module \BufferCC.
Optimizing cells in module \BufferCC_1.
Optimizing cells in module \BufferCC_2.
Optimizing cells in module \BufferCC_3.
Optimizing cells in module \FlowCCByToggle.
Optimizing cells in module \InterruptCtrl.
Optimizing cells in module \JtagBridge.
Optimizing cells in module \Murax.
Optimizing cells in module \MuraxApb3Timer.
Optimizing cells in module \MuraxMasterArbiter.
Optimizing cells in module \MuraxPipelinedMemoryBusRam.
Optimizing cells in module \PipelinedMemoryBusToApbBridge.
Optimizing cells in module \Prescaler.
Optimizing cells in module \StreamFifo.
Optimizing cells in module \StreamFifoLowLatency.
Optimizing cells in module \SystemDebugger.
Optimizing cells in module \Timer.
Optimizing cells in module \UartCtrl.
Optimizing cells in module \UartCtrlRx.
Optimizing cells in module \UartCtrlTx.
Optimizing cells in module \VexRiscv.
Performed a total of 0 changes.
4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Apb3Decoder'.
Finding identical cells in module `\Apb3Gpio'.
Finding identical cells in module `\Apb3Router'.
Finding identical cells in module `\Apb3UartCtrl'.
Finding identical cells in module `\BufferCC'.
Finding identical cells in module `\BufferCC_1'.
Finding identical cells in module `\BufferCC_2'.
Finding identical cells in module `\BufferCC_3'.
Finding identical cells in module `\FlowCCByToggle'.
Finding identical cells in module `\InterruptCtrl'.
Finding identical cells in module `\JtagBridge'.
Finding identical cells in module `\Murax'.
Finding identical cells in module `\MuraxApb3Timer'.
Finding identical cells in module `\MuraxMasterArbiter'.
Finding identical cells in module `\MuraxPipelinedMemoryBusRam'.
Finding identical cells in module `\PipelinedMemoryBusToApbBridge'.
Finding identical cells in module `\Prescaler'.
Finding identical cells in module `\StreamFifo'.
Finding identical cells in module `\StreamFifoLowLatency'.
Finding identical cells in module `\SystemDebugger'.
Finding identical cells in module `\Timer'.
Finding identical cells in module `\UartCtrl'.
Finding identical cells in module `\UartCtrlRx'.
Finding identical cells in module `\UartCtrlTx'.
Finding identical cells in module `\VexRiscv'.
Removed a total of 0 cells.
4.13. Executing OPT_DFF pass (perform DFF optimizations).
4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Apb3Decoder..
Finding unused cells or wires in module \Apb3Gpio..
Finding unused cells or wires in module \Apb3Router..
Finding unused cells or wires in module \Apb3UartCtrl..
Finding unused cells or wires in module \BufferCC..
Finding unused cells or wires in module \BufferCC_1..
Finding unused cells or wires in module \BufferCC_2..
Finding unused cells or wires in module \BufferCC_3..
Finding unused cells or wires in module \FlowCCByToggle..
Finding unused cells or wires in module \InterruptCtrl..
Finding unused cells or wires in module \JtagBridge..
Finding unused cells or wires in module \Murax..
Finding unused cells or wires in module \MuraxApb3Timer..
Finding unused cells or wires in module \MuraxMasterArbiter..
Finding unused cells or wires in module \MuraxPipelinedMemoryBusRam..
Finding unused cells or wires in module \PipelinedMemoryBusToApbBridge..
Finding unused cells or wires in module \Prescaler..
Finding unused cells or wires in module \StreamFifo..
Finding unused cells or wires in module \StreamFifoLowLatency..
Finding unused cells or wires in module \SystemDebugger..
Finding unused cells or wires in module \Timer..
Finding unused cells or wires in module \UartCtrl..
Finding unused cells or wires in module \UartCtrlRx..
Finding unused cells or wires in module \UartCtrlTx..
Finding unused cells or wires in module \VexRiscv..
4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
4.16. Finished OPT passes. (There is nothing left to do.)
5. Executing Verilog backend.
5.1. Executing BMUXMAP pass.
5.2. Executing DEMUXMAP pass.
Dumping module `\Apb3Decoder'.
Dumping module `\Apb3Gpio'.
Dumping module `\Apb3Router'.
Dumping module `\Apb3UartCtrl'.
Dumping module `\BufferCC'.
Dumping module `\BufferCC_1'.
Dumping module `\BufferCC_2'.
Dumping module `\BufferCC_3'.
Dumping module `\FlowCCByToggle'.
Dumping module `\InterruptCtrl'.
Dumping module `\JtagBridge'.
Dumping module `\Murax'.
Dumping module `\MuraxApb3Timer'.
Dumping module `\MuraxMasterArbiter'.
Dumping module `\MuraxPipelinedMemoryBusRam'.
Dumping module `\PipelinedMemoryBusToApbBridge'.
Dumping module `\Prescaler'.
Dumping module `\StreamFifo'.
Dumping module `\StreamFifoLowLatency'.
Dumping module `\SystemDebugger'.
Dumping module `\Timer'.
Dumping module `\UartCtrl'.
Dumping module `\UartCtrlRx'.
Dumping module `\UartCtrlTx'.
Dumping module `\VexRiscv'.
6. Executing SYNTH_ECP5 pass.
6.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_SLICE'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
6.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.
6.3. Executing HIERARCHY pass (managing design hierarchy).
6.3.1. Analyzing design hierarchy..
Top module: \Murax
Used module: \Apb3Router
Used module: \Apb3Decoder
Used module: \BufferCC_3
Used module: \JtagBridge
Used module: \FlowCCByToggle
Used module: \BufferCC_1
Used module: \SystemDebugger
Used module: \PipelinedMemoryBusToApbBridge
Used module: \VexRiscv
Used module: \StreamFifoLowLatency
Used module: \Apb3Gpio
Used module: \BufferCC_2
Used module: \MuraxMasterArbiter
Used module: \MuraxPipelinedMemoryBusRam
Used module: \MuraxApb3Timer
Used module: \InterruptCtrl
Used module: \Prescaler
Used module: \Timer
Used module: \Apb3UartCtrl
Used module: \StreamFifo
Used module: \UartCtrl
Used module: \UartCtrlRx
Used module: \BufferCC
Used module: \UartCtrlTx
6.3.2. Analyzing design hierarchy..
Top module: \Murax
Used module: \Apb3Router
Used module: \Apb3Decoder
Used module: \BufferCC_3
Used module: \JtagBridge
Used module: \FlowCCByToggle
Used module: \BufferCC_1
Used module: \SystemDebugger
Used module: \PipelinedMemoryBusToApbBridge
Used module: \VexRiscv
Used module: \StreamFifoLowLatency
Used module: \Apb3Gpio
Used module: \BufferCC_2
Used module: \MuraxMasterArbiter
Used module: \MuraxPipelinedMemoryBusRam
Used module: \MuraxApb3Timer
Used module: \InterruptCtrl
Used module: \Prescaler
Used module: \Timer
Used module: \Apb3UartCtrl
Used module: \StreamFifo
Used module: \UartCtrl
Used module: \UartCtrlRx
Used module: \BufferCC
Used module: \UartCtrlTx
Removed 0 unused modules.
6.4. Executing PROC pass (convert processes to netlists).
6.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$4173'.
Cleaned up 1 empty switch.
6.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$4273 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174 in module TRELLIS_DPR16X4.
Removed a total of 0 dead cases.
6.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 42 assignments to connections.
6.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4277'.
Set init value: \Q = 1'0
6.4.5. Executing PROC_ARST pass (detect async resets in processes).
6.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4277'.
Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$4273'.
1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232'.
1/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_EN[3:0]$4238
2/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_DATA[3:0]$4237
3/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_ADDR[3:0]$4236
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174'.
1/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_EN[3:0]$4178
2/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_DATA[3:0]$4179
3/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_ADDR[3:0]$4180
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$4173'.
6.4.7. Executing PROC_DLATCH pass (convert process syncs to latches).
6.4.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$4273'.
created $dff cell `$procdff$4301' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4218_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4220_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4223_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4221_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4217_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4219_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4222_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4216_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4224_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4225_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4226_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4227_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4228_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4229_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$4230_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_ADDR' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232'.
created $dff cell `$procdff$4302' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_DATA' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232'.
created $dff cell `$procdff$4303' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$4231_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232'.
created $dff cell `$procdff$4304' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4171_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4170_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4156_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4157_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4158_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4159_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4160_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4161_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4162_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4167_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4166_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4165_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4164_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4163_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4169_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$4168_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174'.
created $dff cell `$procdff$4305' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174'.
created $dff cell `$procdff$4306' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$4172_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174'.
created $dff cell `$procdff$4307' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$4173'.
created direct connection (no actual register cell created).
6.4.9. Executing PROC_MEMWR pass (convert process memory writes to cells).
6.4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4277'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$4273'.
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$4273'.
Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4255'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$4232'.
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$4198'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$4174'.
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$4173'.
Cleaned up 4 empty switches.
6.4.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module Apb3Decoder.
Optimizing module Apb3Gpio.
Optimizing module Apb3Router.
Optimizing module Apb3UartCtrl.
Optimizing module BufferCC.
Optimizing module BufferCC_1.
Optimizing module BufferCC_2.
Optimizing module BufferCC_3.
Optimizing module FlowCCByToggle.
Optimizing module InterruptCtrl.
Optimizing module JtagBridge.
Optimizing module Murax.
Optimizing module MuraxApb3Timer.
Optimizing module MuraxMasterArbiter.
Optimizing module MuraxPipelinedMemoryBusRam.
Optimizing module PipelinedMemoryBusToApbBridge.
Optimizing module Prescaler.
Optimizing module StreamFifo.
Optimizing module StreamFifoLowLatency.
Optimizing module SystemDebugger.
Optimizing module Timer.
Optimizing module UartCtrl.
Optimizing module UartCtrlRx.
Optimizing module UartCtrlTx.
Optimizing module VexRiscv.
6.5. Executing FLATTEN pass (flatten design).
Deleting now unused module Apb3Decoder.
Deleting now unused module Apb3Gpio.
Deleting now unused module Apb3Router.
Deleting now unused module Apb3UartCtrl.
Deleting now unused module BufferCC.
Deleting now unused module BufferCC_1.
Deleting now unused module BufferCC_2.
Deleting now unused module BufferCC_3.
Deleting now unused module FlowCCByToggle.
Deleting now unused module InterruptCtrl.
Deleting now unused module JtagBridge.
Deleting now unused module MuraxApb3Timer.
Deleting now unused module MuraxMasterArbiter.
Deleting now unused module MuraxPipelinedMemoryBusRam.
Deleting now unused module PipelinedMemoryBusToApbBridge.
Deleting now unused module Prescaler.
Deleting now unused module StreamFifo.
Deleting now unused module StreamFifoLowLatency.
Deleting now unused module SystemDebugger.
Deleting now unused module Timer.
Deleting now unused module UartCtrl.
Deleting now unused module UartCtrlRx.
Deleting now unused module UartCtrlTx.
Deleting now unused module VexRiscv.
<suppressed ~26 debug messages>
6.6. Executing TRIBUF pass.
6.7. Executing DEMINOUT pass (demote inout ports to input or output).
6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
<suppressed ~29 debug messages>
6.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
Removed 8 unused cells and 28 unused wires.
<suppressed ~14 debug messages>
6.10. Executing CHECK pass (checking for obvious problems).
Checking module Murax...
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [31] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [30] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [29] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [28] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [27] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [26] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [25] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [24] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [23] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [22] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [21] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [20] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [19] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [18] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [17] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [16] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [15] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [14] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [13] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [12] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [11] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [10] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [9] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [8] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [7] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [6] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [5] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [4] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [3] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [2] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [1] is used but has no driver.
Warning: Wire Murax.\system_gpioACtrl.io_gpio_read_buffercc.io_dataIn [0] is used but has no driver.
Found and reported 32 problems.
6.11. Executing OPT pass (performing simple optimizations).
6.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
<suppressed ~6 debug messages>
6.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
<suppressed ~24 debug messages>
Removed a total of 8 cells.
6.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~186 debug messages>
6.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Murax.
Optimizing cells in module \Murax.
Performed a total of 2 changes.
6.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.
6.11.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $flatten\jtagBridge_1.$auto$ff.cc:262:slice$3449 ($dffe) from module Murax.
Setting constant 0-bit at position 0 on $flatten\system_cpu.\IBusSimplePlugin_rspJoin_rspBuffer_c.$auto$ff.cc:262:slice$3525 ($dffe) from module Murax.
6.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
Removed 2 unused cells and 28 unused wires.
<suppressed ~20 debug messages>
6.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
<suppressed ~3 debug messages>
6.11.9. Rerunning OPT passes. (Maybe there is more to do..)
6.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~184 debug messages>
6.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Murax.
Performed a total of 0 changes.
6.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
Removed a total of 0 cells.
6.11.13. Executing OPT_DFF pass (perform DFF optimizations).
6.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>
6.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
6.11.16. Rerunning OPT passes. (Maybe there is more to do..)
6.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~184 debug messages>
6.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Murax.
Performed a total of 0 changes.
6.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
Removed a total of 0 cells.
6.11.20. Executing OPT_DFF pass (perform DFF optimizations).
6.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
6.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
6.11.23. Finished OPT passes. (There is nothing left to do.)
6.12. Executing FSM pass (extract and optimize FSM).
6.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Warning: Regarding the user-specified fsm_encoding attribute on Murax.system_cpu.CsrPlugin_interrupt_targetPrivilege:
Users of state reg look like FSM recoding might result in larger circuit.
Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Not marking Murax.system_gpioACtrl.io_gpio_read_buffercc.buffers_0 as FSM state register:
Users of register don't seem to benefit from recoding.
6.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\system_cpu.CsrPlugin_interrupt_targetPrivilege' from module `\Murax'.
root of input selection tree: 2'mm
fsm extraction failed: incomplete input selection tree root.
6.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
6.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
6.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
6.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
6.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
6.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
6.13. Executing OPT pass (performing simple optimizations).
6.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
6.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
Removed a total of 0 cells.
6.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~184 debug messages>
6.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Murax.
Performed a total of 0 changes.
6.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
Removed a total of 0 cells.
6.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\system_cpu.$procdff$2954 ($dff) from module Murax (D = \system_cpu.CsrPlugin_csrMapping_writeDataSignal [3], Q = \system_cpu.CsrPlugin_mip_MSIP, rval = 1'0).
Adding SRST signal on $flatten\system_apbBridge.$auto$ff.cc:262:slice$3516 ($dffe) from module Murax (D = \system_cpu_dBus_cmd_rData_address [1:0], Q = \system_apbBridge.io_pipelinedMemoryBus_cmd_rData_address [1:0], rval = 2'00).
Adding SRST signal on $flatten\jtagBridge_1.$auto$ff.cc:262:slice$3452 ($dffe) from module Murax (D = \jtagBridge_1.jtag_readArea_full_shifter [2], Q = \jtagBridge_1.jtag_readArea_full_shifter [1], rval = 1'0).
6.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
Removed 2 unused cells and 2 unused wires.
<suppressed ~3 debug messages>
6.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
6.13.9. Rerunning OPT passes. (Maybe there is more to do..)
6.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~183 debug messages>
6.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Murax.
Performed a total of 0 changes.
6.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
Removed a total of 0 cells.
6.13.13. Executing OPT_DFF pass (perform DFF optimizations).
6.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
6.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
6.13.16. Finished OPT passes. (There is nothing left to do.)
6.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 2 bits (of 6) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3012$284 ($eq).
Removed top 1 bits (of 5) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3013$287 ($eq).
Removed top 1 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3013$288 ($eq).
Removed top 1 bits (of 2) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3025$300 ($eq).
Removed top 3 bits (of 5) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3035$312 ($eq).
Removed top 1 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3037$317 ($eq).
Removed top 1 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3058$337 ($eq).
Removed top 1 bits (of 2) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3066$345 ($eq).
Removed top 1 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3081$359 ($eq).
Removed top 1 bits (of 2) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3086$367 ($eq).
Removed top 1 bits (of 2) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:3088$369 ($eq).
Removed top 1 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:4427$600 ($eq).
Removed top 1 bits (of 2) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:4430$606 ($eq).
Removed top 2 bits (of 3) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:4432$613 ($eq).
Removed top 3 bits (of 5) from port B of cell Murax.$flatten\system_cpu.$eq$../Murax.v:4432$616 ($eq).
Removed top 3 bits (of 8) from port B of cell Murax.$flatten\io_apb_decoder.$eq$../Murax.v:667$48 ($eq).
Removed top 2 bits (of 8) from port B of cell Murax.$flatten\io_apb_decoder.$eq$../Murax.v:668$51 ($eq).
Removed top 1 bits (of 2) from wire Murax.$flatten\system_cpu.$auto$wreduce.cc:454:run$3724.
Removed top 19 bits (of 32) from wire Murax.$flatten\system_cpu.$auto$wreduce.cc:454:run$3725.
Removed top 19 bits (of 32) from wire Murax.$flatten\system_cpu.$ternary$../Murax.v:4417$593_Y.
Removed top 15 bits (of 32) from wire Murax.system_timer_io_apb_PRDATA.
Removed top 3 bits (of 32) from wire Murax.system_uartCtrl_io_apb_PRDATA.
6.15. Executing PEEPOPT pass (run peephole optimizers).
6.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
Removed 0 unused cells and 5 unused wires.
<suppressed ~1 debug messages>
6.17. Executing SHARE pass (SAT-based resource sharing).
6.18. Executing TECHMAP pass (map to technology primitives).
6.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
6.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~6 debug messages>
6.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
6.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
6.21. Executing TECHMAP pass (map to technology primitives).
6.21.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/mul2dsp.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.
6.21.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.
6.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>
6.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module Murax:
created 0 $alu and 0 $macc cells.
6.23. Executing OPT pass (performing simple optimizations).
6.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
6.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
Removed a total of 0 cells.
6.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~183 debug messages>
6.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Murax.
Performed a total of 0 changes.
6.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
Removed a total of 0 cells.
6.23.6. Executing OPT_DFF pass (perform DFF optimizations).
6.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
6.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
6.23.9. Finished OPT passes. (There is nothing left to do.)
6.24. Executing MEMORY pass.
6.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
6.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.
6.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
6.24.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
6.24.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
6.24.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory Murax.system_cpu.RegFilePlugin_regFile by address:
6.24.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
6.24.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
6.24.9. Executing MEMORY_COLLECT pass (generating $mem cells).
6.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
6.26. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
Processing Murax.system_cpu.RegFilePlugin_regFile:
Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min bits 2048' not met.
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=480 dwaste=4 bwaste=17408 waste=17408 efficiency=5
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=992 dwaste=4 bwaste=17984 waste=17984 efficiency=2
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2016 dwaste=4 bwaste=18272 waste=18272 efficiency=1
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=4064 dwaste=0 bwaste=16256 waste=16256 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=8160 dwaste=0 bwaste=16320 waste=16320 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=16352 dwaste=0 bwaste=16352 waste=16352 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
No acceptable bram resources found.
Processing Murax.system_ram.ram_symbol0:
Properties: ports=2 bits=16384 rports=1 wports=1 dbits=8 abits=11 words=2048
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=14336 efficiency=22
Storing for later selection.
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 1):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=10240 efficiency=44
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 2):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=2048 efficiency=88
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 3):
Shuffle bit order to accommodate enable buckets of size 4..
Results of bit order shuffling: 0 1 2 3 4 5 6 7
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=8192 efficiency=50
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 4):
Shuffle bit order to accommodate enable buckets of size 2..
Results of bit order shuffling: 0 1 2 3 4 5 6 7
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=12288 efficiency=25
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 5):
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=14336 efficiency=12
Storing for later selection.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
Selecting best of 6 rules:
Efficiency for rule 4.5: efficiency=12, cells=8, acells=1
Efficiency for rule 4.4: efficiency=25, cells=4, acells=1
Efficiency for rule 4.3: efficiency=50, cells=2, acells=1
Efficiency for rule 4.2: efficiency=88, cells=1, acells=1
Efficiency for rule 4.1: efficiency=44, cells=2, acells=2
Efficiency for rule 1.1: efficiency=22, cells=4, acells=4
Selected rule 4.2 with efficiency 88.
Mapping to bram type $__ECP5_DP16KD (variant 2):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: system_ram.ram_symbol0.0.0.0
Processing Murax.system_ram.ram_symbol1:
Properties: ports=2 bits=16384 rports=1 wports=1 dbits=8 abits=11 words=2048
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=14336 efficiency=22
Storing for later selection.
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 1):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=10240 efficiency=44
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 2):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=2048 efficiency=88
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 3):
Shuffle bit order to accommodate enable buckets of size 4..
Results of bit order shuffling: 0 1 2 3 4 5 6 7
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=8192 efficiency=50
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 4):
Shuffle bit order to accommodate enable buckets of size 2..
Results of bit order shuffling: 0 1 2 3 4 5 6 7
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=12288 efficiency=25
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 5):
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=14336 efficiency=12
Storing for later selection.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
Selecting best of 6 rules:
Efficiency for rule 4.5: efficiency=12, cells=8, acells=1
Efficiency for rule 4.4: efficiency=25, cells=4, acells=1
Efficiency for rule 4.3: efficiency=50, cells=2, acells=1
Efficiency for rule 4.2: efficiency=88, cells=1, acells=1
Efficiency for rule 4.1: efficiency=44, cells=2, acells=2
Efficiency for rule 1.1: efficiency=22, cells=4, acells=4
Selected rule 4.2 with efficiency 88.
Mapping to bram type $__ECP5_DP16KD (variant 2):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: system_ram.ram_symbol1.0.0.0
Processing Murax.system_ram.ram_symbol2:
Properties: ports=2 bits=16384 rports=1 wports=1 dbits=8 abits=11 words=2048
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=14336 efficiency=22
Storing for later selection.
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 1):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=10240 efficiency=44
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 2):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=2048 efficiency=88
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 3):
Shuffle bit order to accommodate enable buckets of size 4..
Results of bit order shuffling: 0 1 2 3 4 5 6 7
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=8192 efficiency=50
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 4):
Shuffle bit order to accommodate enable buckets of size 2..
Results of bit order shuffling: 0 1 2 3 4 5 6 7
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=12288 efficiency=25
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 5):
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=14336 efficiency=12
Storing for later selection.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
Selecting best of 6 rules:
Efficiency for rule 4.5: efficiency=12, cells=8, acells=1
Efficiency for rule 4.4: efficiency=25, cells=4, acells=1
Efficiency for rule 4.3: efficiency=50, cells=2, acells=1
Efficiency for rule 4.2: efficiency=88, cells=1, acells=1
Efficiency for rule 4.1: efficiency=44, cells=2, acells=2
Efficiency for rule 1.1: efficiency=22, cells=4, acells=4
Selected rule 4.2 with efficiency 88.
Mapping to bram type $__ECP5_DP16KD (variant 2):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: system_ram.ram_symbol2.0.0.0
Processing Murax.system_ram.ram_symbol3:
Properties: ports=2 bits=16384 rports=1 wports=1 dbits=8 abits=11 words=2048
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=14336 efficiency=22
Storing for later selection.
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 1):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=10240 efficiency=44
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 2):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=2048 efficiency=88
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 3):
Shuffle bit order to accommodate enable buckets of size 4..
Results of bit order shuffling: 0 1 2 3 4 5 6 7
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=8192 efficiency=50
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 4):
Shuffle bit order to accommodate enable buckets of size 2..
Results of bit order shuffling: 0 1 2 3 4 5 6 7
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=12288 efficiency=25
Storing for later selection.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
Mapping to bram type $__ECP5_DP16KD (variant 5):
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Updated properties: dups=1 waste=14336 efficiency=12
Storing for later selection.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2048 dwaste=0 bwaste=8192 waste=8192 efficiency=50
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=6144 dwaste=0 bwaste=12288 waste=12288 efficiency=25
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=14336 dwaste=0 bwaste=14336 waste=14336 efficiency=12
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
Selecting best of 6 rules:
Efficiency for rule 4.5: efficiency=12, cells=8, acells=1
Efficiency for rule 4.4: efficiency=25, cells=4, acells=1
Efficiency for rule 4.3: efficiency=50, cells=2, acells=1
Efficiency for rule 4.2: efficiency=88, cells=1, acells=1
Efficiency for rule 4.1: efficiency=44, cells=2, acells=2
Efficiency for rule 1.1: efficiency=22, cells=4, acells=4
Selected rule 4.2 with efficiency 88.
Mapping to bram type $__ECP5_DP16KD (variant 2):
Shuffle bit order to accommodate enable buckets of size 9..
Results of bit order shuffling: 0 1 2 3 4 5 6 7 -1
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.1.
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: system_ram.ram_symbol3.0.0.0
Processing Murax.system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram:
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
No acceptable bram resources found.
Processing Murax.system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram:
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
Bram geometry: abits=9 dbits=36 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_PDPW16KD: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0
Rule #3 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min efficiency 5' not met.
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
Rule #4 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min efficiency 5' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_ramstyle="block_ram" ...' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
Bram geometry: abits=10 dbits=18 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
Bram geometry: abits=11 dbits=9 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
Bram geometry: abits=12 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
Bram geometry: abits=13 dbits=2 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'max wports 0' not met.
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
Bram geometry: abits=14 dbits=1 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__ECP5_DP16KD: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0
Rule #6 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'max wports 0' not met.
No acceptable bram resources found.
6.27. Executing TECHMAP pass (map to technology primitives).
6.27.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD'.
Successfully finished Verilog frontend.
6.27.2. Continuing TECHMAP pass.
Using template $paramod$3be384f458d0537a27afbd79f48b29b3c25e4b9a\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
No more expansions possible.
<suppressed ~29 debug messages>
6.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
Processing Murax.system_cpu.RegFilePlugin_regFile:
Properties: ports=3 bits=1024 rports=2 wports=1 dbits=32 abits=5 words=32
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
Bram geometry: abits=4 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.1.
Read port #1 is in clock domain \io_mainClk.
Failed to map read port #1.
Growing more read ports by duplicating bram cells.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.1.
Read port #1 is in clock domain \io_mainClk.
Mapped to bram port A1.2.
Updated properties: dups=2 waste=0 efficiency=50
Extracted data FF from read port 0 of Murax.system_cpu.RegFilePlugin_regFile: $\system_cpu.RegFilePlugin_regFile$rdreg[0]
Extracted data FF from read port 1 of Murax.system_cpu.RegFilePlugin_regFile: $\system_cpu.RegFilePlugin_regFile$rdreg[1]
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: system_cpu.RegFilePlugin_regFile.0.0.0
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 1>: system_cpu.RegFilePlugin_regFile.0.0.1
Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 0>: system_cpu.RegFilePlugin_regFile.0.1.0
Creating $__TRELLIS_DPR16X4 cell at grid position <0 1 1>: system_cpu.RegFilePlugin_regFile.0.1.1
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: system_cpu.RegFilePlugin_regFile.1.0.0
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 1>: system_cpu.RegFilePlugin_regFile.1.0.1
Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 0>: system_cpu.RegFilePlugin_regFile.1.1.0
Creating $__TRELLIS_DPR16X4 cell at grid position <1 1 1>: system_cpu.RegFilePlugin_regFile.1.1.1
Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 0>: system_cpu.RegFilePlugin_regFile.2.0.0
Creating $__TRELLIS_DPR16X4 cell at grid position <2 0 1>: system_cpu.RegFilePlugin_regFile.2.0.1
Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 0>: system_cpu.RegFilePlugin_regFile.2.1.0
Creating $__TRELLIS_DPR16X4 cell at grid position <2 1 1>: system_cpu.RegFilePlugin_regFile.2.1.1
Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 0>: system_cpu.RegFilePlugin_regFile.3.0.0
Creating $__TRELLIS_DPR16X4 cell at grid position <3 0 1>: system_cpu.RegFilePlugin_regFile.3.0.1
Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 0>: system_cpu.RegFilePlugin_regFile.3.1.0
Creating $__TRELLIS_DPR16X4 cell at grid position <3 1 1>: system_cpu.RegFilePlugin_regFile.3.1.1
Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 0>: system_cpu.RegFilePlugin_regFile.4.0.0
Creating $__TRELLIS_DPR16X4 cell at grid position <4 0 1>: system_cpu.RegFilePlugin_regFile.4.0.1
Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 0>: system_cpu.RegFilePlugin_regFile.4.1.0
Creating $__TRELLIS_DPR16X4 cell at grid position <4 1 1>: system_cpu.RegFilePlugin_regFile.4.1.1
Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 0>: system_cpu.RegFilePlugin_regFile.5.0.0
Creating $__TRELLIS_DPR16X4 cell at grid position <5 0 1>: system_cpu.RegFilePlugin_regFile.5.0.1
Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 0>: system_cpu.RegFilePlugin_regFile.5.1.0
Creating $__TRELLIS_DPR16X4 cell at grid position <5 1 1>: system_cpu.RegFilePlugin_regFile.5.1.1
Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 0>: system_cpu.RegFilePlugin_regFile.6.0.0
Creating $__TRELLIS_DPR16X4 cell at grid position <6 0 1>: system_cpu.RegFilePlugin_regFile.6.0.1
Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 0>: system_cpu.RegFilePlugin_regFile.6.1.0
Creating $__TRELLIS_DPR16X4 cell at grid position <6 1 1>: system_cpu.RegFilePlugin_regFile.6.1.1
Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 0>: system_cpu.RegFilePlugin_regFile.7.0.0
Creating $__TRELLIS_DPR16X4 cell at grid position <7 0 1>: system_cpu.RegFilePlugin_regFile.7.0.1
Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 0>: system_cpu.RegFilePlugin_regFile.7.1.0
Creating $__TRELLIS_DPR16X4 cell at grid position <7 1 1>: system_cpu.RegFilePlugin_regFile.7.1.1
Processing Murax.system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram:
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
Bram geometry: abits=4 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.1.
Updated properties: dups=1 waste=0 efficiency=100
Extracted data FF from read port 0 of Murax.system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram: $\system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram$rdreg[0]
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.0.0.0
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ram.1.0.0
Processing Murax.system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram:
Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16
Checking rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1):
Bram geometry: abits=4 dbits=4 wports=0 rports=0
Estimated number of duplicates for more read ports: dups=1
Metrics for $__TRELLIS_DPR16X4: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
Rule #1 for bram type $__TRELLIS_DPR16X4 (variant 1) accepted.
Mapping to bram type $__TRELLIS_DPR16X4 (variant 1):
Write port #0 is in clock domain \io_mainClk.
Mapped to bram port B1.
Read port #0 is in clock domain \io_mainClk.
Mapped to bram port A1.1.
Updated properties: dups=1 waste=0 efficiency=100
Extracted data FF from read port 0 of Murax.system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram: $\system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram$rdreg[0]
Creating $__TRELLIS_DPR16X4 cell at grid position <0 0 0>: system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram.0.0.0
Creating $__TRELLIS_DPR16X4 cell at grid position <1 0 0>: system_uartCtrl.uartCtrl_1_io_read_queueWithOccupancy.logic_ram.1.0.0
6.29. Executing TECHMAP pass (map to technology primitives).
6.29.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4'.
Successfully finished Verilog frontend.
6.29.2. Continuing TECHMAP pass.
Using template $paramod\$__TRELLIS_DPR16X4\CLKPOL2=32'00000000000000000000000000000001 for cells of type $__TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~50 debug messages>
6.30. Executing OPT pass (performing simple optimizations).
6.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
<suppressed ~235 debug messages>
6.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
<suppressed ~186 debug messages>
Removed a total of 62 cells.
6.30.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\jtagBridge_1.$auto$ff.cc:262:slice$3461 ($dffe) from module Murax (D = { \io_jtag_tdi \jtagBridge_1.jtag_tap_instructionShift [3:1] }, Q = \jtagBridge_1.jtag_tap_instructionShift, rval = 4'0001).
Setting constant 1-bit at position 0 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 1 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 2 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 3 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 4 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 5 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 6 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 7 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 8 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 9 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 10 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 11 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 12 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 13 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 14 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 15 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 16 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 17 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 18 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 19 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 20 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 21 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 22 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 23 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 24 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 25 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 26 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 27 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 28 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 29 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 30 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
Setting constant 1-bit at position 31 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2912 ($dff) from module Murax.
6.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
Removed 4 unused cells and 392 unused wires.
<suppressed ~5 debug messages>
6.30.5. Rerunning OPT passes. (Removed registers in this run.)
6.30.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
6.30.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
Removed a total of 0 cells.
6.30.8. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 1-bit at position 0 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 1 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 2 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 3 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 4 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 5 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 6 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 7 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 8 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 9 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 10 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 11 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 12 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 13 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 14 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 15 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 16 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 17 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 18 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 19 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 20 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 21 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 22 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 23 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 24 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 25 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 26 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 27 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 28 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 29 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 30 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
Setting constant 1-bit at position 31 on $flatten\system_gpioACtrl.\io_gpio_read_buffercc.$procdff$2913 ($dff) from module Murax.
6.30.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
6.30.10. Rerunning OPT passes. (Removed registers in this run.)
6.30.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
<suppressed ~1 debug messages>
6.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
Removed a total of 0 cells.
6.30.13. Executing OPT_DFF pass (perform DFF optimizations).
6.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
Removed 1 unused cells and 1 unused wires.
<suppressed ~2 debug messages>
6.30.15. Finished fast OPT passes.
6.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
6.32. Executing OPT pass (performing simple optimizations).
6.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
6.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
Removed a total of 0 cells.
6.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Murax..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~163 debug messages>
6.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \Murax.
Performed a total of 0 changes.
6.32.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
Removed a total of 0 cells.
6.32.6. Executing OPT_DFF pass (perform DFF optimizations).
6.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
6.32.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
6.32.9. Finished OPT passes. (There is nothing left to do.)
6.33. Executing TECHMAP pass (map to technology primitives).
6.33.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
6.33.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.
6.33.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $adff.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $adffe.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $reduce_and.
Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\_90_alu for cells of type $alu.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$d8458b3c47920e79a4e96c2be935e3ae586a4c76\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $not.
Using template $paramod$32e7c4d6f92ff4337599ece53082d2e88a82a9f2\_90_pmux for cells of type $pmux.
Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$92adee9538f2381d8e5006822c900eb986d754e8\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux.
Using template $paramod$103b4016182df467cceab67bcf3e18e6361ec0fd\_80_ecp5_alu for cells of type $alu.
Using template $paramod$b8c0a997bce700f23568a5ada79cc6781d1f5ca0\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $or.
Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux.
Using template $paramod$constmap:1b6115d36d46c0296d0024e3e3623593810ba834$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Analyzing pattern of constant bits for this cell:
Creating constmapped module `$paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr'.
6.33.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
<suppressed ~803 debug messages>
6.33.39. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr.
<suppressed ~35 debug messages>
Removed 0 unused cells and 8 unused wires.
Using template $paramod$constmap:f062eb9b59fe112e8a37f22ba8867a126e0dc845$paramod$3b3a66a7766bf28794ddcd35314b025da1fe57c8\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$5cf79906c00cc8f7a6c2d9b89d3bc7b92e33c859\_90_pmux for cells of type $pmux.
Using template $paramod$5982968ccccb55277ed45bb827df8f5e35c0a049\_90_pmux for cells of type $pmux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using template $paramod$constmap:6e3026a439ed4a6e7983ca0e910890cc59b2f7b2$paramod$f244f79b7bd028e965812e6cbb9720dcefdc7dda\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using extmapper maccmap for cells of type $macc.
add \system_cpu.decode_to_execute_SRC1 (32 bits, signed)
add { 1'0 \system_cpu.decode_to_execute_SRC_USE_SUB_LESS } (2 bits, signed)
add \system_cpu._zz_execute_SrcPlugin_addSub_3 (32 bits, signed)
packed 1 (1) bits / 1 words into adder tree
add \system_cpu.IBusSimplePlugin_pending_value (3 bits, unsigned)
sub \system_cpu.IBusSimplePlugin_pending_dec (1 bits, unsigned)
add bits \system_cpu.IBusSimplePlugin_cmd_fire (1 bits)
packed 1 (1) bits / 1 words into adder tree
Using template $paramod$dc04b7d98e503a7bab16fce2df70e6e2c5ca34d6\_80_ecp5_alu for cells of type $alu.
Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ecp5_alu for cells of type $alu.
Using template $paramod$e978c189388a43a00e4e725f292dc6d7f2ae25b3\_90_pmux for cells of type $pmux.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu.
No more expansions possible.
<suppressed ~2644 debug messages>
6.34. Executing OPT pass (performing simple optimizations).
6.34.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
<suppressed ~1597 debug messages>
6.34.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Murax'.
<suppressed ~1521 debug messages>
Removed a total of 507 cells.
6.34.3. Executing OPT_DFF pass (perform DFF optimizations).
6.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
Removed 574 unused cells and 2881 unused wires.
<suppressed ~584 debug messages>
6.34.5. Finished fast OPT passes.
6.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
6.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
6.37. Executing TECHMAP pass (map to technology primitives).
6.37.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.
6.37.2. Continuing TECHMAP pass.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_.
Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template $paramod\$_DFF_N_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_N_.
No more expansions possible.
<suppressed ~1478 debug messages>
6.38. Executing OPT_EXPR pass (perform const folding).
Optimizing module Murax.
<suppressed ~84 debug messages>
6.39. Executing SIMPLEMAP pass (map simple cells to gate primitives).
6.40. Executing ECP5_GSR pass (implement FF init values).
Handling GSR in Murax.
6.41. Executing ATTRMVCP pass (move or copy attributes).
6.42. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Murax..
Removed 0 unused cells and 6768 unused wires.
<suppressed ~1 debug messages>
6.43. Executing TECHMAP pass (map to technology primitives).
6.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.
6.43.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>
6.44. Executing ABC pass (technology mapping using ABC).
6.44.1. Extracting gate netlist of module `\Murax' to `<abc-temp-dir>/input.blif'..
Extracted 3605 gates and 5015 wires to a netlist network with 1408 inputs and 833 outputs.
6.44.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
ABC: + strash
ABC: + ifraig
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + strash
ABC: + dch -f
ABC: + if
ABC: + mfs2
ABC: + dress
ABC: Total number of equiv classes = 1275.
ABC: Participating nodes from both networks = 2770.
ABC: Participating nodes from the first network = 1284. ( 86.00 % of nodes)
ABC: Participating nodes from the second network = 1486. ( 99.53 % of nodes)
ABC: Node pairs (any polarity) = 1283. ( 85.93 % of names can be moved)
ABC: Node pairs (same polarity) = 958. ( 64.17 % of names can be moved)
ABC: Total runtime = 0.08 sec
ABC: + write_blif <abc-temp-dir>/output.blif
6.44.1.2. Re-integrating ABC results.
ABC RESULTS: $lut cells: 1491
ABC RESULTS: internal signals: 2774
ABC RESULTS: input signals: 1408
ABC RESULTS: output signals: 833
Removing temp directory.
Removed 0 unused cells and 3191 unused wires.
6.45. Executing TECHMAP pass (map to technology primitives).
6.45.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
6.45.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$04b674496422df8889c01c3744b94097628ccfbc\$lut for cells of type $lut.
Using template $paramod$3ab7a02e4f59b3797fed50685a40e5273a7f3af0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$77970d38e1d966d0c74631f307544f2efca4cbe7\$lut for cells of type $lut.
Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut.
Using template $paramod$ad3a97108c9f4d10f8acfa309b668b9455d3d733\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut.
Using template $paramod$1076d5b96410dc32bbe68df15017559464728316\$lut for cells of type $lut.
Using template $paramod$243c00f5eb9faa1d5ce3478fdc389a56070781f8\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec\$lut for cells of type $lut.
Using template $paramod$ac0bc5d4f1e6dcfd192559e5535468fd2bd6a006\$lut for cells of type $lut.
Using template $paramod$238ce1c123ccd5620a61157a2c5350ee6fc4d4ff\$lut for cells of type $lut.
Using template $paramod$3cebaa2b1e3336884049aae719aefe5eeb22e095\$lut for cells of type $lut.
Using template $paramod$e2e4d79bec18c28fa313e8bd8f4df6f8a38115b2\$lut for cells of type $lut.
Using template $paramod$cc08dba3aac8677e797984bdf18a09dd37547dd3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$892f09c166ac66d081a83c58c4c973fa8f6776c4\$lut for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$fe6b9140fa8badb9aa0c84263397a986020885c5\$lut for cells of type $lut.
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796\$lut for cells of type $lut.
Using template $paramod$36d45b81a385db1288ea7fa1afc7f85ff749786d\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$dbe700c159e973016afb4c227ed7292dc8875f1d\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$8b09f347504cfc0d3d65fbb4601497936543b1b3\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$70584433677bebb1f97d6827c9ba85513c8c682b\$lut for cells of type $lut.
Using template $paramod$1a6ea9151e749fe94446f4fb089a0baf2adde081\$lut for cells of type $lut.
Using template $paramod$ba05b8a1a425003df083aea0e69541f5cbdc68f2\$lut for cells of type $lut.
Using template $paramod$a710625e9e626ef5063a9eaeb20113d01f3592de\$lut for cells of type $lut.
Using template $paramod$63d28255a657ee32018d384f961c9cd429c82580\$lut for cells of type $lut.
Using template $paramod$f44e1eab45e047e709d5dfed32527eb1f7745488\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$437f25da516337c16dc93de12e162d405a8f2fb2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$5ef3e2a003d9029352faafd477743177813cd767\$lut for cells of type $lut.
Using template $paramod$aff3a645bb9f572421a4f0f49cf8987ceb4bcdc5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809\$lut for cells of type $lut.
Using template $paramod$4685bd76b86e63a7673afc1b48c70bed06b8ddfb\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut.
Using template $paramod$a4404e742e43b8bf8bde71df8b64cbe0c6ba02bd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$fccccf8bb2add7667329c686feec7546eb9a3ae3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$516e0c30d66d0cb1c81ba299a22eaf236a4b303a\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$ee4b98bad07bc0ced6d708127af2144fc9ba3e00\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3\$lut for cells of type $lut.
Using template $paramod$a9b475774a27fd84fed6eecb5f25fc5601b59ec5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$7d2ffb1127b6d3bcd5c17f2724b343ab1bc3ea11\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011100 for cells of type $lut.
Using template $paramod$001d9634602f00137f774620efde4c651c7a59ca\$lut for cells of type $lut.
Using template $paramod$f63fe32f78d5f3c5de711945c592c8c5ec2303ae\$lut for cells of type $lut.
Using template $paramod$126c776b0f5e5eef0fff11eb6abcf95b4d1189d2\$lut for cells of type $lut.
Using template $paramod$0f52647588235a7349ddd3f3432c9ac1e33ad9e1\$lut for cells of type $lut.
Using template $paramod$4e1cecab63d8e9cc19cb0241724b1211fb7856cb\$lut for cells of type $lut.
Using template $paramod$1a73a09a6e092620145558f2f06f2243b658a28f\$lut for cells of type $lut.
Using template $paramod$50666a8f9d622ca1f027a4587dfd5f2a7d8810c9\$lut for cells of type $lut.
Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$5bb4dad2090b93ea18c2a5cf3364462e38b08d14\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$979794232a1b12010187e90e68ca43f80b43cf7f\$lut for cells of type $lut.
Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut.
Using template $paramod$6961918e3564ac9ead822ba7e0287e436372f86a\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$f54c0ffd7b041ca43eac7710ab19c0666d826c22\$lut for cells of type $lut.
Using template $paramod$6d494330fd261ad16788e47f8e3f9eccfab42476\$lut for cells of type $lut.
Using template $paramod$af763bca85949884aefa417266a961f9c91132de\$lut for cells of type $lut.
Using template $paramod$b4d59a169df3392cc49f75ff3f36786eb368b5e7\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod$38742bbf7987158b879a68af2ec5225dead39592\$lut for cells of type $lut.
Using template $paramod$d0bf26260eea0e8530fb2e72eb38c60e28a47da8\$lut for cells of type $lut.
Using template $paramod$d53578aacfd93124244778d88be0e90eb09c1b1b\$lut for cells of type $lut.
Using template $paramod$987ba47d9f22b1c8fde8a2d7a2abff4be5df6ab8\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$6d7cc275871d0ceead401cadfae2ff1124665ec4\$lut for cells of type $lut.
Using template $paramod$e3d1f7a5be70c549b567cce08ebf28da10c48aca\$lut for cells of type $lut.
Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\$lut for cells of type $lut.
Using template $paramod$c35ad3063d5038410210ddc72c1fd5fed46413b4\$lut for cells of type $lut.
Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut.
Using template $paramod$12879138d1e376f344e47ea40be66b776233be75\$lut for cells of type $lut.
Using template $paramod$503f1caa2d36bf95454dec35a3ec553941806716\$lut for cells of type $lut.
Using template $paramod$4b23d751b3e1d7cde9cd1766bf20ceee12e38a3d\$lut for cells of type $lut.
Using template $paramod$21258e4f137fd0b5b0eaf41c5b0d170364c0ec37\$lut for cells of type $lut.
Using template $paramod$69f20e0703606f2ffd2ee27cd26f815bd5eeb6e9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$9a07e85e0c43955880b8d4f336046932e83335ec\$lut for cells of type $lut.
Using template $paramod$bb59fc9d73f3ced261e3a74efef030fd29d37b76\$lut for cells of type $lut.
Using template $paramod$ecf9cac817e9cbb222dc9e58a122faf05f34c860\$lut for cells of type $lut.
Using template $paramod$ad823946862e656cf7f96d606b18b8f972dc6d6c\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$67cf9e9d1d7679c6328496357baf58f31796fe98\$lut for cells of type $lut.
Using template $paramod$f2c2253739da195f4801437496b091d4b39d9051\$lut for cells of type $lut.
Using template $paramod$b297295e19b03521716155b85537bbe86d6a9ae6\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$cd05f04889088c47a0a5abae8c2d644fd314805e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut.
Using template $paramod$e08323ae5c39c98bbab150aa28bb73956c0bc47f\$lut for cells of type $lut.
Using template $paramod$054ad6ae20dc6b77853fd02d05a30f66c95c29fb\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$575b200168b9e109c2ed99df4359056f2c6696ac\$lut for cells of type $lut.
Using template $paramod$d4fae2c0d9ad2966369cd4e39b81c71bcd1327c9\$lut for cells of type $lut.
Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod$774861bf9b1885d60265e6ddea1c95a32f095489\$lut for cells of type $lut.
Using template $paramod$16985e1706243a019d93daf9cca618b30aa25f6c\$lut for cells of type $lut.
Using template $paramod$21672ccedebaf14674b9405dc8e596f04707c4db\$lut for cells of type $lut.
Using template $paramod$c6932d0419018208e5384761d78f0ead9bcc772f\$lut for cells of type $lut.
Using template $paramod$16773ebb5e5d8dbce266b8a86bb4af4574d61ffd\$lut for cells of type $lut.
Using template $paramod$27ecdd7cfe22d19cb765e27291229c9275d4bc83\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001011 for cells of type $lut.
Using template $paramod$70ebb6cf5bc7d63c5c1a98ccefefa2af79e8f2a9\$lut for cells of type $lut.
Using template $paramod$baa88887c4630803f83ac99e16ebe1294bd45a7a\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101000 for cells of type $lut.
Using template $paramod$868427562418b5dc988caeac6a54689ec9c9025e\$lut for cells of type $lut.
Using template $paramod$09194da5f2c8e08bed8f609fd0e254d8629b24b3\$lut for cells of type $lut.
Using template $paramod$f644023398ad1e2b0531ae68cdf65167cac9a042\$lut for cells of type $lut.
Using template $paramod$c59b53d80ea96d8b5203dc76db438edcc4ac492b\$lut for cells of type $lut.
Using template $paramod$a3cdc1eb771a2c6a16f64da161e11100ac409d2b\$lut for cells of type $lut.
Using template $paramod$376b64e1b363367ba758e2d4a9f90bb42b7b6248\$lut for cells of type $lut.
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100011 for cells of type $lut.
Using template $paramod$ef26adabe6060e01077b576cfe34e95e55a26aef\$lut for cells of type $lut.
Using template $paramod$affcf0f154430e5f24240efdee5f7d379dca7dd1\$lut for cells of type $lut.
Using template $paramod$4fd7b1305bda889fb7cf3da75b130d5c046d290a\$lut for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$ca13f43e42317a8affa4fd1d71c27d091bcacc68\$lut for cells of type $lut.
Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9\$lut for cells of type $lut.
Using template $paramod$21467c203c389a4feadb8ce2044a20839fad01b3\$lut for cells of type $lut.
Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut.
Using template $paramod$12e9049d8709286a770fe60b59ec4d94c39ce3c9\$lut for cells of type $lut.
Using template $paramod$ad66ff31645a1d4356de5b37218dbb8f3a4598ee\$lut for cells of type $lut.
Using template $paramod$3acbcfda92c30d4c719d6131dda3cd813f60e2b4\$lut for cells of type $lut.
Using template $paramod$53547ba0de08bbaa2219d0f5c1dbf5425d76a290\$lut for cells of type $lut.
Using template $paramod$a20b0c093af372402eecf32644de5f0208303079\$lut for cells of type $lut.
Using template $paramod$43c661319c94b3a52ddfa5a880539d205f6bbd5a\$lut for cells of type $lut.
Using template $paramod$79e7cf60c5406fc1d03111fae9bde1471166818b\$lut for cells of type $lut.
Using template $paramod$7e81a8ad8f27fccecc6e805c0ccf27dd70f2d2c2\$lut for cells of type $lut.
Using template $paramod$63e339ea2883ee008caae375935d0922a0b97d1f\$lut for cells of type $lut.
Using template $paramod$33e5359b2ffed03da55edf41d9bc4006935f2f69\$lut for cells of type $lut.
Using template $paramod$f9d599805186f77d6ad04b255d14441f83286ec8\$lut for cells of type $lut.
Using template $paramod$c299bfea24ff1990a23b453be488cdb6a5d0581c\$lut for cells of type $lut.
Using template $paramod$d9b052694296e7084bef89296751fcdab051f8df\$lut for cells of type $lut.
Using template $paramod$8c5b7259c9d9cd17395950154a06a8b3c48fdd5f\$lut for cells of type $lut.
Using template $paramod$02a202a1a635c330b20598d3bac3a9b6e5608208\$lut for cells of type $lut.
Using template $paramod$7a9d9396461df152f697894fa3b294ad1b285e08\$lut for cells of type $lut.
Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c\$lut for cells of type $lut.
Using template $paramod$680fd8d179aaa2b94b3b7c0dab400ac18bb55c38\$lut for cells of type $lut.
Using template $paramod$68036a40c5a685bb357be70d1f585fbcff135b53\$lut for cells of type $lut.
Using template $paramod$f85118f727cbfc385385a0fcb2d977c74c137bb0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111000 for cells of type $lut.
Using template $paramod$7d791c2363f4f019348f93a148b2a44b4ba6b5b3\$lut for cells of type $lut.
Using template $paramod$bfc5ec0efb7a7554a714fba569e000275a25c525\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100001 for cells of type $lut.
Using template $paramod$5b13d2ee598c87cdbe912286a35c6fd102e2087c\$lut for cells of type $lut.
Using template $paramod$ad7246a24b6e56b3b67deb6ce92da7632476b727\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa\$lut for cells of type $lut.
Using template $paramod$965f8f2fa1a796a6c51222eabb50fbd26e97d98b\$lut for cells of type $lut.
Using template $paramod$dfe991354c46989496cb28816eb528b52a03f85c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut.
Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b\$lut for cells of type $lut.
Using template $paramod$0e12ea2d93e07ffd38b30c47251a5243bc5dc262\$lut for cells of type $lut.
Using template $paramod$bff35d97b07dddb273c72678bf847e2b78003681\$lut for cells of type $lut.
Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441\$lut for cells of type $lut.
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut.
Using template $paramod$987d4c6b9265ec278a119d59a96dbc9e6ffc65bc\$lut for cells of type $lut.
Using template $paramod$d184020c951bc948452f5dea6b3f065c16694086\$lut for cells of type $lut.
Using template $paramod$172d96dd42ce7449cb4e1d402244099ce11a0b1c\$lut for cells of type $lut.
Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11\$lut for cells of type $lut.
Using template $paramod$92d606332f1ee29cf1de0bfa0bc5c21b77f4493e\$lut for cells of type $lut.
Using template $paramod$933f4f3e373a784da64d137def3625bdd36d1695\$lut for cells of type $lut.
Using template $paramod$d94f7d3127937b5dc7a66ea8cc409d7cf91bc488\$lut for cells of type $lut.
Using template $paramod$cd0c2a3d5302372e3760f1a1037771a8cae61f4b\$lut for cells of type $lut.
Using template $paramod$9747e27d592a5de65fe94778f9dc8ad338a6e3d4\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~4314 debug messages>
6.46. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in Murax.
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17181.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17191.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17192.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17193.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17183.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16641.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16636.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17117.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16123.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16651.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16737.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16645.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16739.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16421.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17061.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16735.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17123.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17070.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17069.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16741.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17098.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17111.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$16632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17166.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17190.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17173.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17244.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17180.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17359.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17385.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Optimizing lut $abc$16113$auto$blifparse.cc:515:parse_blif$17594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Removed 0 unused cells and 3274 unused wires.
6.47. Executing AUTONAME pass.
Renamed 21428 objects in module Murax (46 iterations).
<suppressed ~4683 debug messages>
6.48. Executing HIERARCHY pass (managing design hierarchy).
6.48.1. Analyzing design hierarchy..
Top module: \Murax
6.48.2. Analyzing design hierarchy..
Top module: \Murax
Removed 0 unused modules.
6.49. Printing statistics.
=== Murax ===
Number of wires: 2397
Number of wire bits: 13510
Number of public wires: 2397
Number of public wire bits: 13510
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 3455
CCU2C 94
DP16KD 4
L6MUX21 27
LUT4 1722
PFUMX 209
TRELLIS_DPR16X4 36
TRELLIS_FF 1363
6.50. Executing CHECK pass (checking for obvious problems).
Checking module Murax...
Found and reported 0 problems.
6.51. Executing JSON backend.
Warnings: 65 unique messages, 65 total
End of script. Logfile hash: 18aae72bca, CPU: user 6.26s system 0.08s, MEM: 330.91 MB peak
Yosys 0.13+28 (git sha1 fc40df091, gcc 11.2.0-7ubuntu2 -fPIC -Os)
Time spent: 17% 42x opt_clean (1 sec), 16% 51x opt_expr (1 sec), ...