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abstractaccelerator/VexRiscv/fpga/gen/synth.v

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/* Generated by Yosys 0.13+28 (git sha1 fc40df091, gcc 11.2.0-7ubuntu2 -fPIC -Os) */
module Apb3Decoder(io_input_PADDR, io_input_PSEL, io_input_PENABLE, io_input_PREADY, io_input_PWRITE, io_input_PWDATA, io_input_PRDATA, io_input_PSLVERROR, io_output_PADDR, io_output_PSEL, io_output_PENABLE, io_output_PREADY, io_output_PWRITE, io_output_PWDATA, io_output_PRDATA, io_output_PSLVERROR);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
input [19:0] io_input_PADDR;
wire [19:0] io_input_PADDR;
input io_input_PENABLE;
wire io_input_PENABLE;
output [31:0] io_input_PRDATA;
wire [31:0] io_input_PRDATA;
output io_input_PREADY;
wire io_input_PREADY;
input io_input_PSEL;
wire io_input_PSEL;
output io_input_PSLVERROR;
wire io_input_PSLVERROR;
input [31:0] io_input_PWDATA;
wire [31:0] io_input_PWDATA;
input io_input_PWRITE;
wire io_input_PWRITE;
output [19:0] io_output_PADDR;
wire [19:0] io_output_PADDR;
output io_output_PENABLE;
wire io_output_PENABLE;
input [31:0] io_output_PRDATA;
wire [31:0] io_output_PRDATA;
input io_output_PREADY;
wire io_output_PREADY;
output [2:0] io_output_PSEL;
wire [2:0] io_output_PSEL;
input io_output_PSLVERROR;
wire io_output_PSLVERROR;
output [31:0] io_output_PWDATA;
wire [31:0] io_output_PWDATA;
output io_output_PWRITE;
wire io_output_PWRITE;
wire when_Apb3Decoder_l88;
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.Y_WIDTH(32'd1)
) _04_ (
.A(io_input_PADDR[19:12]),
.Y(_00_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd8),
.Y_WIDTH(32'd1)
) _05_ (
.A(io_input_PADDR[19:12]),
.B(8'h10),
.Y(_01_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd8),
.Y_WIDTH(32'd1)
) _06_ (
.A(io_input_PADDR[19:12]),
.B(8'h20),
.Y(_02_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _07_ (
.A(io_output_PSEL),
.Y(_03_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _08_ (
.A(_00_),
.B(io_input_PSEL),
.Y(io_output_PSEL[0])
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _09_ (
.A(_01_),
.B(io_input_PSEL),
.Y(io_output_PSEL[1])
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _10_ (
.A(_02_),
.B(io_input_PSEL),
.Y(io_output_PSEL[2])
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _11_ (
.A(io_input_PSEL),
.B(_03_),
.Y(when_Apb3Decoder_l88)
);
\$mux #(
.WIDTH(32'd1)
) _12_ (
.A(io_output_PSLVERROR),
.B(1'h1),
.S(when_Apb3Decoder_l88),
.Y(io_input_PSLVERROR)
);
\$mux #(
.WIDTH(32'd1)
) _13_ (
.A(io_output_PREADY),
.B(1'h1),
.S(when_Apb3Decoder_l88),
.Y(io_input_PREADY)
);
assign io_input_PRDATA = io_output_PRDATA;
assign io_output_PADDR = io_input_PADDR;
assign io_output_PENABLE = io_input_PENABLE;
assign io_output_PWDATA = io_input_PWDATA;
assign io_output_PWRITE = io_input_PWRITE;
endmodule
module Apb3Gpio(io_apb_PADDR, io_apb_PSEL, io_apb_PENABLE, io_apb_PREADY, io_apb_PWRITE, io_apb_PWDATA, io_apb_PRDATA, io_apb_PSLVERROR, io_gpio_read, io_gpio_write, io_gpio_writeEnable, io_value, io_mainClk, resetCtrl_systemReset);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire ctrl_doWrite;
input [3:0] io_apb_PADDR;
wire [3:0] io_apb_PADDR;
input io_apb_PENABLE;
wire io_apb_PENABLE;
output [31:0] io_apb_PRDATA;
wire [31:0] io_apb_PRDATA;
output io_apb_PREADY;
wire io_apb_PREADY;
input io_apb_PSEL;
wire io_apb_PSEL;
output io_apb_PSLVERROR;
wire io_apb_PSLVERROR;
input [31:0] io_apb_PWDATA;
wire [31:0] io_apb_PWDATA;
input io_apb_PWRITE;
wire io_apb_PWRITE;
input [31:0] io_gpio_read;
wire [31:0] io_gpio_read;
wire [31:0] io_gpio_read_buffercc_io_dataOut;
output [31:0] io_gpio_write;
wire [31:0] io_gpio_write;
output [31:0] io_gpio_writeEnable;
wire [31:0] io_gpio_writeEnable;
wire [31:0] io_gpio_writeEnable_driver;
wire [31:0] io_gpio_write_driver;
input io_mainClk;
wire io_mainClk;
output [31:0] io_value;
wire [31:0] io_value;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(32'd0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd32)
) _06_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_apb_PWDATA),
.EN(_00_),
.Q(io_gpio_writeEnable_driver)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd32)
) _07_ (
.CLK(io_mainClk),
.D(io_apb_PWDATA),
.EN(_01_),
.Q(io_gpio_write_driver)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _08_ (
.A({ _04_, ctrl_doWrite }),
.Y(_00_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _09_ (
.A({ _03_, ctrl_doWrite }),
.Y(_01_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _10_ (
.A(io_apb_PSEL),
.B(io_apb_PENABLE),
.Y(_02_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _11_ (
.A(_02_),
.B(io_apb_PWRITE),
.Y(ctrl_doWrite)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _12_ (
.A(io_apb_PADDR),
.B(3'h4),
.Y(_03_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.B_SIGNED(32'd0),
.B_WIDTH(32'd4),
.Y_WIDTH(32'd1)
) _13_ (
.A(io_apb_PADDR),
.B(4'h8),
.Y(_04_)
);
\$pmux #(
.S_WIDTH(32'd3),
.WIDTH(32'd32)
) _14_ (
.A(32'd0),
.B({ io_gpio_read_buffercc_io_dataOut, io_gpio_write_driver, io_gpio_writeEnable_driver }),
.S({ _05_, _03_, _04_ }),
.Y(io_apb_PRDATA)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.Y_WIDTH(32'd1)
) _15_ (
.A(io_apb_PADDR),
.Y(_05_)
);
BufferCC_2 io_gpio_read_buffercc (
.io_dataIn(io_gpio_read),
.io_dataOut(io_gpio_read_buffercc_io_dataOut),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign io_apb_PREADY = 1'h1;
assign io_apb_PSLVERROR = 1'h0;
assign io_gpio_write = io_gpio_write_driver;
assign io_gpio_writeEnable = io_gpio_writeEnable_driver;
assign io_value = io_gpio_read_buffercc_io_dataOut;
endmodule
module Apb3Router(io_input_PADDR, io_input_PSEL, io_input_PENABLE, io_input_PREADY, io_input_PWRITE, io_input_PWDATA, io_input_PRDATA, io_input_PSLVERROR, io_outputs_0_PADDR, io_outputs_0_PSEL, io_outputs_0_PENABLE, io_outputs_0_PREADY, io_outputs_0_PWRITE, io_outputs_0_PWDATA, io_outputs_0_PRDATA, io_outputs_0_PSLVERROR, io_outputs_1_PADDR, io_outputs_1_PSEL, io_outputs_1_PENABLE, io_outputs_1_PREADY, io_outputs_1_PWRITE
, io_outputs_1_PWDATA, io_outputs_1_PRDATA, io_outputs_1_PSLVERROR, io_outputs_2_PADDR, io_outputs_2_PSEL, io_outputs_2_PENABLE, io_outputs_2_PREADY, io_outputs_2_PWRITE, io_outputs_2_PWDATA, io_outputs_2_PRDATA, io_outputs_2_PSLVERROR, io_mainClk, resetCtrl_systemReset);
wire _0_;
wire _1_;
wire [31:0] _zz_io_input_PRDATA;
wire _zz_io_input_PREADY;
wire _zz_io_input_PSLVERROR;
wire _zz_selIndex;
wire _zz_selIndex_1;
input [19:0] io_input_PADDR;
wire [19:0] io_input_PADDR;
input io_input_PENABLE;
wire io_input_PENABLE;
output [31:0] io_input_PRDATA;
wire [31:0] io_input_PRDATA;
output io_input_PREADY;
wire io_input_PREADY;
input [2:0] io_input_PSEL;
wire [2:0] io_input_PSEL;
output io_input_PSLVERROR;
wire io_input_PSLVERROR;
input [31:0] io_input_PWDATA;
wire [31:0] io_input_PWDATA;
input io_input_PWRITE;
wire io_input_PWRITE;
input io_mainClk;
wire io_mainClk;
output [19:0] io_outputs_0_PADDR;
wire [19:0] io_outputs_0_PADDR;
output io_outputs_0_PENABLE;
wire io_outputs_0_PENABLE;
input [31:0] io_outputs_0_PRDATA;
wire [31:0] io_outputs_0_PRDATA;
input io_outputs_0_PREADY;
wire io_outputs_0_PREADY;
output io_outputs_0_PSEL;
wire io_outputs_0_PSEL;
input io_outputs_0_PSLVERROR;
wire io_outputs_0_PSLVERROR;
output [31:0] io_outputs_0_PWDATA;
wire [31:0] io_outputs_0_PWDATA;
output io_outputs_0_PWRITE;
wire io_outputs_0_PWRITE;
output [19:0] io_outputs_1_PADDR;
wire [19:0] io_outputs_1_PADDR;
output io_outputs_1_PENABLE;
wire io_outputs_1_PENABLE;
input [31:0] io_outputs_1_PRDATA;
wire [31:0] io_outputs_1_PRDATA;
input io_outputs_1_PREADY;
wire io_outputs_1_PREADY;
output io_outputs_1_PSEL;
wire io_outputs_1_PSEL;
input io_outputs_1_PSLVERROR;
wire io_outputs_1_PSLVERROR;
output [31:0] io_outputs_1_PWDATA;
wire [31:0] io_outputs_1_PWDATA;
output io_outputs_1_PWRITE;
wire io_outputs_1_PWRITE;
output [19:0] io_outputs_2_PADDR;
wire [19:0] io_outputs_2_PADDR;
output io_outputs_2_PENABLE;
wire io_outputs_2_PENABLE;
input [31:0] io_outputs_2_PRDATA;
wire [31:0] io_outputs_2_PRDATA;
input io_outputs_2_PREADY;
wire io_outputs_2_PREADY;
output io_outputs_2_PSEL;
wire io_outputs_2_PSEL;
input io_outputs_2_PSLVERROR;
wire io_outputs_2_PSLVERROR;
output [31:0] io_outputs_2_PWDATA;
wire [31:0] io_outputs_2_PWDATA;
output io_outputs_2_PWRITE;
wire io_outputs_2_PWRITE;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
wire [1:0] selIndex;
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd2)
) _2_ (
.CLK(io_mainClk),
.D(io_input_PSEL[2:1]),
.Q(selIndex)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd1)
) _3_ (
.A(io_outputs_2_PSLVERROR),
.B({ io_outputs_0_PSLVERROR, io_outputs_1_PSLVERROR }),
.S({ _1_, _0_ }),
.Y(io_input_PSLVERROR)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _4_ (
.A(selIndex),
.B(1'h1),
.Y(_0_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _5_ (
.A(selIndex),
.Y(_1_)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd32)
) _6_ (
.A(io_outputs_2_PRDATA),
.B({ io_outputs_0_PRDATA, io_outputs_1_PRDATA }),
.S({ _1_, _0_ }),
.Y(io_input_PRDATA)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd1)
) _7_ (
.A(io_outputs_2_PREADY),
.B({ io_outputs_0_PREADY, io_outputs_1_PREADY }),
.S({ _1_, _0_ }),
.Y(io_input_PREADY)
);
assign _zz_io_input_PRDATA = io_input_PRDATA;
assign _zz_io_input_PREADY = io_input_PREADY;
assign _zz_io_input_PSLVERROR = io_input_PSLVERROR;
assign _zz_selIndex = io_input_PSEL[1];
assign _zz_selIndex_1 = io_input_PSEL[2];
assign io_outputs_0_PADDR = io_input_PADDR;
assign io_outputs_0_PENABLE = io_input_PENABLE;
assign io_outputs_0_PSEL = io_input_PSEL[0];
assign io_outputs_0_PWDATA = io_input_PWDATA;
assign io_outputs_0_PWRITE = io_input_PWRITE;
assign io_outputs_1_PADDR = io_input_PADDR;
assign io_outputs_1_PENABLE = io_input_PENABLE;
assign io_outputs_1_PSEL = io_input_PSEL[1];
assign io_outputs_1_PWDATA = io_input_PWDATA;
assign io_outputs_1_PWRITE = io_input_PWRITE;
assign io_outputs_2_PADDR = io_input_PADDR;
assign io_outputs_2_PENABLE = io_input_PENABLE;
assign io_outputs_2_PSEL = io_input_PSEL[2];
assign io_outputs_2_PWDATA = io_input_PWDATA;
assign io_outputs_2_PWRITE = io_input_PWRITE;
endmodule
module Apb3UartCtrl(io_apb_PADDR, io_apb_PSEL, io_apb_PENABLE, io_apb_PREADY, io_apb_PWRITE, io_apb_PWDATA, io_apb_PRDATA, io_uart_txd, io_uart_rxd, io_interrupt, io_mainClk, resetCtrl_systemReset);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire [4:0] _06_;
wire [4:0] _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire _27_;
wire [19:0] _zz_1;
wire _zz_bridge_misc_breakDetected;
wire _zz_bridge_misc_doBreak;
wire _zz_bridge_misc_doBreak_1;
wire _zz_bridge_misc_readError;
wire _zz_bridge_misc_readOverflowError;
wire _zz_bridge_write_streamUnbuffered_valid;
wire [4:0] _zz_io_apb_PRDATA;
wire bridge_interruptCtrl_interrupt;
wire bridge_interruptCtrl_readInt;
wire bridge_interruptCtrl_readIntEnable;
wire bridge_interruptCtrl_writeInt;
wire bridge_interruptCtrl_writeIntEnable;
wire bridge_misc_breakDetected;
wire bridge_misc_doBreak;
wire bridge_misc_readError;
wire bridge_misc_readOverflowError;
wire [7:0] bridge_read_streamBreaked_payload;
wire bridge_read_streamBreaked_ready;
wire bridge_read_streamBreaked_valid;
wire [19:0] bridge_uartConfigReg_clockDivider;
wire [2:0] bridge_uartConfigReg_frame_dataLength;
wire [1:0] bridge_uartConfigReg_frame_parity;
wire bridge_uartConfigReg_frame_stop;
wire [7:0] bridge_write_streamUnbuffered_payload;
wire [4:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability;
wire [4:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy;
wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload;
wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid;
wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready;
wire bridge_write_streamUnbuffered_ready;
wire bridge_write_streamUnbuffered_valid;
wire busCtrl_doRead;
wire busCtrl_doWrite;
input [4:0] io_apb_PADDR;
wire [4:0] io_apb_PADDR;
input io_apb_PENABLE;
wire io_apb_PENABLE;
output [31:0] io_apb_PRDATA;
wire [31:0] io_apb_PRDATA;
output io_apb_PREADY;
wire io_apb_PREADY;
input io_apb_PSEL;
wire io_apb_PSEL;
input [31:0] io_apb_PWDATA;
wire [31:0] io_apb_PWDATA;
input io_apb_PWRITE;
wire io_apb_PWRITE;
output io_interrupt;
wire io_interrupt;
input io_mainClk;
wire io_mainClk;
input io_uart_rxd;
wire io_uart_rxd;
output io_uart_txd;
wire io_uart_txd;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
wire uartCtrl_1_io_readBreak;
wire uartCtrl_1_io_readBreak_regNext;
wire uartCtrl_1_io_readError;
wire uartCtrl_1_io_read_isStall;
wire [7:0] uartCtrl_1_io_read_payload;
wire [4:0] uartCtrl_1_io_read_queueWithOccupancy_io_availability;
wire [4:0] uartCtrl_1_io_read_queueWithOccupancy_io_occupancy;
wire [7:0] uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload;
wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready;
wire uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid;
wire uartCtrl_1_io_read_queueWithOccupancy_io_push_ready;
wire uartCtrl_1_io_read_valid;
wire uartCtrl_1_io_uart_txd;
wire uartCtrl_1_io_write_ready;
wire when_BusSlaveFactory_l335;
wire when_BusSlaveFactory_l335_1;
wire when_BusSlaveFactory_l335_2;
wire when_BusSlaveFactory_l335_3;
wire when_BusSlaveFactory_l337;
wire when_BusSlaveFactory_l337_1;
wire when_BusSlaveFactory_l337_2;
wire when_BusSlaveFactory_l337_3;
wire when_BusSlaveFactory_l366;
wire when_BusSlaveFactory_l368;
wire when_UartCtrl_l155;
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd5)
) _28_ (
.A(5'h10),
.B(bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy),
.BI(1'h1),
.CI(1'h1),
.CO(_07_),
.X(_06_),
.Y(_zz_io_apb_PRDATA)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) bridge_misc_readOverflowError_reg /* _29_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_03_),
.EN(_12_),
.Q(bridge_misc_readOverflowError)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) bridge_misc_readError_reg /* _30_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_02_),
.EN(_13_),
.Q(bridge_misc_readError)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) bridge_interruptCtrl_readIntEnable_reg /* _31_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_apb_PWDATA[1]),
.EN(_14_),
.Q(bridge_interruptCtrl_readIntEnable)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) bridge_interruptCtrl_writeIntEnable_reg /* _32_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_apb_PWDATA[0]),
.EN(_14_),
.Q(bridge_interruptCtrl_writeIntEnable)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _33_ (
.A({ uartCtrl_1_io_read_isStall, when_BusSlaveFactory_l335, io_apb_PWDATA[1] }),
.B(2'h2),
.Y(_08_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _34_ (
.A({ uartCtrl_1_io_read_isStall, when_BusSlaveFactory_l335 }),
.Y(_09_)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _35_ (
.A({ when_BusSlaveFactory_l335, uartCtrl_1_io_readError, io_apb_PWDATA[0] }),
.B(3'h4),
.Y(_10_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _36_ (
.A({ when_BusSlaveFactory_l335, uartCtrl_1_io_readError }),
.Y(_11_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _37_ (
.A({ _08_, _09_ }),
.Y(_12_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _38_ (
.A({ _11_, _10_ }),
.Y(_13_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _39_ (
.A({ _25_, busCtrl_doWrite }),
.Y(_14_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _40_ (
.A(io_apb_PSEL),
.B(io_apb_PENABLE),
.Y(_15_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _41_ (
.A(_15_),
.B(io_apb_PWRITE),
.Y(busCtrl_doWrite)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _42_ (
.A(_15_),
.B(_16_),
.Y(busCtrl_doRead)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _43_ (
.A(bridge_interruptCtrl_readIntEnable),
.B(bridge_read_streamBreaked_valid),
.Y(bridge_interruptCtrl_readInt)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _44_ (
.A(bridge_interruptCtrl_writeIntEnable),
.B(_17_),
.Y(bridge_interruptCtrl_writeInt)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _45_ (
.A(uartCtrl_1_io_read_valid),
.B(_18_),
.Y(uartCtrl_1_io_read_isStall)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _46_ (
.A(uartCtrl_1_io_readBreak),
.B(_19_),
.Y(when_UartCtrl_l155)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _47_ (
.A(io_apb_PWRITE),
.Y(_16_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _48_ (
.A(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid),
.Y(_17_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _49_ (
.A(uartCtrl_1_io_read_queueWithOccupancy_io_push_ready),
.Y(_18_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _50_ (
.A(uartCtrl_1_io_readBreak_regNext),
.Y(_19_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _51_ (
.A(bridge_interruptCtrl_readInt),
.B(bridge_interruptCtrl_writeInt),
.Y(io_interrupt)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) uartCtrl_1_io_readBreak_regNext_reg /* _52_ */ (
.CLK(io_mainClk),
.D(uartCtrl_1_io_readBreak),
.Q(uartCtrl_1_io_readBreak_regNext)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) bridge_misc_breakDetected_reg /* _53_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_00_),
.Q(bridge_misc_breakDetected)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) bridge_misc_doBreak_reg /* _54_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_01_),
.Q(bridge_misc_doBreak)
);
\$mux #(
.WIDTH(32'd1)
) _55_ (
.A(bridge_misc_doBreak),
.B(1'h1),
.S(io_apb_PWDATA[10]),
.Y(_20_)
);
\$mux #(
.WIDTH(32'd1)
) _56_ (
.A(bridge_misc_doBreak),
.B(_20_),
.S(when_BusSlaveFactory_l335),
.Y(_21_)
);
\$mux #(
.WIDTH(32'd1)
) _57_ (
.A(_21_),
.B(1'h0),
.S(io_apb_PWDATA[11]),
.Y(_22_)
);
\$mux #(
.WIDTH(32'd1)
) _58_ (
.A(_21_),
.B(_22_),
.S(when_BusSlaveFactory_l335),
.Y(_01_)
);
\$mux #(
.WIDTH(32'd1)
) _59_ (
.A(bridge_misc_breakDetected),
.B(1'h1),
.S(when_UartCtrl_l155),
.Y(_23_)
);
\$mux #(
.WIDTH(32'd1)
) _60_ (
.A(_23_),
.B(1'h0),
.S(io_apb_PWDATA[9]),
.Y(_24_)
);
\$mux #(
.WIDTH(32'd1)
) _61_ (
.A(_23_),
.B(_24_),
.S(when_BusSlaveFactory_l335),
.Y(_00_)
);
\$mux #(
.WIDTH(32'd1)
) _62_ (
.A(1'h0),
.B(1'h1),
.S(uartCtrl_1_io_read_isStall),
.Y(_03_)
);
\$mux #(
.WIDTH(32'd1)
) _63_ (
.A(1'h0),
.B(1'h1),
.S(uartCtrl_1_io_readError),
.Y(_02_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _64_ (
.A(io_apb_PADDR),
.B(3'h4),
.Y(_25_)
);
\$mux #(
.WIDTH(32'd1)
) _65_ (
.A(1'h0),
.B(1'h1),
.S(busCtrl_doWrite),
.Y(_04_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _66_ (
.A(io_apb_PADDR),
.B(5'h10),
.Y(_26_)
);
\$mux #(
.WIDTH(32'd1)
) _67_ (
.A(1'h0),
.B(_04_),
.S(_26_),
.Y(when_BusSlaveFactory_l335)
);
\$mux #(
.WIDTH(32'd1)
) _68_ (
.A(1'h0),
.B(1'h1),
.S(busCtrl_doRead),
.Y(_05_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _69_ (
.A(io_apb_PADDR),
.Y(_27_)
);
\$mux #(
.WIDTH(32'd1)
) _70_ (
.A(1'h0),
.B(_05_),
.S(_27_),
.Y(bridge_read_streamBreaked_ready)
);
\$mux #(
.WIDTH(32'd1)
) _71_ (
.A(bridge_read_streamBreaked_ready),
.B(1'h1),
.S(uartCtrl_1_io_readBreak),
.Y(uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready)
);
\$mux #(
.WIDTH(32'd1)
) _72_ (
.A(uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid),
.B(1'h0),
.S(uartCtrl_1_io_readBreak),
.Y(bridge_read_streamBreaked_valid)
);
\$mux #(
.WIDTH(32'd1)
) _73_ (
.A(1'h0),
.B(_04_),
.S(_27_),
.Y(bridge_write_streamUnbuffered_valid)
);
\$mux #(
.WIDTH(32'd4)
) _74_ (
.A(4'h0),
.B(_zz_io_apb_PRDATA[4:1]),
.S(_25_),
.Y(io_apb_PRDATA[20:17])
);
\$mux #(
.WIDTH(32'd6)
) _75_ (
.A(6'h00),
.B(uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[7:2]),
.S(_27_),
.Y(io_apb_PRDATA[7:2])
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd1)
) _76_ (
.A(1'h0),
.B({ bridge_read_streamBreaked_valid, _zz_io_apb_PRDATA[0] }),
.S({ _27_, _25_ }),
.Y(io_apb_PRDATA[16])
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd1)
) _77_ (
.A(1'h0),
.B({ bridge_interruptCtrl_writeInt, uartCtrl_1_io_readBreak }),
.S({ _25_, _26_ }),
.Y(io_apb_PRDATA[8])
);
\$mux #(
.WIDTH(32'd1)
) _78_ (
.A(1'h0),
.B(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid),
.S(_25_),
.Y(io_apb_PRDATA[15])
);
\$pmux #(
.S_WIDTH(32'd3),
.WIDTH(32'd1)
) _79_ (
.A(1'h0),
.B({ uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[1], bridge_interruptCtrl_readIntEnable, bridge_misc_readOverflowError }),
.S({ _27_, _25_, _26_ }),
.Y(io_apb_PRDATA[1])
);
\$mux #(
.WIDTH(32'd5)
) _80_ (
.A(5'h00),
.B(uartCtrl_1_io_read_queueWithOccupancy_io_occupancy),
.S(_25_),
.Y(io_apb_PRDATA[28:24])
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd1)
) _81_ (
.A(1'h0),
.B({ bridge_interruptCtrl_readInt, bridge_misc_breakDetected }),
.S({ _25_, _26_ }),
.Y(io_apb_PRDATA[9])
);
\$pmux #(
.S_WIDTH(32'd3),
.WIDTH(32'd1)
) _82_ (
.A(1'h0),
.B({ uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload[0], bridge_interruptCtrl_writeIntEnable, bridge_misc_readError }),
.S({ _27_, _25_, _26_ }),
.Y(io_apb_PRDATA[0])
);
StreamFifo bridge_write_streamUnbuffered_queueWithOccupancy (
.io_availability(bridge_write_streamUnbuffered_queueWithOccupancy_io_availability),
.io_flush(1'h0),
.io_mainClk(io_mainClk),
.io_occupancy(bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy),
.io_pop_payload(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload),
.io_pop_ready(uartCtrl_1_io_write_ready),
.io_pop_valid(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid),
.io_push_payload(io_apb_PWDATA[7:0]),
.io_push_ready(bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready),
.io_push_valid(bridge_write_streamUnbuffered_valid),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
UartCtrl uartCtrl_1 (
.io_config_clockDivider(20'h00013),
.io_config_frame_dataLength(3'h7),
.io_config_frame_parity(2'h0),
.io_config_frame_stop(1'h0),
.io_mainClk(io_mainClk),
.io_readBreak(uartCtrl_1_io_readBreak),
.io_readError(uartCtrl_1_io_readError),
.io_read_payload(uartCtrl_1_io_read_payload),
.io_read_ready(uartCtrl_1_io_read_queueWithOccupancy_io_push_ready),
.io_read_valid(uartCtrl_1_io_read_valid),
.io_uart_rxd(io_uart_rxd),
.io_uart_txd(uartCtrl_1_io_uart_txd),
.io_writeBreak(bridge_misc_doBreak),
.io_write_payload(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload),
.io_write_ready(uartCtrl_1_io_write_ready),
.io_write_valid(bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
StreamFifo uartCtrl_1_io_read_queueWithOccupancy (
.io_availability(uartCtrl_1_io_read_queueWithOccupancy_io_availability),
.io_flush(1'h0),
.io_mainClk(io_mainClk),
.io_occupancy(uartCtrl_1_io_read_queueWithOccupancy_io_occupancy),
.io_pop_payload(uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload),
.io_pop_ready(uartCtrl_1_io_read_queueWithOccupancy_io_pop_ready),
.io_pop_valid(uartCtrl_1_io_read_queueWithOccupancy_io_pop_valid),
.io_push_payload(uartCtrl_1_io_read_payload),
.io_push_ready(uartCtrl_1_io_read_queueWithOccupancy_io_push_ready),
.io_push_valid(uartCtrl_1_io_read_valid),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign _zz_1 = 20'h00013;
assign _zz_bridge_misc_breakDetected = 1'h0;
assign _zz_bridge_misc_doBreak = 1'h1;
assign _zz_bridge_misc_doBreak_1 = 1'h0;
assign _zz_bridge_misc_readError = 1'h0;
assign _zz_bridge_misc_readOverflowError = 1'h0;
assign _zz_bridge_write_streamUnbuffered_valid = bridge_write_streamUnbuffered_valid;
assign bridge_interruptCtrl_interrupt = io_interrupt;
assign bridge_read_streamBreaked_payload = uartCtrl_1_io_read_queueWithOccupancy_io_pop_payload;
assign bridge_uartConfigReg_clockDivider = 20'h00013;
assign bridge_uartConfigReg_frame_dataLength = 3'h7;
assign bridge_uartConfigReg_frame_parity = 2'h0;
assign bridge_uartConfigReg_frame_stop = 1'h0;
assign bridge_write_streamUnbuffered_payload = io_apb_PWDATA[7:0];
assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready;
assign { io_apb_PRDATA[31:29], io_apb_PRDATA[23:21], io_apb_PRDATA[14:10] } = 11'h000;
assign io_apb_PREADY = 1'h1;
assign io_uart_txd = uartCtrl_1_io_uart_txd;
assign when_BusSlaveFactory_l335_1 = when_BusSlaveFactory_l335;
assign when_BusSlaveFactory_l335_2 = when_BusSlaveFactory_l335;
assign when_BusSlaveFactory_l335_3 = when_BusSlaveFactory_l335;
assign when_BusSlaveFactory_l337 = io_apb_PWDATA[0];
assign when_BusSlaveFactory_l337_1 = io_apb_PWDATA[1];
assign when_BusSlaveFactory_l337_2 = io_apb_PWDATA[9];
assign when_BusSlaveFactory_l337_3 = io_apb_PWDATA[11];
assign when_BusSlaveFactory_l366 = when_BusSlaveFactory_l335;
assign when_BusSlaveFactory_l368 = io_apb_PWDATA[10];
endmodule
module BufferCC(io_dataIn, io_dataOut, io_mainClk, resetCtrl_systemReset);
wire buffers_0;
wire buffers_1;
input io_dataIn;
wire io_dataIn;
output io_dataOut;
wire io_dataOut;
input io_mainClk;
wire io_mainClk;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) buffers_0_reg /* _0_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_dataIn),
.Q(buffers_0)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) buffers_1_reg /* _1_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(buffers_0),
.Q(buffers_1)
);
assign io_dataOut = buffers_1;
endmodule
module BufferCC_1(io_dataIn, io_dataOut, io_mainClk, resetCtrl_mainClkReset);
wire buffers_0;
wire buffers_1;
input io_dataIn;
wire io_dataIn;
output io_dataOut;
wire io_dataOut;
input io_mainClk;
wire io_mainClk;
input resetCtrl_mainClkReset;
wire resetCtrl_mainClkReset;
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) buffers_0_reg /* _0_ */ (
.CLK(io_mainClk),
.D(io_dataIn),
.Q(buffers_0)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) buffers_1_reg /* _1_ */ (
.CLK(io_mainClk),
.D(buffers_0),
.Q(buffers_1)
);
assign io_dataOut = buffers_1;
endmodule
module BufferCC_2(io_dataIn, io_dataOut, io_mainClk, resetCtrl_systemReset);
wire [31:0] buffers_0;
wire [31:0] buffers_1;
input [31:0] io_dataIn;
wire [31:0] io_dataIn;
output [31:0] io_dataOut;
wire [31:0] io_dataOut;
input io_mainClk;
wire io_mainClk;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd32)
) _0_ (
.CLK(io_mainClk),
.D(io_dataIn),
.Q(buffers_0)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd32)
) _1_ (
.CLK(io_mainClk),
.D(buffers_0),
.Q(buffers_1)
);
assign io_dataOut = buffers_1;
endmodule
module BufferCC_3(io_dataIn, io_dataOut, io_mainClk);
wire buffers_0;
wire buffers_1;
input io_dataIn;
wire io_dataIn;
output io_dataOut;
wire io_dataOut;
input io_mainClk;
wire io_mainClk;
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) buffers_0_reg /* _0_ */ (
.CLK(io_mainClk),
.D(io_dataIn),
.Q(buffers_0)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) buffers_1_reg /* _1_ */ (
.CLK(io_mainClk),
.D(buffers_0),
.Q(buffers_1)
);
assign io_dataOut = buffers_1;
endmodule
module FlowCCByToggle(io_input_valid, io_input_payload_last, io_input_payload_fragment, io_output_valid, io_output_payload_last, io_output_payload_fragment, io_jtag_tck, io_mainClk, resetCtrl_mainClkReset);
wire _0_;
wire inputArea_data_fragment;
wire inputArea_data_last;
wire inputArea_target;
wire inputArea_target_buffercc_io_dataOut;
input io_input_payload_fragment;
wire io_input_payload_fragment;
input io_input_payload_last;
wire io_input_payload_last;
input io_input_valid;
wire io_input_valid;
input io_jtag_tck;
wire io_jtag_tck;
input io_mainClk;
wire io_mainClk;
output io_output_payload_fragment;
wire io_output_payload_fragment;
output io_output_payload_last;
wire io_output_payload_last;
output io_output_valid;
wire io_output_valid;
wire outputArea_flow_m2sPipe_payload_fragment;
wire outputArea_flow_m2sPipe_payload_last;
wire outputArea_flow_m2sPipe_valid;
wire outputArea_flow_payload_fragment;
wire outputArea_flow_payload_last;
wire outputArea_flow_valid;
wire outputArea_hit;
wire outputArea_target;
input resetCtrl_mainClkReset;
wire resetCtrl_mainClkReset;
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) inputArea_data_fragment_reg /* _1_ */ (
.CLK(io_jtag_tck),
.D(io_input_payload_fragment),
.EN(io_input_valid),
.Q(inputArea_data_fragment)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) inputArea_data_last_reg /* _2_ */ (
.CLK(io_jtag_tck),
.D(io_input_payload_last),
.EN(io_input_valid),
.Q(inputArea_data_last)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) inputArea_target_reg /* _3_ */ (
.CLK(io_jtag_tck),
.D(_0_),
.EN(io_input_valid),
.Q(inputArea_target)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) outputArea_flow_m2sPipe_payload_fragment_reg /* _4_ */ (
.CLK(io_mainClk),
.D(inputArea_data_fragment),
.EN(outputArea_flow_valid),
.Q(outputArea_flow_m2sPipe_payload_fragment)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) outputArea_flow_m2sPipe_payload_last_reg /* _5_ */ (
.CLK(io_mainClk),
.D(inputArea_data_last),
.EN(outputArea_flow_valid),
.Q(outputArea_flow_m2sPipe_payload_last)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _6_ (
.A(inputArea_target),
.Y(_0_)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _7_ (
.A(inputArea_target_buffercc_io_dataOut),
.B(outputArea_hit),
.Y(outputArea_flow_valid)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) outputArea_flow_m2sPipe_valid_reg /* _8_ */ (
.ARST(resetCtrl_mainClkReset),
.CLK(io_mainClk),
.D(outputArea_flow_valid),
.Q(outputArea_flow_m2sPipe_valid)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) outputArea_hit_reg /* _9_ */ (
.CLK(io_mainClk),
.D(inputArea_target_buffercc_io_dataOut),
.Q(outputArea_hit)
);
BufferCC_1 inputArea_target_buffercc (
.io_dataIn(inputArea_target),
.io_dataOut(inputArea_target_buffercc_io_dataOut),
.io_mainClk(io_mainClk),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment;
assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last;
assign io_output_valid = outputArea_flow_m2sPipe_valid;
assign outputArea_flow_payload_fragment = inputArea_data_fragment;
assign outputArea_flow_payload_last = inputArea_data_last;
assign outputArea_target = inputArea_target_buffercc_io_dataOut;
endmodule
module InterruptCtrl(io_inputs, io_clears, io_masks, io_pendings, io_mainClk, resetCtrl_systemReset);
wire [1:0] _0_;
wire [1:0] _1_;
wire [1:0] _2_;
input [1:0] io_clears;
wire [1:0] io_clears;
input [1:0] io_inputs;
wire [1:0] io_inputs;
input io_mainClk;
wire io_mainClk;
input [1:0] io_masks;
wire [1:0] io_masks;
output [1:0] io_pendings;
wire [1:0] io_pendings;
wire [1:0] pendings;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd2)
) _3_ (
.A(pendings),
.B(io_masks),
.Y(io_pendings)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd2)
) _4_ (
.A(pendings),
.B(_2_),
.Y(_1_)
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd2)
) _5_ (
.A(io_clears),
.Y(_2_)
);
\$or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd2)
) _6_ (
.A(_1_),
.B(io_inputs),
.Y(_0_)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(2'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd2)
) _7_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_0_),
.Q(pendings)
);
endmodule
module JtagBridge(io_jtag_tms, io_jtag_tdi, io_jtag_tdo, io_jtag_tck, io_remote_cmd_valid, io_remote_cmd_ready, io_remote_cmd_payload_last, io_remote_cmd_payload_fragment, io_remote_rsp_valid, io_remote_rsp_ready, io_remote_rsp_payload_error, io_remote_rsp_payload_data, io_mainClk, resetCtrl_mainClkReset);
wire [3:0] _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire [15:0] _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire [33:0] _043_;
wire [1:0] _zz_jtag_tap_instructionShift;
wire [3:0] _zz_jtag_tap_isBypass;
wire [3:0] _zz_jtag_tap_isBypass_1;
wire flowCCByToggle_1_io_output_payload_fragment;
wire flowCCByToggle_1_io_output_payload_last;
wire flowCCByToggle_1_io_output_valid;
input io_jtag_tck;
wire io_jtag_tck;
input io_jtag_tdi;
wire io_jtag_tdi;
output io_jtag_tdo;
wire io_jtag_tdo;
input io_jtag_tms;
wire io_jtag_tms;
input io_mainClk;
wire io_mainClk;
output io_remote_cmd_payload_fragment;
wire io_remote_cmd_payload_fragment;
output io_remote_cmd_payload_last;
wire io_remote_cmd_payload_last;
input io_remote_cmd_ready;
wire io_remote_cmd_ready;
output io_remote_cmd_valid;
wire io_remote_cmd_valid;
wire io_remote_rsp_fire;
input [31:0] io_remote_rsp_payload_data;
wire [31:0] io_remote_rsp_payload_data;
input io_remote_rsp_payload_error;
wire io_remote_rsp_payload_error;
output io_remote_rsp_ready;
wire io_remote_rsp_ready;
input io_remote_rsp_valid;
wire io_remote_rsp_valid;
wire jtag_idcodeArea_ctrl_capture;
wire jtag_idcodeArea_ctrl_enable;
wire jtag_idcodeArea_ctrl_shift;
wire jtag_idcodeArea_ctrl_tdi;
wire jtag_idcodeArea_ctrl_tdo;
wire [31:0] jtag_idcodeArea_shifter;
wire jtag_readArea_ctrl_capture;
wire jtag_readArea_ctrl_enable;
wire jtag_readArea_ctrl_shift;
wire jtag_readArea_ctrl_tdi;
wire jtag_readArea_ctrl_tdo;
wire [33:0] jtag_readArea_full_shifter;
wire jtag_tap_bypass;
wire [15:0] jtag_tap_fsm_state;
wire [3:0] jtag_tap_instruction;
wire [3:0] jtag_tap_instructionShift;
wire jtag_tap_isBypass;
wire jtag_tap_tdoDr;
wire jtag_tap_tdoIr;
wire jtag_tap_tdoUnbufferd;
wire jtag_tap_tdoUnbufferd_regNext;
wire jtag_writeArea_ctrl_enable;
wire jtag_writeArea_ctrl_shift;
wire jtag_writeArea_ctrl_tdi;
wire jtag_writeArea_ctrl_tdo;
wire jtag_writeArea_data;
wire jtag_writeArea_source_payload_fragment;
wire jtag_writeArea_source_payload_last;
wire jtag_writeArea_source_valid;
wire jtag_writeArea_valid;
input resetCtrl_mainClkReset;
wire resetCtrl_mainClkReset;
wire system_cmd_payload_fragment;
wire system_cmd_payload_last;
wire system_cmd_toStream_payload_fragment;
wire system_cmd_toStream_payload_last;
wire system_cmd_toStream_ready;
wire system_cmd_toStream_valid;
wire system_cmd_valid;
wire [31:0] system_rsp_payload_data;
wire system_rsp_payload_error;
wire system_rsp_valid;
wire when_JtagTap_l120;
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd32)
) _044_ (
.CLK(io_mainClk),
.D(io_remote_rsp_payload_data),
.EN(io_remote_rsp_valid),
.Q(system_rsp_payload_data)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) system_rsp_payload_error_reg /* _045_ */ (
.CLK(io_mainClk),
.D(io_remote_rsp_payload_error),
.EN(io_remote_rsp_valid),
.Q(system_rsp_payload_error)
);
\$sdffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.SRST_POLARITY(32'd1),
.SRST_VALUE(1'h1),
.WIDTH(32'd1)
) system_rsp_valid_reg /* _046_ */ (
.CLK(io_mainClk),
.D(1'h0),
.EN(flowCCByToggle_1_io_output_valid),
.Q(system_rsp_valid),
.SRST(io_remote_rsp_valid)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd34)
) _047_ (
.CLK(io_jtag_tck),
.D(_043_),
.EN(_040_),
.Q(jtag_readArea_full_shifter)
);
\$sdffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.SRST_POLARITY(32'd1),
.SRST_VALUE(32'd268443647),
.WIDTH(32'd32)
) _048_ (
.CLK(io_jtag_tck),
.D({ io_jtag_tdi, jtag_idcodeArea_shifter[31:1] }),
.EN(_041_),
.Q(jtag_idcodeArea_shifter),
.SRST(jtag_tap_fsm_state[5])
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd4)
) _049_ (
.CLK(io_jtag_tck),
.D(_000_),
.EN(_039_),
.Q(jtag_tap_instructionShift)
);
\$sdffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.SRST_POLARITY(32'd1),
.SRST_VALUE(4'h1),
.WIDTH(32'd4)
) _050_ (
.CLK(io_jtag_tck),
.D(jtag_tap_instructionShift),
.EN(jtag_tap_fsm_state[1]),
.Q(jtag_tap_instruction),
.SRST(jtag_tap_fsm_state[0])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _051_ (
.A({ jtag_tap_fsm_state[4], jtag_tap_fsm_state[0] }),
.Y(_005_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _052_ (
.A({ jtag_tap_fsm_state[14], jtag_tap_fsm_state[10] }),
.Y(_006_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _053_ (
.A({ jtag_tap_fsm_state[14], jtag_tap_fsm_state[12], jtag_tap_fsm_state[2] }),
.Y(_007_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _054_ (
.A({ jtag_tap_fsm_state[10], jtag_tap_fsm_state[6] }),
.Y(_009_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _055_ (
.A({ jtag_tap_fsm_state[15], jtag_tap_fsm_state[8], jtag_tap_fsm_state[1] }),
.Y(_010_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _056_ (
.A({ jtag_tap_fsm_state[12], jtag_tap_fsm_state[2] }),
.Y(_011_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _057_ (
.A({ jtag_tap_fsm_state[11], jtag_tap_fsm_state[3] }),
.Y(_012_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _058_ (
.A({ jtag_tap_fsm_state[13], jtag_tap_fsm_state[5] }),
.Y(_008_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _059_ (
.A({ jtag_tap_fsm_state[7], jtag_tap_fsm_state[3] }),
.Y(_013_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _060_ (
.A(io_jtag_tms),
.B(_005_),
.Y(_014_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _061_ (
.A(io_jtag_tms),
.B(_006_),
.Y(_015_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _062_ (
.A(_033_),
.B(_007_),
.Y(_016_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _063_ (
.A(_034_),
.B(_008_),
.Y(_017_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _064_ (
.A(io_jtag_tms),
.B(jtag_tap_fsm_state[9]),
.Y(_018_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _065_ (
.A(_033_),
.B(jtag_tap_fsm_state[9]),
.Y(_019_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _066_ (
.A(_033_),
.B(_009_),
.Y(_020_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _067_ (
.A(io_jtag_tms),
.B(jtag_tap_fsm_state[11]),
.Y(_021_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _068_ (
.A(_035_),
.B(_010_),
.Y(_022_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _069_ (
.A(_033_),
.B(jtag_tap_fsm_state[0]),
.Y(_023_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _070_ (
.A(_036_),
.B(_010_),
.Y(_024_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _071_ (
.A(io_jtag_tms),
.B(_011_),
.Y(_025_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _072_ (
.A(_033_),
.B(_012_),
.Y(_026_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _073_ (
.A(_033_),
.B(jtag_tap_fsm_state[4]),
.Y(_027_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _074_ (
.A(_037_),
.B(_008_),
.Y(_028_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _075_ (
.A(_033_),
.B(jtag_tap_fsm_state[7]),
.Y(_029_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _076_ (
.A(io_jtag_tms),
.B(jtag_tap_fsm_state[6]),
.Y(_030_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _077_ (
.A(io_jtag_tms),
.B(_013_),
.Y(_031_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _078_ (
.A({ _022_, _023_ }),
.Y(_032_[8])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _079_ (
.A({ _029_, _028_ }),
.Y(_032_[13])
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd16)
) _080_ (
.CLK(io_jtag_tck),
.D({ _031_, _030_, _032_[13], _027_, _026_, _025_, _024_, _032_[8], _021_, _020_, _019_, _018_, _017_, _016_, _015_, _014_ }),
.Q(jtag_tap_fsm_state)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _081_ (
.A({ _011_, io_jtag_tms }),
.B(1'h1),
.Y(_034_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _082_ (
.A({ _011_, _008_, io_jtag_tms }),
.Y(_035_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _083_ (
.A({ _011_, _008_, io_jtag_tms }),
.B(1'h1),
.Y(_036_)
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _084_ (
.A(io_jtag_tms),
.Y(_033_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _085_ (
.A({ _011_, io_jtag_tms }),
.Y(_037_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _086_ (
.A({ jtag_tap_fsm_state[13], jtag_tap_fsm_state[5] }),
.Y(_038_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _087_ (
.A({ _042_, jtag_tap_fsm_state[12] }),
.Y(_039_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _088_ (
.A({ _038_, jtag_readArea_ctrl_enable }),
.Y(_040_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _089_ (
.A({ jtag_tap_fsm_state[13], jtag_idcodeArea_ctrl_enable }),
.Y(_041_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _090_ (
.A({ jtag_tap_fsm_state[13], jtag_tap_fsm_state[2] }),
.Y(_042_)
);
\$eq #(
.A_SIGNED(32'd1),
.A_WIDTH(32'd4),
.B_SIGNED(32'd1),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _091_ (
.A(jtag_tap_instruction),
.B(1'h1),
.Y(jtag_tap_isBypass)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _092_ (
.A(jtag_tap_instruction),
.B(1'h1),
.Y(jtag_idcodeArea_ctrl_enable)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _093_ (
.A(jtag_tap_instruction),
.B(2'h2),
.Y(jtag_writeArea_ctrl_enable)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _094_ (
.A(jtag_tap_instruction),
.B(2'h3),
.Y(jtag_readArea_ctrl_enable)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _095_ (
.A(jtag_writeArea_ctrl_enable),
.B(jtag_tap_fsm_state[13]),
.Y(_001_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _096_ (
.A(_001_),
.Y(jtag_writeArea_source_payload_last)
);
\$dff #(
.CLK_POLARITY(1'h0),
.WIDTH(32'd1)
) jtag_tap_tdoUnbufferd_regNext_reg /* _097_ */ (
.CLK(io_jtag_tck),
.D(jtag_tap_tdoUnbufferd),
.Q(jtag_tap_tdoUnbufferd_regNext)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) jtag_tap_bypass_reg /* _098_ */ (
.CLK(io_jtag_tck),
.D(io_jtag_tdi),
.Q(jtag_tap_bypass)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) jtag_writeArea_valid_reg /* _099_ */ (
.CLK(io_jtag_tck),
.D(_001_),
.Q(jtag_writeArea_valid)
);
\$mux #(
.WIDTH(32'd34)
) _100_ (
.A({ system_rsp_payload_data, system_rsp_payload_error, system_rsp_valid }),
.B({ io_jtag_tdi, jtag_readArea_full_shifter[33:1] }),
.S(jtag_tap_fsm_state[13]),
.Y(_043_)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd4)
) _101_ (
.A(4'hx),
.B({ 4'h1, io_jtag_tdi, jtag_tap_instructionShift[3:1] }),
.S({ jtag_tap_fsm_state[12], _042_ }),
.Y(_000_)
);
\$mux #(
.WIDTH(32'd1)
) _102_ (
.A(_003_),
.B(jtag_readArea_full_shifter[0]),
.S(jtag_readArea_ctrl_enable),
.Y(jtag_tap_tdoDr)
);
\$mux #(
.WIDTH(32'd1)
) _103_ (
.A(_002_),
.B(1'h0),
.S(jtag_writeArea_ctrl_enable),
.Y(_003_)
);
\$mux #(
.WIDTH(32'd1)
) _104_ (
.A(1'h0),
.B(jtag_idcodeArea_shifter[0]),
.S(jtag_idcodeArea_ctrl_enable),
.Y(_002_)
);
\$mux #(
.WIDTH(32'd1)
) _105_ (
.A(jtag_tap_tdoDr),
.B(jtag_tap_bypass),
.S(jtag_tap_isBypass),
.Y(_004_)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd1)
) _106_ (
.A(jtag_tap_bypass),
.B({ jtag_tap_instructionShift[0], _004_ }),
.S({ jtag_tap_fsm_state[2], jtag_tap_fsm_state[13] }),
.Y(jtag_tap_tdoUnbufferd)
);
FlowCCByToggle flowCCByToggle_1 (
.io_input_payload_fragment(jtag_tap_bypass),
.io_input_payload_last(jtag_writeArea_source_payload_last),
.io_input_valid(jtag_writeArea_valid),
.io_jtag_tck(io_jtag_tck),
.io_mainClk(io_mainClk),
.io_output_payload_fragment(flowCCByToggle_1_io_output_payload_fragment),
.io_output_payload_last(flowCCByToggle_1_io_output_payload_last),
.io_output_valid(flowCCByToggle_1_io_output_valid),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
assign { _032_[15:14], _032_[12:9], _032_[7:0] } = { _031_, _030_, _027_, _026_, _025_, _024_, _021_, _020_, _019_, _018_, _017_, _016_, _015_, _014_ };
assign _zz_jtag_tap_instructionShift = 2'h1;
assign _zz_jtag_tap_isBypass = jtag_tap_instruction;
assign _zz_jtag_tap_isBypass_1 = 4'hf;
assign io_jtag_tdo = jtag_tap_tdoUnbufferd_regNext;
assign io_remote_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment;
assign io_remote_cmd_payload_last = flowCCByToggle_1_io_output_payload_last;
assign io_remote_cmd_valid = flowCCByToggle_1_io_output_valid;
assign io_remote_rsp_fire = io_remote_rsp_valid;
assign io_remote_rsp_ready = 1'h1;
assign jtag_idcodeArea_ctrl_capture = jtag_tap_fsm_state[5];
assign jtag_idcodeArea_ctrl_shift = jtag_tap_fsm_state[13];
assign jtag_idcodeArea_ctrl_tdi = io_jtag_tdi;
assign jtag_idcodeArea_ctrl_tdo = jtag_idcodeArea_shifter[0];
assign jtag_readArea_ctrl_capture = jtag_tap_fsm_state[5];
assign jtag_readArea_ctrl_shift = jtag_tap_fsm_state[13];
assign jtag_readArea_ctrl_tdi = io_jtag_tdi;
assign jtag_readArea_ctrl_tdo = jtag_readArea_full_shifter[0];
assign jtag_tap_tdoIr = jtag_tap_instructionShift[0];
assign jtag_writeArea_ctrl_shift = jtag_tap_fsm_state[13];
assign jtag_writeArea_ctrl_tdi = io_jtag_tdi;
assign jtag_writeArea_ctrl_tdo = 1'h0;
assign jtag_writeArea_data = jtag_tap_bypass;
assign jtag_writeArea_source_payload_fragment = jtag_tap_bypass;
assign jtag_writeArea_source_valid = jtag_writeArea_valid;
assign system_cmd_payload_fragment = flowCCByToggle_1_io_output_payload_fragment;
assign system_cmd_payload_last = flowCCByToggle_1_io_output_payload_last;
assign system_cmd_toStream_payload_fragment = flowCCByToggle_1_io_output_payload_fragment;
assign system_cmd_toStream_payload_last = flowCCByToggle_1_io_output_payload_last;
assign system_cmd_toStream_ready = io_remote_cmd_ready;
assign system_cmd_toStream_valid = flowCCByToggle_1_io_output_valid;
assign system_cmd_valid = flowCCByToggle_1_io_output_valid;
assign when_JtagTap_l120 = jtag_tap_fsm_state[0];
endmodule
module Murax(io_asyncReset, io_mainClk, io_jtag_tms, io_jtag_tdi, io_jtag_tdo, io_jtag_tck, io_uart_txd, io_uart_rxd);
wire _00_;
wire _01_;
wire _02_;
wire [5:0] _03_;
wire [5:0] _04_;
wire [5:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _zz_io_bus_cmd_payload_write;
wire _zz_io_pipelinedMemoryBus_cmd_payload_write;
wire [31:0] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data;
wire [5:0] _zz_when_Murax_l188;
wire [31:0] apb3Router_1_io_input_PRDATA;
wire apb3Router_1_io_input_PREADY;
wire apb3Router_1_io_input_PSLVERROR;
wire [19:0] apb3Router_1_io_outputs_0_PADDR;
wire apb3Router_1_io_outputs_0_PENABLE;
wire apb3Router_1_io_outputs_0_PSEL;
wire [31:0] apb3Router_1_io_outputs_0_PWDATA;
wire apb3Router_1_io_outputs_0_PWRITE;
wire [19:0] apb3Router_1_io_outputs_1_PADDR;
wire apb3Router_1_io_outputs_1_PENABLE;
wire apb3Router_1_io_outputs_1_PSEL;
wire [31:0] apb3Router_1_io_outputs_1_PWDATA;
wire apb3Router_1_io_outputs_1_PWRITE;
wire [19:0] apb3Router_1_io_outputs_2_PADDR;
wire apb3Router_1_io_outputs_2_PENABLE;
wire apb3Router_1_io_outputs_2_PSEL;
wire [31:0] apb3Router_1_io_outputs_2_PWDATA;
wire apb3Router_1_io_outputs_2_PWRITE;
wire [31:0] io_apb_decoder_io_input_PRDATA;
wire io_apb_decoder_io_input_PREADY;
wire io_apb_decoder_io_input_PSLVERROR;
wire [19:0] io_apb_decoder_io_output_PADDR;
wire io_apb_decoder_io_output_PENABLE;
wire [2:0] io_apb_decoder_io_output_PSEL;
wire [31:0] io_apb_decoder_io_output_PWDATA;
wire io_apb_decoder_io_output_PWRITE;
input io_asyncReset;
wire io_asyncReset;
wire io_asyncReset_buffercc_io_dataOut;
wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
input io_jtag_tck;
wire io_jtag_tck;
input io_jtag_tdi;
wire io_jtag_tdi;
output io_jtag_tdo;
wire io_jtag_tdo;
input io_jtag_tms;
wire io_jtag_tms;
input io_mainClk;
wire io_mainClk;
input io_uart_rxd;
wire io_uart_rxd;
output io_uart_txd;
wire io_uart_txd;
wire jtagBridge_1_io_jtag_tdo;
wire jtagBridge_1_io_remote_cmd_payload_fragment;
wire jtagBridge_1_io_remote_cmd_payload_last;
wire jtagBridge_1_io_remote_cmd_valid;
wire jtagBridge_1_io_remote_rsp_ready;
wire resetCtrl_mainClkReset;
wire resetCtrl_mainClkResetUnbuffered;
wire [5:0] resetCtrl_systemClkResetCounter;
wire resetCtrl_systemReset;
wire [31:0] systemDebugger_1_io_mem_cmd_payload_address;
wire [31:0] systemDebugger_1_io_mem_cmd_payload_data;
wire [1:0] systemDebugger_1_io_mem_cmd_payload_size;
wire systemDebugger_1_io_mem_cmd_payload_wr;
wire systemDebugger_1_io_mem_cmd_valid;
wire systemDebugger_1_io_remote_cmd_ready;
wire [31:0] systemDebugger_1_io_remote_rsp_payload_data;
wire systemDebugger_1_io_remote_rsp_payload_error;
wire systemDebugger_1_io_remote_rsp_valid;
wire [19:0] system_apbBridge_io_apb_PADDR;
wire system_apbBridge_io_apb_PENABLE;
wire system_apbBridge_io_apb_PSEL;
wire [31:0] system_apbBridge_io_apb_PWDATA;
wire system_apbBridge_io_apb_PWRITE;
wire system_apbBridge_io_pipelinedMemoryBus_cmd_ready;
wire system_apbBridge_io_pipelinedMemoryBus_cmd_valid;
wire [31:0] system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data;
wire system_apbBridge_io_pipelinedMemoryBus_rsp_valid;
wire system_cpu_dBus_cmd_halfPipe_fire;
wire [31:0] system_cpu_dBus_cmd_halfPipe_payload_address;
wire [31:0] system_cpu_dBus_cmd_halfPipe_payload_data;
wire [1:0] system_cpu_dBus_cmd_halfPipe_payload_size;
wire system_cpu_dBus_cmd_halfPipe_payload_wr;
wire system_cpu_dBus_cmd_halfPipe_ready;
wire system_cpu_dBus_cmd_halfPipe_valid;
wire [31:0] system_cpu_dBus_cmd_payload_address;
wire [31:0] system_cpu_dBus_cmd_payload_data;
wire [1:0] system_cpu_dBus_cmd_payload_size;
wire system_cpu_dBus_cmd_payload_wr;
wire [31:0] system_cpu_dBus_cmd_rData_address;
wire [31:0] system_cpu_dBus_cmd_rData_data;
wire [1:0] system_cpu_dBus_cmd_rData_size;
wire system_cpu_dBus_cmd_rData_wr;
wire system_cpu_dBus_cmd_rValid;
wire system_cpu_dBus_cmd_ready;
wire system_cpu_dBus_cmd_valid;
wire system_cpu_debug_bus_cmd_fire;
wire system_cpu_debug_bus_cmd_fire_regNext;
wire [7:0] system_cpu_debug_bus_cmd_payload_address;
wire system_cpu_debug_bus_cmd_ready;
wire [31:0] system_cpu_debug_bus_rsp_data;
wire system_cpu_debug_resetOut;
wire system_cpu_debug_resetOut_regNext;
wire [31:0] system_cpu_iBus_cmd_payload_pc;
wire system_cpu_iBus_cmd_valid;
wire system_externalInterrupt;
wire [3:0] system_gpioACtrl_io_apb_PADDR;
wire [31:0] system_gpioACtrl_io_apb_PRDATA;
wire system_gpioACtrl_io_apb_PREADY;
wire system_gpioACtrl_io_apb_PSLVERROR;
wire [31:0] system_gpioACtrl_io_gpio_write;
wire [31:0] system_gpioACtrl_io_gpio_writeEnable;
wire [31:0] system_gpioACtrl_io_value;
wire system_mainBusArbiter_io_dBus_cmd_ready;
wire [31:0] system_mainBusArbiter_io_dBus_rsp_data;
wire system_mainBusArbiter_io_dBus_rsp_error;
wire system_mainBusArbiter_io_dBus_rsp_ready;
wire system_mainBusArbiter_io_iBus_cmd_ready;
wire system_mainBusArbiter_io_iBus_rsp_payload_error;
wire [31:0] system_mainBusArbiter_io_iBus_rsp_payload_inst;
wire system_mainBusArbiter_io_iBus_rsp_valid;
wire [31:0] system_mainBusArbiter_io_masterBus_cmd_payload_address;
wire [31:0] system_mainBusArbiter_io_masterBus_cmd_payload_data;
wire [3:0] system_mainBusArbiter_io_masterBus_cmd_payload_mask;
wire system_mainBusArbiter_io_masterBus_cmd_payload_write;
wire system_mainBusArbiter_io_masterBus_cmd_valid;
wire system_mainBusDecoder_logic_hits_0;
wire system_mainBusDecoder_logic_hits_1;
wire system_mainBusDecoder_logic_masterPipelined_cmd_fire;
wire system_mainBusDecoder_logic_masterPipelined_cmd_fire_1;
wire [31:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_address;
wire [31:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_data;
wire [3:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask;
wire system_mainBusDecoder_logic_masterPipelined_cmd_payload_write;
wire system_mainBusDecoder_logic_masterPipelined_cmd_ready;
wire system_mainBusDecoder_logic_masterPipelined_cmd_valid;
wire [31:0] system_mainBusDecoder_logic_masterPipelined_rsp_payload_data;
wire system_mainBusDecoder_logic_masterPipelined_rsp_valid;
wire system_mainBusDecoder_logic_noHit;
wire system_mainBusDecoder_logic_rspNoHit;
wire system_mainBusDecoder_logic_rspPending;
wire system_mainBusDecoder_logic_rspSourceId;
wire system_ram_io_bus_cmd_ready;
wire system_ram_io_bus_cmd_valid;
wire [31:0] system_ram_io_bus_rsp_payload_data;
wire system_ram_io_bus_rsp_valid;
wire system_timerInterrupt;
wire [7:0] system_timer_io_apb_PADDR;
wire [31:0] system_timer_io_apb_PRDATA;
wire system_timer_io_apb_PREADY;
wire system_timer_io_apb_PSLVERROR;
wire system_timer_io_interrupt;
wire [4:0] system_uartCtrl_io_apb_PADDR;
wire [31:0] system_uartCtrl_io_apb_PRDATA;
wire system_uartCtrl_io_apb_PREADY;
wire system_uartCtrl_io_interrupt;
wire system_uartCtrl_io_uart_txd;
wire when_MuraxUtiles_l127;
wire when_MuraxUtiles_l133;
wire when_Murax_l188;
wire when_Murax_l192;
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd6),
.Y_WIDTH(32'd6)
) _19_ (
.A(1'h1),
.B(resetCtrl_systemClkResetCounter),
.BI(1'h0),
.CI(1'h0),
.CO(_05_),
.X(_04_),
.Y(_03_)
);
\$sdffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.SRST_POLARITY(32'd1),
.SRST_VALUE(6'h00),
.WIDTH(32'd6)
) _20_ (
.CLK(io_mainClk),
.D(_03_),
.EN(when_Murax_l188),
.Q(resetCtrl_systemClkResetCounter),
.SRST(io_asyncReset_buffercc_io_dataOut)
);
\$sdff #(
.CLK_POLARITY(32'd1),
.SRST_POLARITY(32'd1),
.SRST_VALUE(1'h1),
.WIDTH(32'd1)
) resetCtrl_systemReset_reg /* _21_ */ (
.CLK(io_mainClk),
.D(resetCtrl_mainClkResetUnbuffered),
.Q(resetCtrl_systemReset),
.SRST(system_cpu_debug_resetOut_regNext)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) system_mainBusDecoder_logic_rspPending_reg /* _22_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_02_),
.EN(_06_),
.Q(system_mainBusDecoder_logic_rspPending)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) system_cpu_dBus_cmd_rValid_reg /* _23_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_00_),
.EN(_07_),
.Q(system_cpu_dBus_cmd_rValid)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) system_mainBusDecoder_logic_rspSourceId_reg /* _24_ */ (
.CLK(io_mainClk),
.D(system_mainBusDecoder_logic_hits_1),
.EN(system_mainBusDecoder_logic_masterPipelined_cmd_fire),
.Q(system_mainBusDecoder_logic_rspSourceId)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd2)
) _25_ (
.CLK(io_mainClk),
.D(system_cpu_dBus_cmd_payload_size),
.EN(system_cpu_dBus_cmd_rValid),
.Q(system_cpu_dBus_cmd_rData_size)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd32)
) _26_ (
.CLK(io_mainClk),
.D(system_cpu_dBus_cmd_payload_data),
.EN(system_cpu_dBus_cmd_rValid),
.Q(system_cpu_dBus_cmd_rData_data)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd32)
) _27_ (
.CLK(io_mainClk),
.D(system_cpu_dBus_cmd_payload_address),
.EN(system_cpu_dBus_cmd_rValid),
.Q(system_cpu_dBus_cmd_rData_address)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) system_cpu_dBus_cmd_rData_wr_reg /* _28_ */ (
.CLK(io_mainClk),
.D(system_cpu_dBus_cmd_payload_wr),
.EN(system_cpu_dBus_cmd_rValid),
.Q(system_cpu_dBus_cmd_rData_wr)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _29_ (
.A({ when_MuraxUtiles_l127, system_mainBusDecoder_logic_masterPipelined_rsp_valid }),
.Y(_06_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _30_ (
.A({ system_cpu_dBus_cmd_halfPipe_fire, system_cpu_dBus_cmd_valid }),
.Y(_07_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd19),
.B_SIGNED(32'd0),
.B_WIDTH(32'd19),
.Y_WIDTH(32'd1)
) _31_ (
.A(system_mainBusArbiter_io_masterBus_cmd_payload_address[31:13]),
.B(19'h40000),
.Y(system_mainBusDecoder_logic_hits_0)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd12),
.B_SIGNED(32'd0),
.B_WIDTH(32'd12),
.Y_WIDTH(32'd1)
) _32_ (
.A(system_mainBusArbiter_io_masterBus_cmd_payload_address[31:20]),
.B(12'hf00),
.Y(system_mainBusDecoder_logic_hits_1)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _33_ (
.A(system_cpu_dBus_cmd_rValid),
.B(system_cpu_dBus_cmd_halfPipe_ready),
.Y(system_cpu_dBus_cmd_halfPipe_fire)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _34_ (
.A(systemDebugger_1_io_mem_cmd_valid),
.B(system_cpu_debug_bus_cmd_ready),
.Y(system_cpu_debug_bus_cmd_fire)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _35_ (
.A(system_mainBusArbiter_io_masterBus_cmd_valid),
.B(system_mainBusDecoder_logic_hits_0),
.Y(_08_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _36_ (
.A(system_mainBusArbiter_io_masterBus_cmd_valid),
.B(system_mainBusDecoder_logic_hits_1),
.Y(_09_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _37_ (
.A(system_mainBusDecoder_logic_hits_0),
.B(system_ram_io_bus_cmd_ready),
.Y(_10_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _38_ (
.A(system_mainBusDecoder_logic_hits_1),
.B(system_apbBridge_io_pipelinedMemoryBus_cmd_ready),
.Y(_11_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _39_ (
.A(system_mainBusArbiter_io_masterBus_cmd_valid),
.B(system_mainBusDecoder_logic_masterPipelined_cmd_ready),
.Y(system_mainBusDecoder_logic_masterPipelined_cmd_fire)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _40_ (
.A(system_mainBusDecoder_logic_masterPipelined_cmd_fire),
.B(_13_),
.Y(when_MuraxUtiles_l127)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _41_ (
.A(system_mainBusDecoder_logic_rspPending),
.B(system_mainBusDecoder_logic_rspNoHit),
.Y(_12_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _42_ (
.A(system_mainBusDecoder_logic_rspPending),
.B(_14_),
.Y(when_MuraxUtiles_l133)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _43_ (
.A(system_cpu_dBus_cmd_rValid),
.Y(system_cpu_dBus_cmd_ready)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _44_ (
.A(_16_),
.Y(system_mainBusDecoder_logic_noHit)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _45_ (
.A(_zz_io_bus_cmd_payload_write),
.Y(_13_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _46_ (
.A(system_mainBusDecoder_logic_masterPipelined_rsp_valid),
.Y(_14_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _47_ (
.A(_17_),
.B(system_mainBusDecoder_logic_noHit),
.Y(_15_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _48_ (
.A(_18_),
.B(_12_),
.Y(system_mainBusDecoder_logic_masterPipelined_rsp_valid)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd6),
.B_SIGNED(32'd0),
.B_WIDTH(32'd6),
.Y_WIDTH(32'd1)
) _49_ (
.A(resetCtrl_systemClkResetCounter),
.B(6'h3f),
.Y(when_Murax_l188)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _50_ (
.A({ system_mainBusDecoder_logic_hits_1, system_mainBusDecoder_logic_hits_0 }),
.Y(_16_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _51_ (
.A({ _11_, _10_ }),
.Y(_17_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _52_ (
.A({ system_apbBridge_io_pipelinedMemoryBus_rsp_valid, system_ram_io_bus_rsp_valid }),
.Y(_18_)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) system_cpu_debug_bus_cmd_fire_regNext_reg /* _53_ */ (
.ARST(resetCtrl_mainClkReset),
.CLK(io_mainClk),
.D(system_cpu_debug_bus_cmd_fire),
.Q(system_cpu_debug_bus_cmd_fire_regNext)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) system_cpu_debug_resetOut_regNext_reg /* _54_ */ (
.CLK(io_mainClk),
.D(system_cpu_debug_resetOut),
.Q(system_cpu_debug_resetOut_regNext)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) system_mainBusDecoder_logic_rspNoHit_reg /* _55_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_01_),
.Q(system_mainBusDecoder_logic_rspNoHit)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) resetCtrl_mainClkReset_reg /* _56_ */ (
.CLK(io_mainClk),
.D(resetCtrl_mainClkResetUnbuffered),
.Q(resetCtrl_mainClkReset)
);
\$mux #(
.WIDTH(32'd1)
) _57_ (
.A(1'h1),
.B(1'h0),
.S(_16_),
.Y(_01_)
);
\$mux #(
.WIDTH(32'd1)
) _58_ (
.A(1'h0),
.B(1'h1),
.S(when_MuraxUtiles_l127),
.Y(_02_)
);
\$mux #(
.WIDTH(32'd1)
) _59_ (
.A(1'h1),
.B(1'h0),
.S(system_cpu_dBus_cmd_halfPipe_fire),
.Y(_00_)
);
\$mux #(
.WIDTH(32'd1)
) _60_ (
.A(_15_),
.B(1'h0),
.S(when_MuraxUtiles_l133),
.Y(system_mainBusDecoder_logic_masterPipelined_cmd_ready)
);
\$mux #(
.WIDTH(32'd1)
) _61_ (
.A(_09_),
.B(1'h0),
.S(when_MuraxUtiles_l133),
.Y(system_apbBridge_io_pipelinedMemoryBus_cmd_valid)
);
\$mux #(
.WIDTH(32'd1)
) _62_ (
.A(_08_),
.B(1'h0),
.S(when_MuraxUtiles_l133),
.Y(system_ram_io_bus_cmd_valid)
);
\$mux #(
.WIDTH(32'd1)
) _63_ (
.A(1'h0),
.B(1'h1),
.S(system_uartCtrl_io_interrupt),
.Y(system_externalInterrupt)
);
\$mux #(
.WIDTH(32'd1)
) _64_ (
.A(1'h0),
.B(1'h1),
.S(system_timer_io_interrupt),
.Y(system_timerInterrupt)
);
\$mux #(
.WIDTH(32'd1)
) _65_ (
.A(1'h0),
.B(1'h1),
.S(when_Murax_l188),
.Y(resetCtrl_mainClkResetUnbuffered)
);
\$mux #(
.WIDTH(32'd32)
) _66_ (
.A(system_ram_io_bus_rsp_payload_data),
.B(system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data),
.S(system_mainBusDecoder_logic_rspSourceId),
.Y(system_mainBusDecoder_logic_masterPipelined_rsp_payload_data)
);
Apb3Router apb3Router_1 (
.io_input_PADDR(io_apb_decoder_io_output_PADDR),
.io_input_PENABLE(io_apb_decoder_io_output_PENABLE),
.io_input_PRDATA(apb3Router_1_io_input_PRDATA),
.io_input_PREADY(apb3Router_1_io_input_PREADY),
.io_input_PSEL(io_apb_decoder_io_output_PSEL),
.io_input_PSLVERROR(apb3Router_1_io_input_PSLVERROR),
.io_input_PWDATA(io_apb_decoder_io_output_PWDATA),
.io_input_PWRITE(io_apb_decoder_io_output_PWRITE),
.io_mainClk(io_mainClk),
.io_outputs_0_PADDR(apb3Router_1_io_outputs_0_PADDR),
.io_outputs_0_PENABLE(apb3Router_1_io_outputs_0_PENABLE),
.io_outputs_0_PRDATA(system_gpioACtrl_io_apb_PRDATA),
.io_outputs_0_PREADY(system_gpioACtrl_io_apb_PREADY),
.io_outputs_0_PSEL(apb3Router_1_io_outputs_0_PSEL),
.io_outputs_0_PSLVERROR(system_gpioACtrl_io_apb_PSLVERROR),
.io_outputs_0_PWDATA(apb3Router_1_io_outputs_0_PWDATA),
.io_outputs_0_PWRITE(apb3Router_1_io_outputs_0_PWRITE),
.io_outputs_1_PADDR(apb3Router_1_io_outputs_1_PADDR),
.io_outputs_1_PENABLE(apb3Router_1_io_outputs_1_PENABLE),
.io_outputs_1_PRDATA(system_uartCtrl_io_apb_PRDATA),
.io_outputs_1_PREADY(system_uartCtrl_io_apb_PREADY),
.io_outputs_1_PSEL(apb3Router_1_io_outputs_1_PSEL),
.io_outputs_1_PSLVERROR(1'h0),
.io_outputs_1_PWDATA(apb3Router_1_io_outputs_1_PWDATA),
.io_outputs_1_PWRITE(apb3Router_1_io_outputs_1_PWRITE),
.io_outputs_2_PADDR(apb3Router_1_io_outputs_2_PADDR),
.io_outputs_2_PENABLE(apb3Router_1_io_outputs_2_PENABLE),
.io_outputs_2_PRDATA(system_timer_io_apb_PRDATA),
.io_outputs_2_PREADY(system_timer_io_apb_PREADY),
.io_outputs_2_PSEL(apb3Router_1_io_outputs_2_PSEL),
.io_outputs_2_PSLVERROR(system_timer_io_apb_PSLVERROR),
.io_outputs_2_PWDATA(apb3Router_1_io_outputs_2_PWDATA),
.io_outputs_2_PWRITE(apb3Router_1_io_outputs_2_PWRITE),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Apb3Decoder io_apb_decoder (
.io_input_PADDR(system_apbBridge_io_apb_PADDR),
.io_input_PENABLE(system_apbBridge_io_apb_PENABLE),
.io_input_PRDATA(io_apb_decoder_io_input_PRDATA),
.io_input_PREADY(io_apb_decoder_io_input_PREADY),
.io_input_PSEL(system_apbBridge_io_apb_PSEL),
.io_input_PSLVERROR(io_apb_decoder_io_input_PSLVERROR),
.io_input_PWDATA(system_apbBridge_io_apb_PWDATA),
.io_input_PWRITE(system_apbBridge_io_apb_PWRITE),
.io_output_PADDR(io_apb_decoder_io_output_PADDR),
.io_output_PENABLE(io_apb_decoder_io_output_PENABLE),
.io_output_PRDATA(apb3Router_1_io_input_PRDATA),
.io_output_PREADY(apb3Router_1_io_input_PREADY),
.io_output_PSEL(io_apb_decoder_io_output_PSEL),
.io_output_PSLVERROR(apb3Router_1_io_input_PSLVERROR),
.io_output_PWDATA(io_apb_decoder_io_output_PWDATA),
.io_output_PWRITE(io_apb_decoder_io_output_PWRITE)
);
BufferCC_3 io_asyncReset_buffercc (
.io_dataIn(io_asyncReset),
.io_dataOut(io_asyncReset_buffercc_io_dataOut),
.io_mainClk(io_mainClk)
);
JtagBridge jtagBridge_1 (
.io_jtag_tck(io_jtag_tck),
.io_jtag_tdi(io_jtag_tdi),
.io_jtag_tdo(jtagBridge_1_io_jtag_tdo),
.io_jtag_tms(io_jtag_tms),
.io_mainClk(io_mainClk),
.io_remote_cmd_payload_fragment(jtagBridge_1_io_remote_cmd_payload_fragment),
.io_remote_cmd_payload_last(jtagBridge_1_io_remote_cmd_payload_last),
.io_remote_cmd_ready(systemDebugger_1_io_remote_cmd_ready),
.io_remote_cmd_valid(jtagBridge_1_io_remote_cmd_valid),
.io_remote_rsp_payload_data(systemDebugger_1_io_remote_rsp_payload_data),
.io_remote_rsp_payload_error(systemDebugger_1_io_remote_rsp_payload_error),
.io_remote_rsp_ready(jtagBridge_1_io_remote_rsp_ready),
.io_remote_rsp_valid(systemDebugger_1_io_remote_rsp_valid),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
SystemDebugger systemDebugger_1 (
.io_mainClk(io_mainClk),
.io_mem_cmd_payload_address(systemDebugger_1_io_mem_cmd_payload_address),
.io_mem_cmd_payload_data(systemDebugger_1_io_mem_cmd_payload_data),
.io_mem_cmd_payload_size(systemDebugger_1_io_mem_cmd_payload_size),
.io_mem_cmd_payload_wr(systemDebugger_1_io_mem_cmd_payload_wr),
.io_mem_cmd_ready(system_cpu_debug_bus_cmd_ready),
.io_mem_cmd_valid(systemDebugger_1_io_mem_cmd_valid),
.io_mem_rsp_payload(system_cpu_debug_bus_rsp_data),
.io_mem_rsp_valid(system_cpu_debug_bus_cmd_fire_regNext),
.io_remote_cmd_payload_fragment(jtagBridge_1_io_remote_cmd_payload_fragment),
.io_remote_cmd_payload_last(jtagBridge_1_io_remote_cmd_payload_last),
.io_remote_cmd_ready(systemDebugger_1_io_remote_cmd_ready),
.io_remote_cmd_valid(jtagBridge_1_io_remote_cmd_valid),
.io_remote_rsp_payload_data(systemDebugger_1_io_remote_rsp_payload_data),
.io_remote_rsp_payload_error(systemDebugger_1_io_remote_rsp_payload_error),
.io_remote_rsp_ready(jtagBridge_1_io_remote_rsp_ready),
.io_remote_rsp_valid(systemDebugger_1_io_remote_rsp_valid),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
PipelinedMemoryBusToApbBridge system_apbBridge (
.io_apb_PADDR(system_apbBridge_io_apb_PADDR),
.io_apb_PENABLE(system_apbBridge_io_apb_PENABLE),
.io_apb_PRDATA(io_apb_decoder_io_input_PRDATA),
.io_apb_PREADY(io_apb_decoder_io_input_PREADY),
.io_apb_PSEL(system_apbBridge_io_apb_PSEL),
.io_apb_PSLVERROR(io_apb_decoder_io_input_PSLVERROR),
.io_apb_PWDATA(system_apbBridge_io_apb_PWDATA),
.io_apb_PWRITE(system_apbBridge_io_apb_PWRITE),
.io_mainClk(io_mainClk),
.io_pipelinedMemoryBus_cmd_payload_address(system_mainBusArbiter_io_masterBus_cmd_payload_address),
.io_pipelinedMemoryBus_cmd_payload_data(system_mainBusArbiter_io_masterBus_cmd_payload_data),
.io_pipelinedMemoryBus_cmd_payload_mask(system_mainBusArbiter_io_masterBus_cmd_payload_mask),
.io_pipelinedMemoryBus_cmd_payload_write(_zz_io_bus_cmd_payload_write),
.io_pipelinedMemoryBus_cmd_ready(system_apbBridge_io_pipelinedMemoryBus_cmd_ready),
.io_pipelinedMemoryBus_cmd_valid(system_apbBridge_io_pipelinedMemoryBus_cmd_valid),
.io_pipelinedMemoryBus_rsp_payload_data(system_apbBridge_io_pipelinedMemoryBus_rsp_payload_data),
.io_pipelinedMemoryBus_rsp_valid(system_apbBridge_io_pipelinedMemoryBus_rsp_valid),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
VexRiscv system_cpu (
.dBus_cmd_payload_address(system_cpu_dBus_cmd_payload_address),
.dBus_cmd_payload_data(system_cpu_dBus_cmd_payload_data),
.dBus_cmd_payload_size(system_cpu_dBus_cmd_payload_size),
.dBus_cmd_payload_wr(system_cpu_dBus_cmd_payload_wr),
.dBus_cmd_ready(system_cpu_dBus_cmd_ready),
.dBus_cmd_valid(system_cpu_dBus_cmd_valid),
.dBus_rsp_data(system_mainBusArbiter_io_dBus_rsp_data),
.dBus_rsp_error(system_mainBusArbiter_io_dBus_rsp_error),
.dBus_rsp_ready(system_mainBusArbiter_io_dBus_rsp_ready),
.debug_bus_cmd_payload_address(systemDebugger_1_io_mem_cmd_payload_address[7:0]),
.debug_bus_cmd_payload_data(systemDebugger_1_io_mem_cmd_payload_data),
.debug_bus_cmd_payload_wr(systemDebugger_1_io_mem_cmd_payload_wr),
.debug_bus_cmd_ready(system_cpu_debug_bus_cmd_ready),
.debug_bus_cmd_valid(systemDebugger_1_io_mem_cmd_valid),
.debug_bus_rsp_data(system_cpu_debug_bus_rsp_data),
.debug_resetOut(system_cpu_debug_resetOut),
.externalInterrupt(system_externalInterrupt),
.iBus_cmd_payload_pc(system_cpu_iBus_cmd_payload_pc),
.iBus_cmd_ready(system_mainBusArbiter_io_iBus_cmd_ready),
.iBus_cmd_valid(system_cpu_iBus_cmd_valid),
.iBus_rsp_payload_error(system_mainBusArbiter_io_iBus_rsp_payload_error),
.iBus_rsp_payload_inst(system_mainBusArbiter_io_iBus_rsp_payload_inst),
.iBus_rsp_valid(system_mainBusArbiter_io_iBus_rsp_valid),
.io_mainClk(io_mainClk),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset),
.resetCtrl_systemReset(resetCtrl_systemReset),
.softwareInterrupt(1'h0),
.timerInterrupt(system_timerInterrupt)
);
Apb3Gpio system_gpioACtrl (
.io_apb_PADDR(apb3Router_1_io_outputs_0_PADDR[3:0]),
.io_apb_PENABLE(apb3Router_1_io_outputs_0_PENABLE),
.io_apb_PRDATA(system_gpioACtrl_io_apb_PRDATA),
.io_apb_PREADY(system_gpioACtrl_io_apb_PREADY),
.io_apb_PSEL(apb3Router_1_io_outputs_0_PSEL),
.io_apb_PSLVERROR(system_gpioACtrl_io_apb_PSLVERROR),
.io_apb_PWDATA(apb3Router_1_io_outputs_0_PWDATA),
.io_apb_PWRITE(apb3Router_1_io_outputs_0_PWRITE),
.io_gpio_read(io_gpioA_read),
.io_gpio_write(system_gpioACtrl_io_gpio_write),
.io_gpio_writeEnable(system_gpioACtrl_io_gpio_writeEnable),
.io_mainClk(io_mainClk),
.io_value(system_gpioACtrl_io_value),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
MuraxMasterArbiter system_mainBusArbiter (
.io_dBus_cmd_payload_address(system_cpu_dBus_cmd_rData_address),
.io_dBus_cmd_payload_data(system_cpu_dBus_cmd_rData_data),
.io_dBus_cmd_payload_size(system_cpu_dBus_cmd_rData_size),
.io_dBus_cmd_payload_wr(system_cpu_dBus_cmd_rData_wr),
.io_dBus_cmd_ready(system_cpu_dBus_cmd_halfPipe_ready),
.io_dBus_cmd_valid(system_cpu_dBus_cmd_rValid),
.io_dBus_rsp_data(system_mainBusArbiter_io_dBus_rsp_data),
.io_dBus_rsp_error(system_mainBusArbiter_io_dBus_rsp_error),
.io_dBus_rsp_ready(system_mainBusArbiter_io_dBus_rsp_ready),
.io_iBus_cmd_payload_pc(system_cpu_iBus_cmd_payload_pc),
.io_iBus_cmd_ready(system_mainBusArbiter_io_iBus_cmd_ready),
.io_iBus_cmd_valid(system_cpu_iBus_cmd_valid),
.io_iBus_rsp_payload_error(system_mainBusArbiter_io_iBus_rsp_payload_error),
.io_iBus_rsp_payload_inst(system_mainBusArbiter_io_iBus_rsp_payload_inst),
.io_iBus_rsp_valid(system_mainBusArbiter_io_iBus_rsp_valid),
.io_mainClk(io_mainClk),
.io_masterBus_cmd_payload_address(system_mainBusArbiter_io_masterBus_cmd_payload_address),
.io_masterBus_cmd_payload_data(system_mainBusArbiter_io_masterBus_cmd_payload_data),
.io_masterBus_cmd_payload_mask(system_mainBusArbiter_io_masterBus_cmd_payload_mask),
.io_masterBus_cmd_payload_write(_zz_io_bus_cmd_payload_write),
.io_masterBus_cmd_ready(system_mainBusDecoder_logic_masterPipelined_cmd_ready),
.io_masterBus_cmd_valid(system_mainBusArbiter_io_masterBus_cmd_valid),
.io_masterBus_rsp_payload_data(system_mainBusDecoder_logic_masterPipelined_rsp_payload_data),
.io_masterBus_rsp_valid(system_mainBusDecoder_logic_masterPipelined_rsp_valid),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
MuraxPipelinedMemoryBusRam system_ram (
.io_bus_cmd_payload_address(system_mainBusArbiter_io_masterBus_cmd_payload_address),
.io_bus_cmd_payload_data(system_mainBusArbiter_io_masterBus_cmd_payload_data),
.io_bus_cmd_payload_mask(system_mainBusArbiter_io_masterBus_cmd_payload_mask),
.io_bus_cmd_payload_write(_zz_io_bus_cmd_payload_write),
.io_bus_cmd_ready(system_ram_io_bus_cmd_ready),
.io_bus_cmd_valid(system_ram_io_bus_cmd_valid),
.io_bus_rsp_payload_data(system_ram_io_bus_rsp_payload_data),
.io_bus_rsp_valid(system_ram_io_bus_rsp_valid),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
MuraxApb3Timer system_timer (
.io_apb_PADDR(apb3Router_1_io_outputs_2_PADDR[7:0]),
.io_apb_PENABLE(apb3Router_1_io_outputs_2_PENABLE),
.io_apb_PRDATA(system_timer_io_apb_PRDATA),
.io_apb_PREADY(system_timer_io_apb_PREADY),
.io_apb_PSEL(apb3Router_1_io_outputs_2_PSEL),
.io_apb_PSLVERROR(system_timer_io_apb_PSLVERROR),
.io_apb_PWDATA(apb3Router_1_io_outputs_2_PWDATA),
.io_apb_PWRITE(apb3Router_1_io_outputs_2_PWRITE),
.io_interrupt(system_timer_io_interrupt),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Apb3UartCtrl system_uartCtrl (
.io_apb_PADDR(apb3Router_1_io_outputs_1_PADDR[4:0]),
.io_apb_PENABLE(apb3Router_1_io_outputs_1_PENABLE),
.io_apb_PRDATA(system_uartCtrl_io_apb_PRDATA),
.io_apb_PREADY(system_uartCtrl_io_apb_PREADY),
.io_apb_PSEL(apb3Router_1_io_outputs_1_PSEL),
.io_apb_PWDATA(apb3Router_1_io_outputs_1_PWDATA),
.io_apb_PWRITE(apb3Router_1_io_outputs_1_PWRITE),
.io_interrupt(system_uartCtrl_io_interrupt),
.io_mainClk(io_mainClk),
.io_uart_rxd(io_uart_rxd),
.io_uart_txd(system_uartCtrl_io_uart_txd),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign _zz_io_pipelinedMemoryBus_cmd_payload_write = _zz_io_bus_cmd_payload_write;
assign _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data = system_mainBusDecoder_logic_masterPipelined_rsp_payload_data;
assign _zz_when_Murax_l188 = 6'h3f;
assign io_gpioA_write = system_gpioACtrl_io_gpio_write;
assign io_gpioA_writeEnable = system_gpioACtrl_io_gpio_writeEnable;
assign io_jtag_tdo = jtagBridge_1_io_jtag_tdo;
assign io_uart_txd = system_uartCtrl_io_uart_txd;
assign system_cpu_dBus_cmd_halfPipe_payload_address = system_cpu_dBus_cmd_rData_address;
assign system_cpu_dBus_cmd_halfPipe_payload_data = system_cpu_dBus_cmd_rData_data;
assign system_cpu_dBus_cmd_halfPipe_payload_size = system_cpu_dBus_cmd_rData_size;
assign system_cpu_dBus_cmd_halfPipe_payload_wr = system_cpu_dBus_cmd_rData_wr;
assign system_cpu_dBus_cmd_halfPipe_valid = system_cpu_dBus_cmd_rValid;
assign system_cpu_debug_bus_cmd_payload_address = systemDebugger_1_io_mem_cmd_payload_address[7:0];
assign system_gpioACtrl_io_apb_PADDR = apb3Router_1_io_outputs_0_PADDR[3:0];
assign system_mainBusArbiter_io_dBus_cmd_ready = system_cpu_dBus_cmd_halfPipe_ready;
assign system_mainBusArbiter_io_masterBus_cmd_payload_write = _zz_io_bus_cmd_payload_write;
assign system_mainBusDecoder_logic_masterPipelined_cmd_fire_1 = system_mainBusDecoder_logic_masterPipelined_cmd_fire;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_address = system_mainBusArbiter_io_masterBus_cmd_payload_address;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_data = system_mainBusArbiter_io_masterBus_cmd_payload_data;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask = system_mainBusArbiter_io_masterBus_cmd_payload_mask;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_write = _zz_io_bus_cmd_payload_write;
assign system_mainBusDecoder_logic_masterPipelined_cmd_valid = system_mainBusArbiter_io_masterBus_cmd_valid;
assign system_timer_io_apb_PADDR = apb3Router_1_io_outputs_2_PADDR[7:0];
assign system_uartCtrl_io_apb_PADDR = apb3Router_1_io_outputs_1_PADDR[4:0];
assign when_Murax_l192 = io_asyncReset_buffercc_io_dataOut;
endmodule
module MuraxApb3Timer(io_apb_PADDR, io_apb_PSEL, io_apb_PENABLE, io_apb_PREADY, io_apb_PWRITE, io_apb_PWDATA, io_apb_PRDATA, io_apb_PSLVERROR, io_interrupt, io_mainClk, resetCtrl_systemReset);
wire _00_;
wire _01_;
wire _02_;
wire [1:0] _03_;
wire _04_;
wire [1:0] _05_;
wire _06_;
wire [1:0] _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _zz_io_clear;
wire [15:0] _zz_io_limit;
wire busCtrl_doWrite;
wire [1:0] interruptCtrl_1_io_clears;
wire [1:0] interruptCtrl_1_io_inputs;
wire [1:0] interruptCtrl_1_io_masks_driver;
wire [1:0] interruptCtrl_1_io_pendings;
input [7:0] io_apb_PADDR;
wire [7:0] io_apb_PADDR;
input io_apb_PENABLE;
wire io_apb_PENABLE;
output [31:0] io_apb_PRDATA;
wire [31:0] io_apb_PRDATA;
output io_apb_PREADY;
wire io_apb_PREADY;
input io_apb_PSEL;
wire io_apb_PSEL;
output io_apb_PSLVERROR;
wire io_apb_PSLVERROR;
input [31:0] io_apb_PWDATA;
wire [31:0] io_apb_PWDATA;
input io_apb_PWRITE;
wire io_apb_PWRITE;
output io_interrupt;
wire io_interrupt;
input io_mainClk;
wire io_mainClk;
wire prescaler_1_io_overflow;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
wire timerABridge_busClearing;
wire timerABridge_clearsEnable;
wire [1:0] timerABridge_ticksEnable;
wire timerA_io_clear;
wire timerA_io_full;
wire [15:0] timerA_io_limit_driver;
wire timerA_io_tick;
wire [15:0] timerA_io_value;
wire timerBBridge_busClearing;
wire timerBBridge_clearsEnable;
wire [1:0] timerBBridge_ticksEnable;
wire timerB_io_clear;
wire timerB_io_full;
wire [15:0] timerB_io_limit_driver;
wire timerB_io_tick;
wire [15:0] timerB_io_value;
wire when_Timer_l40;
wire when_Timer_l40_1;
wire when_Timer_l44;
wire when_Timer_l44_1;
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _24_ (
.A(timerABridge_clearsEnable),
.B(timerA_io_full),
.Y(_04_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _25_ (
.A(timerBBridge_clearsEnable),
.B(timerB_io_full),
.Y(_06_)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(2'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd2)
) _26_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_apb_PWDATA[1:0]),
.EN(_08_),
.Q(interruptCtrl_1_io_masks_driver)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) timerBBridge_clearsEnable_reg /* _27_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_apb_PWDATA[16]),
.EN(_09_),
.Q(timerBBridge_clearsEnable)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(2'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd2)
) _28_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_apb_PWDATA[1:0]),
.EN(_09_),
.Q(timerBBridge_ticksEnable)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) timerABridge_clearsEnable_reg /* _29_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_apb_PWDATA[16]),
.EN(_10_),
.Q(timerABridge_clearsEnable)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(2'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd2)
) _30_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_apb_PWDATA[1:0]),
.EN(_10_),
.Q(timerABridge_ticksEnable)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd16)
) _31_ (
.CLK(io_mainClk),
.D(io_apb_PWDATA[15:0]),
.EN(_11_),
.Q(timerB_io_limit_driver)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd16)
) _32_ (
.CLK(io_mainClk),
.D(io_apb_PWDATA[15:0]),
.EN(_12_),
.Q(timerA_io_limit_driver)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd16)
) _33_ (
.CLK(io_mainClk),
.D(io_apb_PWDATA[15:0]),
.EN(_13_),
.Q(_zz_io_limit)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _34_ (
.A({ _18_, busCtrl_doWrite }),
.Y(_08_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _35_ (
.A({ _19_, busCtrl_doWrite }),
.Y(_09_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _36_ (
.A({ _20_, busCtrl_doWrite }),
.Y(_10_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _37_ (
.A({ _15_, busCtrl_doWrite }),
.Y(_11_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _38_ (
.A({ _16_, busCtrl_doWrite }),
.Y(_12_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _39_ (
.A({ _17_, busCtrl_doWrite }),
.Y(_13_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _40_ (
.A(timerABridge_ticksEnable[1]),
.B(prescaler_1_io_overflow),
.Y(_05_[1])
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _41_ (
.A(timerBBridge_ticksEnable[1]),
.B(prescaler_1_io_overflow),
.Y(_07_[1])
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _42_ (
.A(io_apb_PSEL),
.B(io_apb_PENABLE),
.Y(_14_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _43_ (
.A(_14_),
.B(io_apb_PWRITE),
.Y(busCtrl_doWrite)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _44_ (
.A(_04_),
.B(timerABridge_busClearing),
.Y(timerA_io_clear)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _45_ (
.A(_06_),
.B(timerBBridge_busClearing),
.Y(timerB_io_clear)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd7),
.Y_WIDTH(32'd1)
) _46_ (
.A(io_apb_PADDR),
.B(7'h54),
.Y(_15_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd7),
.Y_WIDTH(32'd1)
) _47_ (
.A(io_apb_PADDR),
.B(7'h44),
.Y(_16_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.Y_WIDTH(32'd1)
) _48_ (
.A(io_apb_PADDR),
.Y(_17_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _49_ (
.A(io_apb_PADDR),
.B(5'h14),
.Y(_18_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd7),
.Y_WIDTH(32'd1)
) _50_ (
.A(io_apb_PADDR),
.B(7'h50),
.Y(_19_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd7),
.Y_WIDTH(32'd1)
) _51_ (
.A(io_apb_PADDR),
.B(7'h40),
.Y(_20_)
);
\$mux #(
.WIDTH(32'd2)
) _52_ (
.A(2'h0),
.B(io_apb_PWDATA[1:0]),
.S(busCtrl_doWrite),
.Y(_03_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _53_ (
.A(io_apb_PADDR),
.B(5'h10),
.Y(_21_)
);
\$mux #(
.WIDTH(32'd2)
) _54_ (
.A(2'h0),
.B(_03_),
.S(_21_),
.Y(interruptCtrl_1_io_clears)
);
\$mux #(
.WIDTH(32'd1)
) _55_ (
.A(1'h0),
.B(1'h1),
.S(busCtrl_doWrite),
.Y(_02_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd7),
.Y_WIDTH(32'd1)
) _56_ (
.A(io_apb_PADDR),
.B(7'h58),
.Y(_22_)
);
\$mux #(
.WIDTH(32'd1)
) _57_ (
.A(1'h0),
.B(_02_),
.S(_22_),
.Y(when_Timer_l44_1)
);
\$mux #(
.WIDTH(32'd1)
) _58_ (
.A(1'h0),
.B(_02_),
.S(_15_),
.Y(when_Timer_l40_1)
);
\$mux #(
.WIDTH(32'd1)
) _59_ (
.A(_01_),
.B(1'h1),
.S(when_Timer_l44_1),
.Y(timerBBridge_busClearing)
);
\$mux #(
.WIDTH(32'd1)
) _60_ (
.A(1'h0),
.B(1'h1),
.S(when_Timer_l40_1),
.Y(_01_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd7),
.Y_WIDTH(32'd1)
) _61_ (
.A(io_apb_PADDR),
.B(7'h48),
.Y(_23_)
);
\$mux #(
.WIDTH(32'd1)
) _62_ (
.A(1'h0),
.B(_02_),
.S(_23_),
.Y(when_Timer_l44)
);
\$mux #(
.WIDTH(32'd1)
) _63_ (
.A(1'h0),
.B(_02_),
.S(_16_),
.Y(when_Timer_l40)
);
\$mux #(
.WIDTH(32'd1)
) _64_ (
.A(_00_),
.B(1'h1),
.S(when_Timer_l44),
.Y(timerABridge_busClearing)
);
\$mux #(
.WIDTH(32'd1)
) _65_ (
.A(1'h0),
.B(1'h1),
.S(when_Timer_l40),
.Y(_00_)
);
\$mux #(
.WIDTH(32'd1)
) _66_ (
.A(1'h0),
.B(_02_),
.S(_17_),
.Y(_zz_io_clear)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd1)
) _67_ (
.A(1'h0),
.B({ timerABridge_clearsEnable, timerBBridge_clearsEnable }),
.S({ _20_, _19_ }),
.Y(io_apb_PRDATA[16])
);
\$pmux #(
.S_WIDTH(32'd5),
.WIDTH(32'd14)
) _68_ (
.A(14'h0000),
.B({ _zz_io_limit[15:2], timerA_io_limit_driver[15:2], timerA_io_value[15:2], timerB_io_limit_driver[15:2], timerB_io_value[15:2] }),
.S({ _17_, _16_, _23_, _15_, _22_ }),
.Y(io_apb_PRDATA[15:2])
);
\$pmux #(
.S_WIDTH(32'd9),
.WIDTH(32'd2)
) _69_ (
.A(2'h0),
.B({ _zz_io_limit[1:0], timerABridge_ticksEnable, timerA_io_limit_driver[1:0], timerA_io_value[1:0], timerBBridge_ticksEnable, timerB_io_limit_driver[1:0], timerB_io_value[1:0], interruptCtrl_1_io_pendings, interruptCtrl_1_io_masks_driver }),
.S({ _17_, _20_, _16_, _23_, _19_, _15_, _22_, _21_, _18_ }),
.Y(io_apb_PRDATA[1:0])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _70_ (
.A({ _05_[1], timerABridge_ticksEnable[0] }),
.Y(timerA_io_tick)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _71_ (
.A({ _07_[1], timerBBridge_ticksEnable[0] }),
.Y(timerB_io_tick)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _72_ (
.A(interruptCtrl_1_io_pendings),
.Y(io_interrupt)
);
InterruptCtrl interruptCtrl_1 (
.io_clears(interruptCtrl_1_io_clears),
.io_inputs({ timerB_io_full, timerA_io_full }),
.io_mainClk(io_mainClk),
.io_masks(interruptCtrl_1_io_masks_driver),
.io_pendings(interruptCtrl_1_io_pendings),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Prescaler prescaler_1 (
.io_clear(_zz_io_clear),
.io_limit(_zz_io_limit),
.io_mainClk(io_mainClk),
.io_overflow(prescaler_1_io_overflow),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Timer timerA (
.io_clear(timerA_io_clear),
.io_full(timerA_io_full),
.io_limit(timerA_io_limit_driver),
.io_mainClk(io_mainClk),
.io_tick(timerA_io_tick),
.io_value(timerA_io_value),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Timer timerB (
.io_clear(timerB_io_clear),
.io_full(timerB_io_full),
.io_limit(timerB_io_limit_driver),
.io_mainClk(io_mainClk),
.io_tick(timerB_io_tick),
.io_value(timerB_io_value),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign _05_[0] = timerABridge_ticksEnable[0];
assign _07_[0] = timerBBridge_ticksEnable[0];
assign interruptCtrl_1_io_inputs = { timerB_io_full, timerA_io_full };
assign io_apb_PRDATA[31:17] = 15'h0000;
assign io_apb_PREADY = 1'h1;
assign io_apb_PSLVERROR = 1'h0;
endmodule
module MuraxMasterArbiter(io_iBus_cmd_valid, io_iBus_cmd_ready, io_iBus_cmd_payload_pc, io_iBus_rsp_valid, io_iBus_rsp_payload_error, io_iBus_rsp_payload_inst, io_dBus_cmd_valid, io_dBus_cmd_ready, io_dBus_cmd_payload_wr, io_dBus_cmd_payload_address, io_dBus_cmd_payload_data, io_dBus_cmd_payload_size, io_dBus_rsp_ready, io_dBus_rsp_error, io_dBus_rsp_data, io_masterBus_cmd_valid, io_masterBus_cmd_ready, io_masterBus_cmd_payload_write, io_masterBus_cmd_payload_address, io_masterBus_cmd_payload_data, io_masterBus_cmd_payload_mask
, io_masterBus_rsp_valid, io_masterBus_rsp_payload_data, io_mainClk, resetCtrl_systemReset);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire [3:0] _zz_io_masterBus_cmd_payload_mask;
input [31:0] io_dBus_cmd_payload_address;
wire [31:0] io_dBus_cmd_payload_address;
input [31:0] io_dBus_cmd_payload_data;
wire [31:0] io_dBus_cmd_payload_data;
input [1:0] io_dBus_cmd_payload_size;
wire [1:0] io_dBus_cmd_payload_size;
input io_dBus_cmd_payload_wr;
wire io_dBus_cmd_payload_wr;
output io_dBus_cmd_ready;
wire io_dBus_cmd_ready;
input io_dBus_cmd_valid;
wire io_dBus_cmd_valid;
output [31:0] io_dBus_rsp_data;
wire [31:0] io_dBus_rsp_data;
output io_dBus_rsp_error;
wire io_dBus_rsp_error;
output io_dBus_rsp_ready;
wire io_dBus_rsp_ready;
input [31:0] io_iBus_cmd_payload_pc;
wire [31:0] io_iBus_cmd_payload_pc;
output io_iBus_cmd_ready;
wire io_iBus_cmd_ready;
input io_iBus_cmd_valid;
wire io_iBus_cmd_valid;
output io_iBus_rsp_payload_error;
wire io_iBus_rsp_payload_error;
output [31:0] io_iBus_rsp_payload_inst;
wire [31:0] io_iBus_rsp_payload_inst;
output io_iBus_rsp_valid;
wire io_iBus_rsp_valid;
input io_mainClk;
wire io_mainClk;
wire io_masterBus_cmd_fire;
output [31:0] io_masterBus_cmd_payload_address;
wire [31:0] io_masterBus_cmd_payload_address;
output [31:0] io_masterBus_cmd_payload_data;
wire [31:0] io_masterBus_cmd_payload_data;
output [3:0] io_masterBus_cmd_payload_mask;
wire [3:0] io_masterBus_cmd_payload_mask;
output io_masterBus_cmd_payload_write;
wire io_masterBus_cmd_payload_write;
input io_masterBus_cmd_ready;
wire io_masterBus_cmd_ready;
output io_masterBus_cmd_valid;
wire io_masterBus_cmd_valid;
input [31:0] io_masterBus_rsp_payload_data;
wire [31:0] io_masterBus_rsp_payload_data;
input io_masterBus_rsp_valid;
wire io_masterBus_rsp_valid;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
wire rspPending;
wire rspTarget;
wire when_MuraxUtiles_l31;
wire when_MuraxUtiles_l36;
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) rspTarget_reg /* _10_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_dBus_cmd_valid),
.EN(when_MuraxUtiles_l31),
.Q(rspTarget)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) rspPending_reg /* _11_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_00_),
.EN(_01_),
.Q(rspPending)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _12_ (
.A({ when_MuraxUtiles_l31, io_masterBus_rsp_valid }),
.Y(_01_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _13_ (
.A(io_dBus_cmd_valid),
.B(io_dBus_cmd_payload_wr),
.Y(io_masterBus_cmd_payload_write)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _14_ (
.A(io_masterBus_cmd_ready),
.B(_03_),
.Y(_02_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _15_ (
.A(io_masterBus_cmd_valid),
.B(io_masterBus_cmd_ready),
.Y(io_masterBus_cmd_fire)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _16_ (
.A(io_masterBus_cmd_fire),
.B(_04_),
.Y(when_MuraxUtiles_l31)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _17_ (
.A(rspPending),
.B(_05_),
.Y(when_MuraxUtiles_l36)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _18_ (
.A(io_masterBus_rsp_valid),
.B(_06_),
.Y(io_iBus_rsp_valid)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _19_ (
.A(io_masterBus_rsp_valid),
.B(rspTarget),
.Y(io_dBus_rsp_ready)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _20_ (
.A(io_dBus_cmd_valid),
.Y(_03_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _21_ (
.A(io_masterBus_cmd_payload_write),
.Y(_04_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _22_ (
.A(io_masterBus_rsp_valid),
.Y(_05_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _23_ (
.A(rspTarget),
.Y(_06_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _24_ (
.A(io_iBus_cmd_valid),
.B(io_dBus_cmd_valid),
.Y(_07_)
);
\$mux #(
.WIDTH(32'd1)
) _25_ (
.A(1'h0),
.B(1'h1),
.S(when_MuraxUtiles_l31),
.Y(_00_)
);
\$mux #(
.WIDTH(32'd1)
) _26_ (
.A(io_masterBus_cmd_ready),
.B(1'h0),
.S(when_MuraxUtiles_l36),
.Y(io_dBus_cmd_ready)
);
\$mux #(
.WIDTH(32'd1)
) _27_ (
.A(_02_),
.B(1'h0),
.S(when_MuraxUtiles_l36),
.Y(io_iBus_cmd_ready)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd2)
) _28_ (
.A(2'h3),
.B(4'h1),
.S({ _09_, _08_ }),
.Y({ _zz_io_masterBus_cmd_payload_mask[3], _zz_io_masterBus_cmd_payload_mask[1] })
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _29_ (
.A(io_dBus_cmd_payload_size),
.B(1'h1),
.Y(_08_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _30_ (
.A(io_dBus_cmd_payload_size),
.Y(_09_)
);
\$mux #(
.WIDTH(32'd1)
) _31_ (
.A(_07_),
.B(1'h0),
.S(when_MuraxUtiles_l36),
.Y(io_masterBus_cmd_valid)
);
\$sshl #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd4)
) _32_ (
.A({ _zz_io_masterBus_cmd_payload_mask[3], _zz_io_masterBus_cmd_payload_mask[3], _zz_io_masterBus_cmd_payload_mask[1], 1'h1 }),
.B(io_dBus_cmd_payload_address[1:0]),
.Y(io_masterBus_cmd_payload_mask)
);
\$mux #(
.WIDTH(32'd32)
) _33_ (
.A(io_iBus_cmd_payload_pc),
.B(io_dBus_cmd_payload_address),
.S(io_dBus_cmd_valid),
.Y(io_masterBus_cmd_payload_address)
);
assign { _zz_io_masterBus_cmd_payload_mask[2], _zz_io_masterBus_cmd_payload_mask[0] } = { _zz_io_masterBus_cmd_payload_mask[3], 1'h1 };
assign io_dBus_rsp_data = io_masterBus_rsp_payload_data;
assign io_dBus_rsp_error = 1'h0;
assign io_iBus_rsp_payload_error = 1'h0;
assign io_iBus_rsp_payload_inst = io_masterBus_rsp_payload_data;
assign io_masterBus_cmd_payload_data = io_dBus_cmd_payload_data;
endmodule
module MuraxPipelinedMemoryBusRam(io_bus_cmd_valid, io_bus_cmd_ready, io_bus_cmd_payload_write, io_bus_cmd_payload_address, io_bus_cmd_payload_data, io_bus_cmd_payload_mask, io_bus_rsp_valid, io_bus_rsp_payload_data, io_mainClk, resetCtrl_systemReset);
wire [7:0] _00_;
wire [7:0] _01_;
wire [7:0] _02_;
wire [7:0] _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire [29:0] _zz_io_bus_rsp_payload_data;
wire [31:0] _zz_io_bus_rsp_payload_data_1;
wire [10:0] _zz_io_bus_rsp_payload_data_2;
wire _zz_io_bus_rsp_valid;
wire [31:0] _zz_ram_port0;
wire [7:0] _zz_ramsymbol_read;
wire [7:0] _zz_ramsymbol_read_1;
wire [7:0] _zz_ramsymbol_read_2;
wire [7:0] _zz_ramsymbol_read_3;
wire io_bus_cmd_fire;
input [31:0] io_bus_cmd_payload_address;
wire [31:0] io_bus_cmd_payload_address;
input [31:0] io_bus_cmd_payload_data;
wire [31:0] io_bus_cmd_payload_data;
input [3:0] io_bus_cmd_payload_mask;
wire [3:0] io_bus_cmd_payload_mask;
input io_bus_cmd_payload_write;
wire io_bus_cmd_payload_write;
output io_bus_cmd_ready;
wire io_bus_cmd_ready;
input io_bus_cmd_valid;
wire io_bus_cmd_valid;
output [31:0] io_bus_rsp_payload_data;
wire [31:0] io_bus_rsp_payload_data;
output io_bus_rsp_valid;
wire io_bus_rsp_valid;
input io_mainClk;
wire io_mainClk;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
reg [7:0] ram_symbol0 [2047:0];
always @(posedge io_mainClk) begin
if (_00_[7])
ram_symbol0[io_bus_cmd_payload_address[12:2]] <= io_bus_cmd_payload_data[7:0];
end
reg [7:0] _29_;
always @(posedge io_mainClk) begin
if (io_bus_cmd_valid) begin
_29_ <= ram_symbol0[io_bus_cmd_payload_address[12:2]];
end
end
assign _zz_ramsymbol_read = _29_;
reg [7:0] ram_symbol1 [2047:0];
always @(posedge io_mainClk) begin
if (_01_[7])
ram_symbol1[io_bus_cmd_payload_address[12:2]] <= io_bus_cmd_payload_data[15:8];
end
reg [7:0] _30_;
always @(posedge io_mainClk) begin
if (io_bus_cmd_valid) begin
_30_ <= ram_symbol1[io_bus_cmd_payload_address[12:2]];
end
end
assign _zz_ramsymbol_read_1 = _30_;
reg [7:0] ram_symbol2 [2047:0];
always @(posedge io_mainClk) begin
if (_02_[7])
ram_symbol2[io_bus_cmd_payload_address[12:2]] <= io_bus_cmd_payload_data[23:16];
end
reg [7:0] _31_;
always @(posedge io_mainClk) begin
if (io_bus_cmd_valid) begin
_31_ <= ram_symbol2[io_bus_cmd_payload_address[12:2]];
end
end
assign _zz_ramsymbol_read_2 = _31_;
reg [7:0] ram_symbol3 [2047:0];
always @(posedge io_mainClk) begin
if (_03_[7])
ram_symbol3[io_bus_cmd_payload_address[12:2]] <= io_bus_cmd_payload_data[31:24];
end
reg [7:0] _32_;
always @(posedge io_mainClk) begin
if (io_bus_cmd_valid) begin
_32_ <= ram_symbol3[io_bus_cmd_payload_address[12:2]];
end
end
assign _zz_ramsymbol_read_3 = _32_;
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _14_ (
.A(io_bus_cmd_payload_mask[0]),
.B(io_bus_cmd_valid),
.Y(_05_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _15_ (
.A(_05_),
.B(io_bus_cmd_payload_write),
.Y(_06_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _16_ (
.A(io_bus_cmd_payload_mask[1]),
.B(io_bus_cmd_valid),
.Y(_07_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _17_ (
.A(_07_),
.B(io_bus_cmd_payload_write),
.Y(_08_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _18_ (
.A(io_bus_cmd_payload_mask[2]),
.B(io_bus_cmd_valid),
.Y(_09_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _19_ (
.A(_09_),
.B(io_bus_cmd_payload_write),
.Y(_10_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _20_ (
.A(io_bus_cmd_payload_mask[3]),
.B(io_bus_cmd_valid),
.Y(_11_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _21_ (
.A(_11_),
.B(io_bus_cmd_payload_write),
.Y(_12_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _22_ (
.A(io_bus_cmd_valid),
.B(_13_),
.Y(_04_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _23_ (
.A(io_bus_cmd_payload_write),
.Y(_13_)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) _zz_io_bus_rsp_valid_reg /* _24_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_04_),
.Q(_zz_io_bus_rsp_valid)
);
\$mux #(
.WIDTH(32'd1)
) _25_ (
.A(1'h0),
.B(1'h1),
.S(_12_),
.Y(_03_[7])
);
\$mux #(
.WIDTH(32'd1)
) _26_ (
.A(1'h0),
.B(1'h1),
.S(_10_),
.Y(_02_[7])
);
\$mux #(
.WIDTH(32'd1)
) _27_ (
.A(1'h0),
.B(1'h1),
.S(_08_),
.Y(_01_[7])
);
\$mux #(
.WIDTH(32'd1)
) _28_ (
.A(1'h0),
.B(1'h1),
.S(_06_),
.Y(_00_[7])
);
assign _00_[6:0] = { _00_[7], _00_[7], _00_[7], _00_[7], _00_[7], _00_[7], _00_[7] };
assign _01_[6:0] = { _01_[7], _01_[7], _01_[7], _01_[7], _01_[7], _01_[7], _01_[7] };
assign _02_[6:0] = { _02_[7], _02_[7], _02_[7], _02_[7], _02_[7], _02_[7], _02_[7] };
assign _03_[6:0] = { _03_[7], _03_[7], _03_[7], _03_[7], _03_[7], _03_[7], _03_[7] };
assign _zz_io_bus_rsp_payload_data = io_bus_cmd_payload_address[31:2];
assign _zz_io_bus_rsp_payload_data_1 = io_bus_cmd_payload_data;
assign _zz_io_bus_rsp_payload_data_2 = io_bus_cmd_payload_address[12:2];
assign _zz_ram_port0 = { _zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read };
assign io_bus_cmd_fire = io_bus_cmd_valid;
assign io_bus_cmd_ready = 1'h1;
assign io_bus_rsp_payload_data = { _zz_ramsymbol_read_3, _zz_ramsymbol_read_2, _zz_ramsymbol_read_1, _zz_ramsymbol_read };
assign io_bus_rsp_valid = _zz_io_bus_rsp_valid;
endmodule
module PipelinedMemoryBusToApbBridge(io_pipelinedMemoryBus_cmd_valid, io_pipelinedMemoryBus_cmd_ready, io_pipelinedMemoryBus_cmd_payload_write, io_pipelinedMemoryBus_cmd_payload_address, io_pipelinedMemoryBus_cmd_payload_data, io_pipelinedMemoryBus_cmd_payload_mask, io_pipelinedMemoryBus_rsp_valid, io_pipelinedMemoryBus_rsp_payload_data, io_apb_PADDR, io_apb_PSEL, io_apb_PENABLE, io_apb_PREADY, io_apb_PWRITE, io_apb_PWDATA, io_apb_PRDATA, io_apb_PSLVERROR, io_mainClk, resetCtrl_systemReset);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
output [19:0] io_apb_PADDR;
wire [19:0] io_apb_PADDR;
output io_apb_PENABLE;
wire io_apb_PENABLE;
input [31:0] io_apb_PRDATA;
wire [31:0] io_apb_PRDATA;
input io_apb_PREADY;
wire io_apb_PREADY;
output io_apb_PSEL;
wire io_apb_PSEL;
input io_apb_PSLVERROR;
wire io_apb_PSLVERROR;
output [31:0] io_apb_PWDATA;
wire [31:0] io_apb_PWDATA;
output io_apb_PWRITE;
wire io_apb_PWRITE;
input io_mainClk;
wire io_mainClk;
wire io_pipelinedMemoryBus_cmd_halfPipe_fire;
wire [31:0] io_pipelinedMemoryBus_cmd_halfPipe_payload_address;
wire [31:0] io_pipelinedMemoryBus_cmd_halfPipe_payload_data;
wire io_pipelinedMemoryBus_cmd_halfPipe_payload_write;
wire io_pipelinedMemoryBus_cmd_halfPipe_ready;
wire io_pipelinedMemoryBus_cmd_halfPipe_valid;
input [31:0] io_pipelinedMemoryBus_cmd_payload_address;
wire [31:0] io_pipelinedMemoryBus_cmd_payload_address;
input [31:0] io_pipelinedMemoryBus_cmd_payload_data;
wire [31:0] io_pipelinedMemoryBus_cmd_payload_data;
input [3:0] io_pipelinedMemoryBus_cmd_payload_mask;
wire [3:0] io_pipelinedMemoryBus_cmd_payload_mask;
input io_pipelinedMemoryBus_cmd_payload_write;
wire io_pipelinedMemoryBus_cmd_payload_write;
wire [31:0] io_pipelinedMemoryBus_cmd_rData_address;
wire [31:0] io_pipelinedMemoryBus_cmd_rData_data;
wire io_pipelinedMemoryBus_cmd_rData_write;
wire io_pipelinedMemoryBus_cmd_rValid;
output io_pipelinedMemoryBus_cmd_ready;
wire io_pipelinedMemoryBus_cmd_ready;
input io_pipelinedMemoryBus_cmd_valid;
wire io_pipelinedMemoryBus_cmd_valid;
output [31:0] io_pipelinedMemoryBus_rsp_payload_data;
wire [31:0] io_pipelinedMemoryBus_rsp_payload_data;
output io_pipelinedMemoryBus_rsp_valid;
wire io_pipelinedMemoryBus_rsp_valid;
wire [31:0] pipelinedMemoryBusStage_cmd_payload_address;
wire [31:0] pipelinedMemoryBusStage_cmd_payload_data;
wire pipelinedMemoryBusStage_cmd_payload_write;
wire pipelinedMemoryBusStage_cmd_ready;
wire pipelinedMemoryBusStage_cmd_valid;
wire [31:0] pipelinedMemoryBusStage_rsp_payload_data;
wire [31:0] pipelinedMemoryBusStage_rsp_regNext_payload_data;
wire pipelinedMemoryBusStage_rsp_regNext_valid;
wire pipelinedMemoryBusStage_rsp_valid;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
wire state;
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) io_pipelinedMemoryBus_cmd_rValid_reg /* _07_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_00_),
.EN(_04_),
.Q(io_pipelinedMemoryBus_cmd_rValid)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd32)
) _08_ (
.CLK(io_mainClk),
.D(io_pipelinedMemoryBus_cmd_payload_data),
.EN(io_pipelinedMemoryBus_cmd_rValid),
.Q(io_pipelinedMemoryBus_cmd_rData_data)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd20)
) _09_ (
.CLK(io_mainClk),
.D(io_pipelinedMemoryBus_cmd_payload_address[19:0]),
.EN(io_pipelinedMemoryBus_cmd_rValid),
.Q(io_pipelinedMemoryBus_cmd_rData_address[19:0])
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) io_pipelinedMemoryBus_cmd_rData_write_reg /* _10_ */ (
.CLK(io_mainClk),
.D(io_pipelinedMemoryBus_cmd_payload_write),
.EN(io_pipelinedMemoryBus_cmd_rValid),
.Q(io_pipelinedMemoryBus_cmd_rData_write)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _11_ (
.A({ io_pipelinedMemoryBus_cmd_halfPipe_fire, io_pipelinedMemoryBus_cmd_valid }),
.Y(_04_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _12_ (
.A(io_pipelinedMemoryBus_cmd_rValid),
.B(io_pipelinedMemoryBus_cmd_halfPipe_ready),
.Y(io_pipelinedMemoryBus_cmd_halfPipe_fire)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _13_ (
.A(io_pipelinedMemoryBus_cmd_rValid),
.Y(io_pipelinedMemoryBus_cmd_ready)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _14_ (
.A(io_pipelinedMemoryBus_cmd_rData_write),
.Y(_05_)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd32)
) _15_ (
.CLK(io_mainClk),
.D(io_apb_PRDATA),
.Q(pipelinedMemoryBusStage_rsp_regNext_payload_data)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) pipelinedMemoryBusStage_rsp_regNext_valid_reg /* _16_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(pipelinedMemoryBusStage_rsp_valid),
.Q(pipelinedMemoryBusStage_rsp_regNext_valid)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) state_reg /* _17_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_01_),
.Q(state)
);
\$mux #(
.WIDTH(32'd1)
) _18_ (
.A(1'h1),
.B(1'h0),
.S(io_apb_PREADY),
.Y(_06_)
);
\$mux #(
.WIDTH(32'd1)
) _19_ (
.A(io_pipelinedMemoryBus_cmd_rValid),
.B(_06_),
.S(state),
.Y(_01_)
);
\$mux #(
.WIDTH(32'd1)
) _20_ (
.A(1'h1),
.B(1'h0),
.S(io_pipelinedMemoryBus_cmd_halfPipe_fire),
.Y(_00_)
);
\$mux #(
.WIDTH(32'd1)
) _21_ (
.A(1'h0),
.B(_05_),
.S(io_apb_PREADY),
.Y(_03_)
);
\$mux #(
.WIDTH(32'd1)
) _22_ (
.A(1'h0),
.B(_03_),
.S(state),
.Y(pipelinedMemoryBusStage_rsp_valid)
);
\$mux #(
.WIDTH(32'd1)
) _23_ (
.A(1'h0),
.B(1'h1),
.S(io_apb_PREADY),
.Y(_02_)
);
\$mux #(
.WIDTH(32'd1)
) _24_ (
.A(1'h0),
.B(_02_),
.S(state),
.Y(io_pipelinedMemoryBus_cmd_halfPipe_ready)
);
assign io_apb_PADDR = io_pipelinedMemoryBus_cmd_rData_address[19:0];
assign io_apb_PENABLE = state;
assign io_apb_PSEL = io_pipelinedMemoryBus_cmd_rValid;
assign io_apb_PWDATA = io_pipelinedMemoryBus_cmd_rData_data;
assign io_apb_PWRITE = io_pipelinedMemoryBus_cmd_rData_write;
assign io_pipelinedMemoryBus_cmd_halfPipe_payload_address[19:0] = io_pipelinedMemoryBus_cmd_rData_address[19:0];
assign io_pipelinedMemoryBus_cmd_halfPipe_payload_data = io_pipelinedMemoryBus_cmd_rData_data;
assign io_pipelinedMemoryBus_cmd_halfPipe_payload_write = io_pipelinedMemoryBus_cmd_rData_write;
assign io_pipelinedMemoryBus_cmd_halfPipe_valid = io_pipelinedMemoryBus_cmd_rValid;
assign io_pipelinedMemoryBus_cmd_rData_address[31:20] = io_pipelinedMemoryBus_cmd_halfPipe_payload_address[31:20];
assign io_pipelinedMemoryBus_rsp_payload_data = pipelinedMemoryBusStage_rsp_regNext_payload_data;
assign io_pipelinedMemoryBus_rsp_valid = pipelinedMemoryBusStage_rsp_regNext_valid;
assign pipelinedMemoryBusStage_cmd_payload_address = { io_pipelinedMemoryBus_cmd_halfPipe_payload_address[31:20], io_pipelinedMemoryBus_cmd_rData_address[19:0] };
assign pipelinedMemoryBusStage_cmd_payload_data = io_pipelinedMemoryBus_cmd_rData_data;
assign pipelinedMemoryBusStage_cmd_payload_write = io_pipelinedMemoryBus_cmd_rData_write;
assign pipelinedMemoryBusStage_cmd_ready = io_pipelinedMemoryBus_cmd_halfPipe_ready;
assign pipelinedMemoryBusStage_cmd_valid = io_pipelinedMemoryBus_cmd_rValid;
assign pipelinedMemoryBusStage_rsp_payload_data = io_apb_PRDATA;
endmodule
module Prescaler(io_clear, io_limit, io_overflow, io_mainClk, resetCtrl_systemReset);
wire [15:0] _0_;
wire [15:0] _1_;
wire [15:0] _2_;
wire [15:0] counter;
input io_clear;
wire io_clear;
input [15:0] io_limit;
wire [15:0] io_limit;
input io_mainClk;
wire io_mainClk;
output io_overflow;
wire io_overflow;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
wire when_Prescaler_l17;
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd16),
.Y_WIDTH(32'd16)
) _3_ (
.A(1'h1),
.B(counter),
.BI(1'h0),
.CI(1'h0),
.CO(_2_),
.X(_1_),
.Y(_0_)
);
\$sdff #(
.CLK_POLARITY(32'd1),
.SRST_POLARITY(32'd1),
.SRST_VALUE(16'h0000),
.WIDTH(32'd16)
) _4_ (
.CLK(io_mainClk),
.D(_0_),
.Q(counter),
.SRST(when_Prescaler_l17)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd16),
.B_SIGNED(32'd0),
.B_WIDTH(32'd16),
.Y_WIDTH(32'd1)
) _5_ (
.A(counter),
.B(io_limit),
.Y(io_overflow)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _6_ (
.A(io_clear),
.B(io_overflow),
.Y(when_Prescaler_l17)
);
endmodule
module StreamFifo(io_push_valid, io_push_ready, io_push_payload, io_pop_valid, io_pop_ready, io_pop_payload, io_flush, io_occupancy, io_availability, io_mainClk, resetCtrl_systemReset);
wire [7:0] _00_;
wire _01_;
wire _02_;
wire [3:0] _03_;
wire [3:0] _04_;
wire [3:0] _05_;
wire [3:0] _06_;
wire [3:0] _07_;
wire [3:0] _08_;
wire [3:0] _09_;
wire [3:0] _10_;
wire [3:0] _11_;
wire [3:0] _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _zz_1;
wire [3:0] _zz_io_availability;
wire _zz_io_pop_payload;
wire _zz_io_pop_valid;
wire [3:0] _zz_logic_popPtr_valueNext;
wire _zz_logic_popPtr_valueNext_1;
wire [3:0] _zz_logic_pushPtr_valueNext;
wire _zz_logic_pushPtr_valueNext_1;
wire [7:0] _zz_logic_ram_port0;
output [4:0] io_availability;
wire [4:0] io_availability;
input io_flush;
wire io_flush;
input io_mainClk;
wire io_mainClk;
output [4:0] io_occupancy;
wire [4:0] io_occupancy;
output [7:0] io_pop_payload;
wire [7:0] io_pop_payload;
input io_pop_ready;
wire io_pop_ready;
output io_pop_valid;
wire io_pop_valid;
input [7:0] io_push_payload;
wire [7:0] io_push_payload;
output io_push_ready;
wire io_push_ready;
input io_push_valid;
wire io_push_valid;
wire logic_empty;
wire logic_full;
wire [3:0] logic_popPtr_value;
wire [3:0] logic_popPtr_valueNext;
wire logic_popPtr_willClear;
wire logic_popPtr_willIncrement;
wire logic_popping;
wire [3:0] logic_ptrDif;
wire logic_ptrMatch;
wire [3:0] logic_pushPtr_value;
wire [3:0] logic_pushPtr_valueNext;
wire logic_pushPtr_willClear;
wire logic_pushPtr_willIncrement;
wire logic_pushing;
wire logic_risingOccupancy;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
wire when_Stream_l954;
reg [7:0] logic_ram [15:0];
always @(posedge io_mainClk) begin
if (_00_[7])
logic_ram[logic_pushPtr_value] <= io_push_payload;
end
reg [7:0] _47_;
always @(posedge io_mainClk) begin
_47_ <= logic_ram[logic_popPtr_valueNext];
end
assign _zz_logic_ram_port0 = _47_;
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd4),
.Y_WIDTH(32'd4)
) _18_ (
.A(_zz_1),
.B(logic_pushPtr_value),
.BI(1'h0),
.CI(1'h0),
.CO(_09_),
.X(_05_),
.Y(_03_)
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd4),
.Y_WIDTH(32'd4)
) _19_ (
.A(_zz_logic_popPtr_valueNext_1),
.B(logic_popPtr_value),
.BI(1'h0),
.CI(1'h0),
.CO(_10_),
.X(_06_),
.Y(_04_)
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.B_SIGNED(32'd0),
.B_WIDTH(32'd4),
.Y_WIDTH(32'd4)
) _20_ (
.A(logic_popPtr_value),
.B(logic_pushPtr_value),
.BI(1'h1),
.CI(1'h1),
.CO(_11_),
.X(_07_),
.Y(_zz_io_availability)
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.B_SIGNED(32'd0),
.B_WIDTH(32'd4),
.Y_WIDTH(32'd4)
) _21_ (
.A(logic_pushPtr_value),
.B(logic_popPtr_value),
.BI(1'h1),
.CI(1'h1),
.CO(_12_),
.X(_08_),
.Y(logic_ptrDif)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.Y_WIDTH(32'd1)
) _22_ (
.A(_08_),
.Y(logic_ptrMatch)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) logic_risingOccupancy_reg /* _23_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_02_),
.EN(_13_),
.Q(logic_risingOccupancy)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _24_ (
.A({ when_Stream_l954, io_flush }),
.Y(_13_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.B_SIGNED(32'd0),
.B_WIDTH(32'd4),
.Y_WIDTH(32'd1)
) _25_ (
.A(logic_popPtr_valueNext),
.B(logic_pushPtr_value),
.Y(_01_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _26_ (
.A(io_push_valid),
.B(io_push_ready),
.Y(logic_pushing)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _27_ (
.A(io_pop_valid),
.B(io_pop_ready),
.Y(logic_popping)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _28_ (
.A(logic_ptrMatch),
.B(_15_),
.Y(logic_empty)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _29_ (
.A(logic_ptrMatch),
.B(logic_risingOccupancy),
.Y(logic_full)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _30_ (
.A(_zz_io_pop_valid),
.B(io_push_ready),
.Y(_14_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _31_ (
.A(_16_),
.B(_17_),
.Y(io_pop_valid)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _32_ (
.A(logic_risingOccupancy),
.Y(_15_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _33_ (
.A(logic_full),
.Y(io_push_ready)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _34_ (
.A(logic_empty),
.Y(_16_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _35_ (
.A(_14_),
.Y(_17_)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _36_ (
.A(logic_pushing),
.B(logic_popping),
.Y(when_Stream_l954)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(4'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd4)
) _37_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(logic_pushPtr_valueNext),
.Q(logic_pushPtr_value)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(4'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd4)
) _38_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(logic_popPtr_valueNext),
.Q(logic_popPtr_value)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) _zz_io_pop_valid_reg /* _39_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_01_),
.Q(_zz_io_pop_valid)
);
\$mux #(
.WIDTH(32'd1)
) _40_ (
.A(logic_pushing),
.B(1'h0),
.S(io_flush),
.Y(_02_)
);
\$mux #(
.WIDTH(32'd4)
) _41_ (
.A(_04_),
.B(4'h0),
.S(logic_popPtr_willClear),
.Y(logic_popPtr_valueNext)
);
\$mux #(
.WIDTH(32'd1)
) _42_ (
.A(1'h0),
.B(1'h1),
.S(io_flush),
.Y(logic_popPtr_willClear)
);
\$mux #(
.WIDTH(32'd1)
) _43_ (
.A(1'h0),
.B(1'h1),
.S(logic_popping),
.Y(_zz_logic_popPtr_valueNext_1)
);
\$mux #(
.WIDTH(32'd4)
) _44_ (
.A(_03_),
.B(4'h0),
.S(logic_popPtr_willClear),
.Y(logic_pushPtr_valueNext)
);
\$mux #(
.WIDTH(32'd1)
) _45_ (
.A(1'h0),
.B(1'h1),
.S(logic_pushing),
.Y(_zz_1)
);
\$mux #(
.WIDTH(32'd1)
) _46_ (
.A(1'h0),
.B(1'h1),
.S(_zz_1),
.Y(_00_[7])
);
assign _00_[6:0] = { _00_[7], _00_[7], _00_[7], _00_[7], _00_[7], _00_[7], _00_[7] };
assign _zz_io_pop_payload = 1'h1;
assign _zz_logic_popPtr_valueNext = { 3'h0, _zz_logic_popPtr_valueNext_1 };
assign _zz_logic_pushPtr_valueNext = { 3'h0, _zz_1 };
assign _zz_logic_pushPtr_valueNext_1 = _zz_1;
assign io_availability = { logic_empty, _zz_io_availability };
assign io_occupancy = { logic_full, logic_ptrDif };
assign io_pop_payload = _zz_logic_ram_port0;
assign logic_popPtr_willIncrement = _zz_logic_popPtr_valueNext_1;
assign logic_pushPtr_willClear = logic_popPtr_willClear;
assign logic_pushPtr_willIncrement = _zz_1;
endmodule
module StreamFifoLowLatency(io_push_valid, io_push_ready, io_push_payload_error, io_push_payload_inst, io_pop_valid, io_pop_ready, io_pop_payload_error, io_pop_payload_inst, io_flush, io_occupancy, io_mainClk, resetCtrl_systemReset);
wire _00_;
wire _01_;
wire [32:0] _zz_readed_error;
wire [32:0] _zz_readed_error_1;
wire [32:0] _zz_readed_error_2;
wire full;
input io_flush;
wire io_flush;
input io_mainClk;
wire io_mainClk;
output io_occupancy;
wire io_occupancy;
output io_pop_payload_error;
wire io_pop_payload_error;
output [31:0] io_pop_payload_inst;
wire [31:0] io_pop_payload_inst;
input io_pop_ready;
wire io_pop_ready;
output io_pop_valid;
wire io_pop_valid;
input io_push_payload_error;
wire io_push_payload_error;
input [31:0] io_push_payload_inst;
wire [31:0] io_push_payload_inst;
output io_push_ready;
wire io_push_ready;
input io_push_valid;
wire io_push_valid;
wire popPtr_willOverflowIfInc;
wire popping;
wire ptrMatch;
wire pushPtr_willOverflowIfInc;
wire pushing;
wire readed_error;
wire [31:0] readed_inst;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
wire risingOccupancy;
wire when_Phase_l623;
wire when_Stream_l1019;
wire when_Stream_l1032;
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) risingOccupancy_reg /* _02_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_00_),
.EN(_01_),
.Q(risingOccupancy)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd33)
) _03_ (
.CLK(io_mainClk),
.D({ io_push_payload_inst, io_push_payload_error }),
.EN(when_Phase_l623),
.Q(_zz_readed_error_2)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _04_ (
.A({ when_Stream_l1032, io_flush }),
.Y(_01_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _05_ (
.A(io_push_valid),
.B(io_push_ready),
.Y(pushing)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _06_ (
.A(io_pop_valid),
.B(io_pop_ready),
.Y(popping)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _07_ (
.A(risingOccupancy),
.Y(io_push_ready)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _08_ (
.A(pushing),
.B(popping),
.Y(when_Stream_l1032)
);
\$mux #(
.WIDTH(32'd1)
) _09_ (
.A(pushing),
.B(1'h0),
.S(io_flush),
.Y(_00_)
);
\$mux #(
.WIDTH(32'd32)
) _10_ (
.A(io_push_payload_inst),
.B(_zz_readed_error_2[32:1]),
.S(risingOccupancy),
.Y(io_pop_payload_inst)
);
\$mux #(
.WIDTH(32'd1)
) _11_ (
.A(io_push_payload_error),
.B(_zz_readed_error_2[0]),
.S(risingOccupancy),
.Y(io_pop_payload_error)
);
\$mux #(
.WIDTH(32'd1)
) _12_ (
.A(io_push_valid),
.B(1'h1),
.S(risingOccupancy),
.Y(io_pop_valid)
);
\$mux #(
.WIDTH(32'd1)
) _13_ (
.A(1'h0),
.B(1'h1),
.S(pushing),
.Y(when_Phase_l623)
);
assign _zz_readed_error = _zz_readed_error_2;
assign _zz_readed_error_1 = _zz_readed_error_2;
assign full = risingOccupancy;
assign io_occupancy = risingOccupancy;
assign popPtr_willOverflowIfInc = 1'h1;
assign ptrMatch = 1'h1;
assign pushPtr_willOverflowIfInc = 1'h1;
assign readed_error = _zz_readed_error_2[0];
assign readed_inst = _zz_readed_error_2[32:1];
assign when_Stream_l1019 = risingOccupancy;
endmodule
module SystemDebugger(io_remote_cmd_valid, io_remote_cmd_ready, io_remote_cmd_payload_last, io_remote_cmd_payload_fragment, io_remote_rsp_valid, io_remote_rsp_ready, io_remote_rsp_payload_error, io_remote_rsp_payload_data, io_mem_cmd_valid, io_mem_cmd_ready, io_mem_cmd_payload_address, io_mem_cmd_payload_data, io_mem_cmd_payload_wr, io_mem_cmd_payload_size, io_mem_rsp_valid, io_mem_rsp_payload, io_mainClk, resetCtrl_mainClkReset);
wire _00_;
wire _01_;
wire [2:0] _02_;
wire [2:0] _03_;
wire [2:0] _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire [2:0] _17_;
wire _18_;
wire _19_;
wire _20_;
wire [66:0] _zz_io_mem_cmd_payload_address;
wire [2:0] dispatcher_counter;
wire dispatcher_dataLoaded;
wire [66:0] dispatcher_dataShifter;
wire [7:0] dispatcher_header;
wire dispatcher_headerLoaded;
wire [7:0] dispatcher_headerShifter;
input io_mainClk;
wire io_mainClk;
wire io_mem_cmd_isStall;
output [31:0] io_mem_cmd_payload_address;
wire [31:0] io_mem_cmd_payload_address;
output [31:0] io_mem_cmd_payload_data;
wire [31:0] io_mem_cmd_payload_data;
output [1:0] io_mem_cmd_payload_size;
wire [1:0] io_mem_cmd_payload_size;
output io_mem_cmd_payload_wr;
wire io_mem_cmd_payload_wr;
input io_mem_cmd_ready;
wire io_mem_cmd_ready;
output io_mem_cmd_valid;
wire io_mem_cmd_valid;
input [31:0] io_mem_rsp_payload;
wire [31:0] io_mem_rsp_payload;
input io_mem_rsp_valid;
wire io_mem_rsp_valid;
input io_remote_cmd_payload_fragment;
wire io_remote_cmd_payload_fragment;
input io_remote_cmd_payload_last;
wire io_remote_cmd_payload_last;
output io_remote_cmd_ready;
wire io_remote_cmd_ready;
input io_remote_cmd_valid;
wire io_remote_cmd_valid;
output [31:0] io_remote_rsp_payload_data;
wire [31:0] io_remote_rsp_payload_data;
output io_remote_rsp_payload_error;
wire io_remote_rsp_payload_error;
input io_remote_rsp_ready;
wire io_remote_rsp_ready;
output io_remote_rsp_valid;
wire io_remote_rsp_valid;
input resetCtrl_mainClkReset;
wire resetCtrl_mainClkReset;
wire when_Fragment_l349;
wire when_Fragment_l372;
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd3)
) _21_ (
.A(1'h1),
.B(dispatcher_counter),
.BI(1'h0),
.CI(1'h0),
.CO(_04_),
.X(_03_),
.Y(_02_)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(3'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd3)
) _22_ (
.ARST(resetCtrl_mainClkReset),
.CLK(io_mainClk),
.D(_17_),
.EN(_08_),
.Q(dispatcher_counter)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) dispatcher_headerLoaded_reg /* _23_ */ (
.ARST(resetCtrl_mainClkReset),
.CLK(io_mainClk),
.D(_01_),
.EN(_06_),
.Q(dispatcher_headerLoaded)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) dispatcher_dataLoaded_reg /* _24_ */ (
.ARST(resetCtrl_mainClkReset),
.CLK(io_mainClk),
.D(_00_),
.EN(_09_),
.Q(dispatcher_dataLoaded)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd8)
) _25_ (
.CLK(io_mainClk),
.D({ io_remote_cmd_payload_fragment, dispatcher_headerShifter[7:1] }),
.EN(_10_),
.Q(dispatcher_headerShifter)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd67)
) _26_ (
.CLK(io_mainClk),
.D({ io_remote_cmd_payload_fragment, dispatcher_dataShifter[66:1] }),
.EN(_11_),
.Q(dispatcher_dataShifter)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _27_ (
.A({ dispatcher_headerLoaded, io_remote_cmd_payload_last }),
.B(2'h2),
.Y(_05_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _28_ (
.A({ when_Fragment_l372, io_remote_cmd_valid }),
.Y(_06_)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _29_ (
.A({ when_Fragment_l372, io_remote_cmd_payload_last, io_remote_cmd_valid }),
.B(1'h1),
.Y(_07_)
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _30_ (
.A(dispatcher_headerLoaded),
.Y(_12_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _31_ (
.A({ _05_, io_remote_cmd_valid }),
.Y(_08_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _32_ (
.A({ _06_, _07_ }),
.Y(_09_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _33_ (
.A({ _12_, io_remote_cmd_valid }),
.Y(_10_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _34_ (
.A({ dispatcher_headerLoaded, io_remote_cmd_valid }),
.Y(_11_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _35_ (
.A(dispatcher_counter),
.B(3'h7),
.Y(when_Fragment_l349)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.Y_WIDTH(32'd1)
) _36_ (
.A(dispatcher_headerShifter),
.Y(_13_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _37_ (
.A(dispatcher_dataLoaded),
.B(_13_),
.Y(io_mem_cmd_valid)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _38_ (
.A(io_mem_cmd_valid),
.B(_15_),
.Y(io_mem_cmd_isStall)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _39_ (
.A(dispatcher_headerLoaded),
.B(dispatcher_dataLoaded),
.Y(_14_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _40_ (
.A(_14_),
.B(_16_),
.Y(when_Fragment_l372)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _41_ (
.A(dispatcher_dataLoaded),
.Y(io_remote_cmd_ready)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _42_ (
.A(io_mem_cmd_ready),
.Y(_15_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _43_ (
.A(io_mem_cmd_isStall),
.Y(_16_)
);
\$mux #(
.WIDTH(32'd3)
) _44_ (
.A(_02_),
.B(3'h0),
.S(io_remote_cmd_payload_last),
.Y(_17_)
);
\$mux #(
.WIDTH(32'd1)
) _45_ (
.A(1'h0),
.B(1'h1),
.S(when_Fragment_l349),
.Y(_18_)
);
\$mux #(
.WIDTH(32'd1)
) _46_ (
.A(_18_),
.B(1'h1),
.S(dispatcher_headerLoaded),
.Y(_19_)
);
\$mux #(
.WIDTH(32'd1)
) _47_ (
.A(_19_),
.B(1'h1),
.S(io_remote_cmd_payload_last),
.Y(_20_)
);
\$mux #(
.WIDTH(32'd1)
) _48_ (
.A(_20_),
.B(1'h0),
.S(when_Fragment_l372),
.Y(_01_)
);
\$mux #(
.WIDTH(32'd1)
) _49_ (
.A(1'h1),
.B(1'h0),
.S(when_Fragment_l372),
.Y(_00_)
);
assign _zz_io_mem_cmd_payload_address = dispatcher_dataShifter;
assign dispatcher_header = dispatcher_headerShifter;
assign io_mem_cmd_payload_address = dispatcher_dataShifter[31:0];
assign io_mem_cmd_payload_data = dispatcher_dataShifter[63:32];
assign io_mem_cmd_payload_size = dispatcher_dataShifter[66:65];
assign io_mem_cmd_payload_wr = dispatcher_dataShifter[64];
assign io_remote_rsp_payload_data = io_mem_rsp_payload;
assign io_remote_rsp_payload_error = 1'h0;
assign io_remote_rsp_valid = io_mem_rsp_valid;
endmodule
module Timer(io_tick, io_clear, io_limit, io_full, io_value, io_mainClk, resetCtrl_systemReset);
wire _00_;
wire [15:0] _01_;
wire [15:0] _02_;
wire [15:0] _03_;
wire _04_;
wire _05_;
wire _06_;
wire [15:0] _zz_counter;
wire _zz_counter_1;
wire [15:0] counter;
wire inhibitFull;
input io_clear;
wire io_clear;
output io_full;
wire io_full;
input [15:0] io_limit;
wire [15:0] io_limit;
input io_mainClk;
wire io_mainClk;
input io_tick;
wire io_tick;
output [15:0] io_value;
wire [15:0] io_value;
wire limitHit;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd16),
.Y_WIDTH(32'd16)
) _07_ (
.A(_zz_counter_1),
.B(counter),
.BI(1'h0),
.CI(1'h0),
.CO(_03_),
.X(_02_),
.Y(_01_)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) inhibitFull_reg /* _08_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_00_),
.EN(_04_),
.Q(inhibitFull)
);
\$sdffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.SRST_POLARITY(32'd1),
.SRST_VALUE(16'h0000),
.WIDTH(32'd16)
) _09_ (
.CLK(io_mainClk),
.D(_01_),
.EN(io_tick),
.Q(counter),
.SRST(io_clear)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _10_ (
.A({ io_tick, io_clear }),
.Y(_04_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd16),
.B_SIGNED(32'd0),
.B_WIDTH(32'd16),
.Y_WIDTH(32'd1)
) _11_ (
.A(counter),
.B(io_limit),
.Y(limitHit)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _12_ (
.A(limitHit),
.B(io_tick),
.Y(_05_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _13_ (
.A(_05_),
.B(_06_),
.Y(io_full)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _14_ (
.A(limitHit),
.Y(_zz_counter_1)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _15_ (
.A(inhibitFull),
.Y(_06_)
);
\$mux #(
.WIDTH(32'd1)
) _16_ (
.A(limitHit),
.B(1'h0),
.S(io_clear),
.Y(_00_)
);
assign _zz_counter = { 15'h0000, _zz_counter_1 };
assign io_value = counter;
endmodule
module UartCtrl(io_config_frame_dataLength, io_config_frame_stop, io_config_frame_parity, io_config_clockDivider, io_write_valid, io_write_ready, io_write_payload, io_read_valid, io_read_ready, io_read_payload, io_uart_txd, io_uart_rxd, io_readError, io_writeBreak, io_readBreak, io_mainClk, resetCtrl_systemReset);
wire [19:0] _00_;
wire [19:0] _01_;
wire [19:0] _02_;
wire [19:0] _03_;
wire [19:0] clockDivider_counter;
wire clockDivider_tick;
wire clockDivider_tickReg;
input [19:0] io_config_clockDivider;
wire [19:0] io_config_clockDivider;
input [2:0] io_config_frame_dataLength;
wire [2:0] io_config_frame_dataLength;
input [1:0] io_config_frame_parity;
wire [1:0] io_config_frame_parity;
input io_config_frame_stop;
wire io_config_frame_stop;
input io_mainClk;
wire io_mainClk;
output io_readBreak;
wire io_readBreak;
output io_readError;
wire io_readError;
output [7:0] io_read_payload;
wire [7:0] io_read_payload;
input io_read_ready;
wire io_read_ready;
output io_read_valid;
wire io_read_valid;
input io_uart_rxd;
wire io_uart_rxd;
output io_uart_txd;
wire io_uart_txd;
input io_writeBreak;
wire io_writeBreak;
input [7:0] io_write_payload;
wire [7:0] io_write_payload;
output io_write_ready;
wire io_write_ready;
wire [7:0] io_write_thrown_payload;
wire io_write_thrown_ready;
wire io_write_thrown_valid;
input io_write_valid;
wire io_write_valid;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
wire rx_io_break;
wire rx_io_error;
wire [7:0] rx_io_read_payload;
wire rx_io_read_valid;
wire rx_io_rts;
wire tx_io_txd;
wire tx_io_write_ready;
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd20),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd20)
) _04_ (
.A(clockDivider_counter),
.B(1'h1),
.BI(1'h1),
.CI(1'h1),
.CO(_02_),
.X(_01_),
.Y(_03_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd20),
.Y_WIDTH(32'd1)
) _05_ (
.A(clockDivider_counter),
.Y(clockDivider_tick)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(20'h00000),
.CLK_POLARITY(1'h1),
.WIDTH(32'd20)
) _06_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_00_),
.Q(clockDivider_counter)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) clockDivider_tickReg_reg /* _07_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(clockDivider_tick),
.Q(clockDivider_tickReg)
);
\$mux #(
.WIDTH(32'd20)
) _08_ (
.A(_03_),
.B(io_config_clockDivider),
.S(clockDivider_tick),
.Y(_00_)
);
\$mux #(
.WIDTH(32'd1)
) _09_ (
.A(tx_io_write_ready),
.B(1'h1),
.S(rx_io_break),
.Y(io_write_ready)
);
\$mux #(
.WIDTH(32'd1)
) _10_ (
.A(io_write_valid),
.B(1'h0),
.S(rx_io_break),
.Y(io_write_thrown_valid)
);
UartCtrlRx rx (
.io_break(rx_io_break),
.io_configFrame_dataLength(io_config_frame_dataLength),
.io_configFrame_parity(io_config_frame_parity),
.io_configFrame_stop(io_config_frame_stop),
.io_error(rx_io_error),
.io_mainClk(io_mainClk),
.io_read_payload(rx_io_read_payload),
.io_read_ready(io_read_ready),
.io_read_valid(rx_io_read_valid),
.io_rts(rx_io_rts),
.io_rxd(io_uart_rxd),
.io_samplingTick(clockDivider_tickReg),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
UartCtrlTx tx (
.io_break(io_writeBreak),
.io_configFrame_dataLength(io_config_frame_dataLength),
.io_configFrame_parity(io_config_frame_parity),
.io_configFrame_stop(io_config_frame_stop),
.io_cts(1'h0),
.io_mainClk(io_mainClk),
.io_samplingTick(clockDivider_tickReg),
.io_txd(tx_io_txd),
.io_write_payload(io_write_payload),
.io_write_ready(tx_io_write_ready),
.io_write_valid(io_write_thrown_valid),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign io_readBreak = rx_io_break;
assign io_readError = rx_io_error;
assign io_read_payload = rx_io_read_payload;
assign io_read_valid = rx_io_read_valid;
assign io_uart_txd = tx_io_txd;
assign io_write_thrown_payload = io_write_payload;
assign io_write_thrown_ready = tx_io_write_ready;
endmodule
module UartCtrlRx(io_configFrame_dataLength, io_configFrame_stop, io_configFrame_parity, io_samplingTick, io_read_valid, io_read_ready, io_read_payload, io_rxd, io_rts, io_error, io_break, io_mainClk, resetCtrl_systemReset);
wire _000_;
wire [2:0] _001_;
wire [2:0] _002_;
wire [6:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [6:0] _012_;
wire [2:0] _013_;
wire [7:0] _014_;
wire [6:0] _015_;
wire [2:0] _016_;
wire [2:0] _017_;
wire [6:0] _018_;
wire [2:0] _019_;
wire [2:0] _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire [4:0] _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire [7:0] _061_;
wire [7:0] _062_;
wire _063_;
wire _064_;
wire [2:0] _065_;
wire [2:0] _066_;
wire [2:0] _067_;
wire [2:0] _068_;
wire [2:0] _069_;
wire [2:0] _070_;
wire [2:0] _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire [7:0] _077_;
wire [7:0] _078_;
wire [2:0] _079_;
wire _080_;
wire _zz_io_rts;
wire [2:0] _zz_when_UartCtrlRx_l139;
wire _zz_when_UartCtrlRx_l139_1;
wire [2:0] bitCounter_value;
wire [2:0] bitTimer_counter;
wire bitTimer_tick;
wire [6:0] break_counter;
wire break_valid;
output io_break;
wire io_break;
input [2:0] io_configFrame_dataLength;
wire [2:0] io_configFrame_dataLength;
input [1:0] io_configFrame_parity;
wire [1:0] io_configFrame_parity;
input io_configFrame_stop;
wire io_configFrame_stop;
output io_error;
wire io_error;
input io_mainClk;
wire io_mainClk;
output [7:0] io_read_payload;
wire [7:0] io_read_payload;
input io_read_ready;
wire io_read_ready;
output io_read_valid;
wire io_read_valid;
output io_rts;
wire io_rts;
input io_rxd;
wire io_rxd;
wire io_rxd_buffercc_io_dataOut;
input io_samplingTick;
wire io_samplingTick;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
wire sampler_samples_0;
wire sampler_samples_1;
wire sampler_samples_2;
wire sampler_synchroniser;
wire sampler_tick;
wire sampler_value;
wire stateMachine_parity;
wire [7:0] stateMachine_shifter;
wire [4:0] stateMachine_state;
wire stateMachine_validReg;
wire when_UartCtrlRx_l103;
wire when_UartCtrlRx_l111;
wire when_UartCtrlRx_l113;
wire when_UartCtrlRx_l125;
wire when_UartCtrlRx_l139;
wire when_UartCtrlRx_l43;
wire when_UartCtrlRx_l69;
wire when_UartCtrlRx_l93;
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd8),
.Y_WIDTH(32'd8)
) _081_ (
.A(stateMachine_shifter),
.B(_061_),
.Y(_014_)
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd7),
.Y_WIDTH(32'd7)
) _082_ (
.A(1'h1),
.B(break_counter),
.BI(1'h0),
.CI(1'h0),
.CO(_018_),
.X(_015_),
.Y(_012_)
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd3)
) _083_ (
.A(1'h1),
.B(bitCounter_value),
.BI(1'h0),
.CI(1'h0),
.CO(_019_),
.X(_016_),
.Y(_013_)
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd3)
) _084_ (
.A(bitTimer_counter),
.B(1'h1),
.BI(1'h1),
.CI(1'h1),
.CO(_020_),
.X(_017_),
.Y(_079_)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(7'h00),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd7)
) _085_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_003_),
.EN(_049_),
.Q(break_counter)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h1),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) sampler_samples_2_reg /* _086_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(sampler_samples_1),
.EN(io_samplingTick),
.Q(sampler_samples_2)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h1),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) sampler_samples_1_reg /* _087_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_rxd_buffercc_io_dataOut),
.EN(io_samplingTick),
.Q(sampler_samples_1)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd8)
) _088_ (
.CLK(io_mainClk),
.D(_062_),
.EN(_050_),
.Q(stateMachine_shifter)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _089_ (
.A(_038_),
.B(stateMachine_state[1]),
.Y(_021_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _090_ (
.A(_039_),
.B(stateMachine_state[1]),
.Y(_022_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _091_ (
.A(_040_),
.B(stateMachine_state[3]),
.Y(_023_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _092_ (
.A(_041_),
.B(stateMachine_state[4]),
.Y(_024_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _093_ (
.A(_042_),
.B(stateMachine_state[0]),
.Y(_025_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _094_ (
.A(_043_),
.B(stateMachine_state[1]),
.Y(_026_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _095_ (
.A(_044_),
.B(stateMachine_state[1]),
.Y(_027_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _096_ (
.A(_045_),
.B(stateMachine_state[2]),
.Y(_028_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _097_ (
.A(_046_),
.B(stateMachine_state[4]),
.Y(_029_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _098_ (
.A(_038_),
.B(stateMachine_state[3]),
.Y(_030_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _099_ (
.A(_044_),
.B(stateMachine_state[2]),
.Y(_031_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _100_ (
.A(_047_),
.B(stateMachine_state[2]),
.Y(_032_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _101_ (
.A(_044_),
.B(stateMachine_state[3]),
.Y(_033_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _102_ (
.A(when_UartCtrlRx_l93),
.B(stateMachine_state[0]),
.Y(_034_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _103_ (
.A(_044_),
.B(stateMachine_state[4]),
.Y(_035_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _104_ (
.A(_048_),
.B(stateMachine_state[2]),
.Y(_036_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _105_ (
.A({ _021_, _022_, _023_, _024_, _025_ }),
.Y(_037_[0])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.Y_WIDTH(32'd1)
) _106_ (
.A({ _029_, _028_, _027_, _026_ }),
.Y(_037_[1])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _107_ (
.A({ _032_, _031_, _030_ }),
.Y(_037_[2])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _108_ (
.A({ _034_, _033_ }),
.Y(_037_[3])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _109_ (
.A({ _036_, _035_ }),
.Y(_037_[4])
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(5'h01),
.CLK_POLARITY(1'h1),
.WIDTH(32'd5)
) _110_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_037_),
.Q(stateMachine_state)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _111_ (
.A({ when_UartCtrlRx_l139, bitTimer_tick, sampler_value }),
.B(3'h7),
.Y(_039_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _112_ (
.A({ bitTimer_tick, sampler_value }),
.B(2'h3),
.Y(_040_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _113_ (
.A({ when_UartCtrlRx_l125, bitTimer_tick }),
.B(1'h1),
.Y(_041_)
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _114_ (
.A(when_UartCtrlRx_l93),
.Y(_042_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _115_ (
.A({ when_UartCtrlRx_l139, bitTimer_tick, sampler_value }),
.B(2'h3),
.Y(_043_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _116_ (
.A({ when_UartCtrlRx_l113, when_UartCtrlRx_l111, bitTimer_tick }),
.B(3'h7),
.Y(_045_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _117_ (
.A({ when_UartCtrlRx_l125, bitTimer_tick }),
.B(2'h3),
.Y(_046_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _118_ (
.A({ bitTimer_tick, sampler_value }),
.B(2'h2),
.Y(_038_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _119_ (
.A({ when_UartCtrlRx_l111, bitTimer_tick }),
.B(1'h1),
.Y(_047_)
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _120_ (
.A(bitTimer_tick),
.Y(_044_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _121_ (
.A({ when_UartCtrlRx_l113, when_UartCtrlRx_l111, bitTimer_tick }),
.B(2'h3),
.Y(_048_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _122_ (
.A({ when_UartCtrlRx_l69, sampler_value }),
.Y(_049_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _123_ (
.A({ bitTimer_tick, stateMachine_state[2] }),
.Y(_050_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _124_ (
.A({ stateMachine_state[3:2], stateMachine_state[0] }),
.Y(_051_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _125_ (
.A(stateMachine_state[4:3]),
.Y(_052_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _126_ (
.A(bitTimer_counter),
.Y(when_UartCtrlRx_l43)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd7),
.B_SIGNED(32'd0),
.B_WIDTH(32'd7),
.Y_WIDTH(32'd1)
) _127_ (
.A(break_counter),
.B(7'h41),
.Y(break_valid)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _128_ (
.A(bitCounter_value),
.B(io_configFrame_dataLength),
.Y(when_UartCtrlRx_l111)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _129_ (
.A(io_configFrame_parity),
.Y(when_UartCtrlRx_l113)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _130_ (
.A(stateMachine_parity),
.B(sampler_value),
.Y(when_UartCtrlRx_l125)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _131_ (
.A(bitCounter_value),
.B(_zz_when_UartCtrlRx_l139_1),
.Y(when_UartCtrlRx_l139)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _132_ (
.A(io_configFrame_parity),
.B(2'h2),
.Y(_053_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _133_ (
.A(io_samplingTick),
.B(_058_),
.Y(when_UartCtrlRx_l69)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _134_ (
.A(sampler_tick),
.B(_059_),
.Y(_054_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _135_ (
.A(_054_),
.B(_058_),
.Y(when_UartCtrlRx_l93)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _136_ (
.A(io_rxd_buffercc_io_dataOut),
.B(sampler_samples_1),
.Y(_055_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _137_ (
.A(io_rxd_buffercc_io_dataOut),
.B(sampler_samples_2),
.Y(_056_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _138_ (
.A(sampler_samples_1),
.B(sampler_samples_2),
.Y(_057_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _139_ (
.A(break_valid),
.Y(_058_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _140_ (
.A(sampler_value),
.Y(_059_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _141_ (
.A(io_read_ready),
.Y(_000_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _142_ (
.A(_055_),
.B(_056_),
.Y(_060_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _143_ (
.A(_060_),
.B(_057_),
.Y(_004_)
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.Y_WIDTH(32'd8)
) _144_ (
.A(_077_),
.Y(_061_)
);
\$or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd8),
.Y_WIDTH(32'd8)
) _145_ (
.A(_014_),
.B(_078_),
.Y(_062_)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd3)
) _146_ (
.CLK(io_mainClk),
.D(_002_),
.Q(bitTimer_counter)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd3)
) _147_ (
.CLK(io_mainClk),
.D(_001_),
.Q(bitCounter_value)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) stateMachine_parity_reg /* _148_ */ (
.CLK(io_mainClk),
.D(_005_),
.Q(stateMachine_parity)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) _zz_io_rts_reg /* _149_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_000_),
.Q(_zz_io_rts)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h1),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) sampler_value_reg /* _150_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_004_),
.Q(sampler_value)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) sampler_tick_reg /* _151_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(io_samplingTick),
.Q(sampler_tick)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) stateMachine_validReg_reg /* _152_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_006_),
.Q(stateMachine_validReg)
);
\$mux #(
.WIDTH(32'd1)
) _153_ (
.A(stateMachine_parity),
.B(_080_),
.S(bitTimer_tick),
.Y(_063_)
);
\$mux #(
.WIDTH(32'd1)
) _154_ (
.A(_063_),
.B(_053_),
.S(bitTimer_tick),
.Y(_064_)
);
\$mux #(
.WIDTH(32'd1)
) _155_ (
.A(_063_),
.B(_064_),
.S(stateMachine_state[3]),
.Y(_005_)
);
\$mux #(
.WIDTH(32'd3)
) _156_ (
.A(bitCounter_value),
.B(_013_),
.S(bitTimer_tick),
.Y(_065_)
);
\$mux #(
.WIDTH(32'd3)
) _157_ (
.A(_065_),
.B(3'h0),
.S(bitTimer_tick),
.Y(_066_)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd3)
) _158_ (
.A(_065_),
.B({ _068_, _066_ }),
.S({ stateMachine_state[2], _052_ }),
.Y(_001_)
);
\$mux #(
.WIDTH(32'd3)
) _159_ (
.A(_065_),
.B(3'h0),
.S(when_UartCtrlRx_l111),
.Y(_067_)
);
\$mux #(
.WIDTH(32'd3)
) _160_ (
.A(_065_),
.B(_067_),
.S(bitTimer_tick),
.Y(_068_)
);
\$mux #(
.WIDTH(32'd3)
) _161_ (
.A(_079_),
.B(3'h4),
.S(when_UartCtrlRx_l43),
.Y(_069_)
);
\$mux #(
.WIDTH(32'd3)
) _162_ (
.A(bitTimer_counter),
.B(_069_),
.S(sampler_tick),
.Y(_070_)
);
\$mux #(
.WIDTH(32'd3)
) _163_ (
.A(_070_),
.B(3'h1),
.S(when_UartCtrlRx_l93),
.Y(_071_)
);
\$mux #(
.WIDTH(32'd3)
) _164_ (
.A(_070_),
.B(_071_),
.S(stateMachine_state[0]),
.Y(_002_)
);
\$mux #(
.WIDTH(32'd1)
) _165_ (
.A(1'h0),
.B(1'h1),
.S(when_UartCtrlRx_l125),
.Y(_072_)
);
\$mux #(
.WIDTH(32'd1)
) _166_ (
.A(1'h0),
.B(_072_),
.S(bitTimer_tick),
.Y(_073_)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd1)
) _167_ (
.A(1'h0),
.B({ _076_, _073_ }),
.S({ stateMachine_state[2], stateMachine_state[4] }),
.Y(_006_)
);
\$mux #(
.WIDTH(32'd1)
) _168_ (
.A(1'h0),
.B(1'h1),
.S(when_UartCtrlRx_l113),
.Y(_074_)
);
\$mux #(
.WIDTH(32'd1)
) _169_ (
.A(1'h0),
.B(_074_),
.S(when_UartCtrlRx_l111),
.Y(_075_)
);
\$mux #(
.WIDTH(32'd1)
) _170_ (
.A(1'h0),
.B(_075_),
.S(bitTimer_tick),
.Y(_076_)
);
\$mux #(
.WIDTH(32'd7)
) _171_ (
.A(_012_),
.B(7'h00),
.S(sampler_value),
.Y(_003_)
);
\$mux #(
.WIDTH(32'd1)
) _172_ (
.A(1'h0),
.B(1'h1),
.S(when_UartCtrlRx_l43),
.Y(_007_)
);
\$mux #(
.WIDTH(32'd1)
) _173_ (
.A(1'h0),
.B(_007_),
.S(sampler_tick),
.Y(bitTimer_tick)
);
\$mux #(
.WIDTH(32'd1)
) _174_ (
.A(1'h1),
.B(1'h0),
.S(sampler_value),
.Y(_011_)
);
\$mux #(
.WIDTH(32'd1)
) _175_ (
.A(1'h0),
.B(_011_),
.S(bitTimer_tick),
.Y(_010_)
);
\$mux #(
.WIDTH(32'd1)
) _176_ (
.A(1'h1),
.B(1'h0),
.S(when_UartCtrlRx_l125),
.Y(_009_)
);
\$mux #(
.WIDTH(32'd1)
) _177_ (
.A(1'h0),
.B(_009_),
.S(bitTimer_tick),
.Y(_008_)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd1)
) _178_ (
.A(_010_),
.B({ 1'h0, _008_ }),
.S({ _051_, stateMachine_state[4] }),
.Y(io_error)
);
\$shl #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd8)
) _179_ (
.A(1'h1),
.B(bitCounter_value),
.Y(_077_)
);
\$shl #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd8)
) _180_ (
.A(sampler_value),
.B(bitCounter_value),
.Y(_078_)
);
\$mux #(
.WIDTH(32'd1)
) _181_ (
.A(1'h0),
.B(1'h1),
.S(io_configFrame_stop),
.Y(_zz_when_UartCtrlRx_l139_1)
);
\$xor #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _182_ (
.A(stateMachine_parity),
.B(sampler_value),
.Y(_080_)
);
BufferCC io_rxd_buffercc (
.io_dataIn(io_rxd),
.io_dataOut(io_rxd_buffercc_io_dataOut),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign _zz_when_UartCtrlRx_l139 = { 2'h0, _zz_when_UartCtrlRx_l139_1 };
assign io_break = break_valid;
assign io_read_payload = stateMachine_shifter;
assign io_read_valid = stateMachine_validReg;
assign io_rts = _zz_io_rts;
assign sampler_samples_0 = io_rxd_buffercc_io_dataOut;
assign sampler_synchroniser = io_rxd_buffercc_io_dataOut;
assign when_UartCtrlRx_l103 = sampler_value;
endmodule
module UartCtrlTx(io_configFrame_dataLength, io_configFrame_stop, io_configFrame_parity, io_samplingTick, io_write_valid, io_write_ready, io_write_payload, io_cts, io_txd, io_break, io_mainClk, resetCtrl_systemReset);
wire _000_;
wire _001_;
wire [2:0] _002_;
wire _003_;
wire _004_;
wire [2:0] _005_;
wire [2:0] _006_;
wire [2:0] _007_;
wire [2:0] _008_;
wire [2:0] _009_;
wire [2:0] _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire [4:0] _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire [2:0] _039_;
wire [2:0] _040_;
wire [2:0] _041_;
wire [2:0] _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire [2:0] _zz_clockDivider_counter_valueNext;
wire _zz_clockDivider_counter_valueNext_1;
wire _zz_io_txd;
wire [2:0] _zz_when_UartCtrlTx_l93;
wire _zz_when_UartCtrlTx_l93_1;
wire [2:0] clockDivider_counter_value;
wire [2:0] clockDivider_counter_valueNext;
wire clockDivider_counter_willClear;
wire clockDivider_counter_willIncrement;
wire clockDivider_counter_willOverflow;
wire clockDivider_counter_willOverflowIfInc;
input io_break;
wire io_break;
input [2:0] io_configFrame_dataLength;
wire [2:0] io_configFrame_dataLength;
input [1:0] io_configFrame_parity;
wire [1:0] io_configFrame_parity;
input io_configFrame_stop;
wire io_configFrame_stop;
input io_cts;
wire io_cts;
input io_mainClk;
wire io_mainClk;
input io_samplingTick;
wire io_samplingTick;
output io_txd;
wire io_txd;
input [7:0] io_write_payload;
wire [7:0] io_write_payload;
output io_write_ready;
wire io_write_ready;
input io_write_valid;
wire io_write_valid;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
wire stateMachine_parity;
wire [4:0] stateMachine_state;
wire stateMachine_txd;
wire [2:0] tickCounter_value;
wire when_UartCtrlTx_l58;
wire when_UartCtrlTx_l73;
wire when_UartCtrlTx_l76;
wire when_UartCtrlTx_l93;
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd3)
) _047_ (
.A(clockDivider_counter_willIncrement),
.B(clockDivider_counter_value),
.BI(1'h0),
.CI(1'h0),
.CO(_009_),
.X(_007_),
.Y(_005_)
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd3)
) _048_ (
.A(1'h1),
.B(tickCounter_value),
.BI(1'h0),
.CI(1'h0),
.CO(_010_),
.X(_008_),
.Y(_006_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _049_ (
.A(_026_),
.B(stateMachine_state[1]),
.Y(_011_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _050_ (
.A(_027_),
.B(stateMachine_state[0]),
.Y(_012_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _051_ (
.A(_028_),
.B(stateMachine_state[1]),
.Y(_013_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _052_ (
.A(_029_),
.B(stateMachine_state[2]),
.Y(_014_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _053_ (
.A(_030_),
.B(stateMachine_state[1]),
.Y(_015_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _054_ (
.A(clockDivider_counter_willOverflow),
.B(stateMachine_state[4]),
.Y(_016_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _055_ (
.A(_028_),
.B(stateMachine_state[2]),
.Y(_017_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _056_ (
.A(_031_),
.B(stateMachine_state[2]),
.Y(_018_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _057_ (
.A(clockDivider_counter_willOverflow),
.B(stateMachine_state[3]),
.Y(_019_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _058_ (
.A(_032_),
.B(stateMachine_state[1]),
.Y(_020_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _059_ (
.A(_028_),
.B(stateMachine_state[3]),
.Y(_021_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _060_ (
.A(when_UartCtrlTx_l58),
.B(stateMachine_state[0]),
.Y(_022_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _061_ (
.A(_028_),
.B(stateMachine_state[4]),
.Y(_023_)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _062_ (
.A(_033_),
.B(stateMachine_state[2]),
.Y(_024_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _063_ (
.A({ _012_, _011_ }),
.Y(_025_[0])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.Y_WIDTH(32'd1)
) _064_ (
.A({ _016_, _015_, _014_, _013_ }),
.Y(_025_[1])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _065_ (
.A({ _019_, _018_, _017_ }),
.Y(_025_[2])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _066_ (
.A({ _021_, _020_, _022_ }),
.Y(_025_[3])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _067_ (
.A({ _024_, _023_ }),
.Y(_025_[4])
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(5'h01),
.CLK_POLARITY(1'h1),
.WIDTH(32'd5)
) _068_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_025_),
.Q(stateMachine_state)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _069_ (
.A({ when_UartCtrlTx_l93, clockDivider_counter_willOverflow, io_write_valid }),
.B(3'h6),
.Y(_026_)
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _070_ (
.A(when_UartCtrlTx_l58),
.Y(_027_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _071_ (
.A({ when_UartCtrlTx_l76, when_UartCtrlTx_l73, clockDivider_counter_willOverflow }),
.B(3'h7),
.Y(_029_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _072_ (
.A({ when_UartCtrlTx_l93, clockDivider_counter_willOverflow }),
.B(1'h1),
.Y(_030_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _073_ (
.A({ when_UartCtrlTx_l73, clockDivider_counter_willOverflow }),
.B(1'h1),
.Y(_031_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _074_ (
.A({ when_UartCtrlTx_l93, clockDivider_counter_willOverflow, io_write_valid }),
.B(3'h7),
.Y(_032_)
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _075_ (
.A(clockDivider_counter_willOverflow),
.Y(_028_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _076_ (
.A({ when_UartCtrlTx_l76, when_UartCtrlTx_l73, clockDivider_counter_willOverflow }),
.B(2'h3),
.Y(_033_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _077_ (
.A(stateMachine_state[4:3]),
.Y(_034_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _078_ (
.A(clockDivider_counter_value),
.B(3'h4),
.Y(clockDivider_counter_willOverflowIfInc)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _079_ (
.A(tickCounter_value),
.B(io_configFrame_dataLength),
.Y(when_UartCtrlTx_l73)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _080_ (
.A(io_configFrame_parity),
.Y(when_UartCtrlTx_l76)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _081_ (
.A(tickCounter_value),
.B(_zz_when_UartCtrlTx_l93_1),
.Y(when_UartCtrlTx_l93)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _082_ (
.A(io_configFrame_parity),
.B(2'h2),
.Y(_035_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _083_ (
.A(clockDivider_counter_willOverflowIfInc),
.B(clockDivider_counter_willIncrement),
.Y(clockDivider_counter_willOverflow)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _084_ (
.A(io_write_valid),
.B(_037_),
.Y(_036_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _085_ (
.A(_036_),
.B(clockDivider_counter_willOverflow),
.Y(when_UartCtrlTx_l58)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _086_ (
.A(stateMachine_txd),
.B(_038_),
.Y(_000_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _087_ (
.A(io_cts),
.Y(_037_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _088_ (
.A(io_break),
.Y(_038_)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) stateMachine_parity_reg /* _089_ */ (
.CLK(io_mainClk),
.D(_001_),
.Q(stateMachine_parity)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd3)
) _090_ (
.CLK(io_mainClk),
.D(_002_),
.Q(tickCounter_value)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(3'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd3)
) _091_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(clockDivider_counter_valueNext),
.Q(clockDivider_counter_value)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h1),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) _zz_io_txd_reg /* _092_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_000_),
.Q(_zz_io_txd)
);
\$mux #(
.WIDTH(32'd3)
) _093_ (
.A(tickCounter_value),
.B(_006_),
.S(clockDivider_counter_willOverflow),
.Y(_039_)
);
\$mux #(
.WIDTH(32'd3)
) _094_ (
.A(_039_),
.B(3'h0),
.S(clockDivider_counter_willOverflow),
.Y(_040_)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd3)
) _095_ (
.A(_039_),
.B({ _042_, _040_ }),
.S({ stateMachine_state[2], _034_ }),
.Y(_002_)
);
\$mux #(
.WIDTH(32'd3)
) _096_ (
.A(_039_),
.B(3'h0),
.S(when_UartCtrlTx_l73),
.Y(_041_)
);
\$mux #(
.WIDTH(32'd3)
) _097_ (
.A(_039_),
.B(_041_),
.S(clockDivider_counter_willOverflow),
.Y(_042_)
);
\$mux #(
.WIDTH(32'd1)
) _098_ (
.A(stateMachine_parity),
.B(_046_),
.S(clockDivider_counter_willOverflow),
.Y(_043_)
);
\$mux #(
.WIDTH(32'd1)
) _099_ (
.A(_043_),
.B(_035_),
.S(clockDivider_counter_willOverflow),
.Y(_044_)
);
\$mux #(
.WIDTH(32'd1)
) _100_ (
.A(_043_),
.B(_044_),
.S(stateMachine_state[3]),
.Y(_001_)
);
\$mux #(
.WIDTH(32'd1)
) _101_ (
.A(io_break),
.B(1'h1),
.S(when_UartCtrlTx_l73),
.Y(_004_)
);
\$mux #(
.WIDTH(32'd1)
) _102_ (
.A(io_break),
.B(_004_),
.S(clockDivider_counter_willOverflow),
.Y(_003_)
);
\$mux #(
.WIDTH(32'd1)
) _103_ (
.A(io_break),
.B(_003_),
.S(stateMachine_state[2]),
.Y(io_write_ready)
);
\$pmux #(
.S_WIDTH(32'd3),
.WIDTH(32'd1)
) _104_ (
.A(1'h1),
.B({ 1'h0, _045_, stateMachine_parity }),
.S({ stateMachine_state[3:2], stateMachine_state[4] }),
.Y(stateMachine_txd)
);
\$mux #(
.WIDTH(32'd3)
) _105_ (
.A(_005_),
.B(3'h0),
.S(clockDivider_counter_willOverflow),
.Y(clockDivider_counter_valueNext)
);
\$mux #(
.WIDTH(32'd1)
) _106_ (
.A(1'h0),
.B(1'h1),
.S(io_samplingTick),
.Y(clockDivider_counter_willIncrement)
);
\$shiftx #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd8),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _107_ (
.A(io_write_payload),
.B(tickCounter_value),
.Y(_045_)
);
\$mux #(
.WIDTH(32'd1)
) _108_ (
.A(1'h0),
.B(1'h1),
.S(io_configFrame_stop),
.Y(_zz_when_UartCtrlTx_l93_1)
);
\$xor #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _109_ (
.A(stateMachine_parity),
.B(stateMachine_txd),
.Y(_046_)
);
assign _zz_clockDivider_counter_valueNext = { 2'h0, clockDivider_counter_willIncrement };
assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement;
assign _zz_when_UartCtrlTx_l93 = { 2'h0, _zz_when_UartCtrlTx_l93_1 };
assign clockDivider_counter_willClear = 1'h0;
assign io_txd = _zz_io_txd;
endmodule
module VexRiscv(iBus_cmd_valid, iBus_cmd_ready, iBus_cmd_payload_pc, iBus_rsp_valid, iBus_rsp_payload_error, iBus_rsp_payload_inst, timerInterrupt, externalInterrupt, softwareInterrupt, debug_bus_cmd_valid, debug_bus_cmd_ready, debug_bus_cmd_payload_wr, debug_bus_cmd_payload_address, debug_bus_cmd_payload_data, debug_bus_rsp_data, debug_resetOut, dBus_cmd_valid, dBus_cmd_ready, dBus_cmd_payload_wr, dBus_cmd_payload_address, dBus_cmd_payload_data
, dBus_cmd_payload_size, dBus_rsp_ready, dBus_rsp_error, dBus_rsp_data, io_mainClk, resetCtrl_systemReset, resetCtrl_mainClkReset);
wire [31:0] _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire [1:0] _005_;
wire _006_;
wire _007_;
wire _008_;
wire [31:0] _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire [2:0] _014_;
wire _015_;
wire _016_;
wire [31:0] _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire [2:0] _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire [31:0] _029_;
wire _030_;
wire [31:0] _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire [31:0] _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire [31:0] _059_;
wire [12:0] _060_;
wire [31:0] _061_;
wire [2:0] _062_;
wire [4:0] _063_;
wire [31:0] _064_;
wire [31:0] _065_;
wire _066_;
wire [2:0] _067_;
wire [4:0] _068_;
wire [31:0] _069_;
wire [31:0] _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire [2:0] _102_;
wire _103_;
wire [6:0] _104_;
wire _105_;
wire _106_;
wire _107_;
wire [1:0] _108_;
wire [31:0] _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire [31:0] _176_;
wire [31:0] _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire [1:0] _205_;
wire [1:0] _206_;
wire _207_;
wire [1:0] _208_;
wire [1:0] _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire [2:0] _243_;
wire [4:0] _244_;
wire [31:0] _245_;
wire _246_;
wire [31:0] _247_;
wire [31:0] BranchPlugin_jumpInterface_payload;
wire BranchPlugin_jumpInterface_valid;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_csrMapping_allowCsrSignal;
wire [31:0] CsrPlugin_csrMapping_readDataInit;
wire [31:0] CsrPlugin_csrMapping_readDataSignal;
wire [12:0] CsrPlugin_csrMapping_writeDataSignal;
wire CsrPlugin_exception;
wire CsrPlugin_hadException;
wire CsrPlugin_inWfi;
wire CsrPlugin_interruptJump;
wire [3:0] CsrPlugin_interrupt_code;
wire [1:0] CsrPlugin_interrupt_targetPrivilege;
wire CsrPlugin_interrupt_valid;
wire [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_jumpInterface_valid;
wire CsrPlugin_lastStageWasWfi;
wire [3:0] CsrPlugin_mcause_exceptionCode;
wire CsrPlugin_mcause_interrupt;
wire [31:0] CsrPlugin_mepc;
wire CsrPlugin_mie_MEIE;
wire CsrPlugin_mie_MSIE;
wire CsrPlugin_mie_MTIE;
wire CsrPlugin_mip_MEIP;
wire CsrPlugin_mip_MSIP;
wire CsrPlugin_mip_MTIP;
wire [1:0] CsrPlugin_misa_base;
wire [25:0] CsrPlugin_misa_extensions;
wire CsrPlugin_mstatus_MIE;
wire CsrPlugin_mstatus_MPIE;
wire [1:0] CsrPlugin_mstatus_MPP;
wire [29:0] CsrPlugin_mtvec_base;
wire [1:0] CsrPlugin_mtvec_mode;
wire CsrPlugin_pipelineLiberator_active;
wire CsrPlugin_pipelineLiberator_done;
wire CsrPlugin_pipelineLiberator_pcValids_0;
wire CsrPlugin_pipelineLiberator_pcValids_1;
wire CsrPlugin_pipelineLiberator_pcValids_2;
wire [1:0] CsrPlugin_privilege;
wire [1:0] CsrPlugin_targetPrivilege;
wire [3:0] CsrPlugin_trapCause;
wire [29:0] CsrPlugin_xtvec_base;
wire DebugPlugin_allowEBreak;
wire [31:0] DebugPlugin_busReadDataReg;
wire DebugPlugin_debugUsed;
wire DebugPlugin_disableEbreak;
wire DebugPlugin_haltIt;
wire DebugPlugin_haltedByBreak;
wire DebugPlugin_isPipBusy;
wire DebugPlugin_resetIt;
wire DebugPlugin_resetIt_regNext;
wire DebugPlugin_stepIt;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire HazardSimplePlugin_src0Hazard;
wire HazardSimplePlugin_src1Hazard;
wire [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
wire HazardSimplePlugin_writeBackBuffer_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
wire HazardSimplePlugin_writeBackWrites_valid;
wire IBusSimplePlugin_cmdFork_canEmit;
wire IBusSimplePlugin_cmd_fire;
wire [31:0] IBusSimplePlugin_cmd_payload_pc;
wire IBusSimplePlugin_cmd_ready;
wire IBusSimplePlugin_cmd_valid;
wire IBusSimplePlugin_externalFlush;
wire IBusSimplePlugin_fetchPc_booted;
wire IBusSimplePlugin_fetchPc_correction;
wire IBusSimplePlugin_fetchPc_inc;
wire IBusSimplePlugin_fetchPc_output_fire_1;
wire [31:0] IBusSimplePlugin_fetchPc_output_payload;
wire IBusSimplePlugin_fetchPc_output_ready;
wire IBusSimplePlugin_fetchPc_output_valid;
wire [31:0] IBusSimplePlugin_fetchPc_pc;
wire [31:0] IBusSimplePlugin_fetchPc_pcReg;
wire IBusSimplePlugin_fetchPc_pcRegPropagate;
wire IBusSimplePlugin_fetcherHalt;
wire IBusSimplePlugin_iBusRsp_flush;
wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc;
wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst;
wire IBusSimplePlugin_iBusRsp_output_ready;
wire IBusSimplePlugin_iBusRsp_output_valid;
wire IBusSimplePlugin_iBusRsp_redoFetch;
wire IBusSimplePlugin_iBusRsp_stages_0_halt;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload;
wire IBusSimplePlugin_iBusRsp_stages_0_input_ready;
wire IBusSimplePlugin_iBusRsp_stages_0_input_valid;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload;
wire IBusSimplePlugin_iBusRsp_stages_0_output_ready;
wire IBusSimplePlugin_iBusRsp_stages_0_output_valid;
wire IBusSimplePlugin_iBusRsp_stages_1_halt;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload;
wire IBusSimplePlugin_iBusRsp_stages_1_input_ready;
wire IBusSimplePlugin_iBusRsp_stages_1_input_valid;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload;
wire IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_ready;
wire IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload;
wire IBusSimplePlugin_iBusRsp_stages_1_output_ready;
wire IBusSimplePlugin_iBusRsp_stages_1_output_valid;
wire IBusSimplePlugin_iBusRsp_stages_2_halt;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_input_payload;
wire IBusSimplePlugin_iBusRsp_stages_2_input_ready;
wire IBusSimplePlugin_iBusRsp_stages_2_input_valid;
wire [31:0] IBusSimplePlugin_iBusRsp_stages_2_output_payload;
wire IBusSimplePlugin_iBusRsp_stages_2_output_ready;
wire IBusSimplePlugin_iBusRsp_stages_2_output_valid;
wire IBusSimplePlugin_incomingInstruction;
wire [31:0] IBusSimplePlugin_injectionPort_payload;
wire IBusSimplePlugin_injectionPort_ready;
wire IBusSimplePlugin_injectionPort_valid;
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc;
wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
wire IBusSimplePlugin_injector_decodeInput_ready;
wire IBusSimplePlugin_injector_decodeInput_valid;
wire [31:0] IBusSimplePlugin_jump_pcLoad_payload;
wire IBusSimplePlugin_jump_pcLoad_valid;
wire IBusSimplePlugin_pending_dec;
wire IBusSimplePlugin_pending_inc;
wire [2:0] IBusSimplePlugin_pending_next;
wire [2:0] IBusSimplePlugin_pending_value;
wire IBusSimplePlugin_rspJoin_exceptionDetected;
wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc;
wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst;
wire IBusSimplePlugin_rspJoin_join_fire;
wire IBusSimplePlugin_rspJoin_join_fire_1;
wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc;
wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst;
wire IBusSimplePlugin_rspJoin_join_ready;
wire IBusSimplePlugin_rspJoin_join_valid;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid;
wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready;
wire [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter;
wire IBusSimplePlugin_rspJoin_rspBuffer_flush;
wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error;
wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst;
wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready;
wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid;
wire _zz_1;
wire _zz_2;
wire [12:0] _zz_CsrPlugin_csrMapping_readDataInit;
wire [11:0] _zz_CsrPlugin_csrMapping_readDataInit_1;
wire [11:0] _zz_CsrPlugin_csrMapping_readDataInit_2;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3;
wire [12:0] _zz_CsrPlugin_csrMapping_writeDataSignal;
wire [31:0] _zz_IBusSimplePlugin_fetchPc_pc;
wire [2:0] _zz_IBusSimplePlugin_fetchPc_pc_1;
wire _zz_IBusSimplePlugin_iBusRsp_output_valid;
wire _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1;
wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2;
wire _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready;
wire [31:0] _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload;
wire _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire _zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready;
wire [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_pc;
wire [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
wire _zz_IBusSimplePlugin_injector_decodeInput_valid;
wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload;
wire _zz_IBusSimplePlugin_jump_pcLoad_payload_1;
wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload_2;
wire [2:0] _zz_IBusSimplePlugin_pending_next_1;
wire _zz_IBusSimplePlugin_pending_next_2;
wire [2:0] _zz_IBusSimplePlugin_pending_next_3;
wire _zz_IBusSimplePlugin_pending_next_4;
wire [2:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter;
wire _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1;
wire [31:0] _zz_RegFilePlugin_regFile_port0;
wire [31:0] _zz_RegFilePlugin_regFile_port1;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_1;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_10;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_11;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_12;
wire _zz__zz_decode_BRANCH_CTRL_2_13;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_14;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_15;
wire [18:0] _zz__zz_decode_BRANCH_CTRL_2_16;
wire _zz__zz_decode_BRANCH_CTRL_2_17;
wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_18;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_19;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_2;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_20;
wire _zz__zz_decode_BRANCH_CTRL_2_21;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_22;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_23;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_24;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_25;
wire _zz__zz_decode_BRANCH_CTRL_2_26;
wire [14:0] _zz__zz_decode_BRANCH_CTRL_2_27;
wire _zz__zz_decode_BRANCH_CTRL_2_28;
wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_29;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_3;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_30;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_31;
wire _zz__zz_decode_BRANCH_CTRL_2_32;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_33;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_34;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_35;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_36;
wire _zz__zz_decode_BRANCH_CTRL_2_37;
wire _zz__zz_decode_BRANCH_CTRL_2_39;
wire _zz__zz_decode_BRANCH_CTRL_2_4;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_41;
wire [10:0] _zz__zz_decode_BRANCH_CTRL_2_42;
wire _zz__zz_decode_BRANCH_CTRL_2_43;
wire _zz__zz_decode_BRANCH_CTRL_2_44;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_45;
wire _zz__zz_decode_BRANCH_CTRL_2_46;
wire _zz__zz_decode_BRANCH_CTRL_2_47;
wire _zz__zz_decode_BRANCH_CTRL_2_48;
wire [4:0] _zz__zz_decode_BRANCH_CTRL_2_49;
wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_5;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_50;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_51;
wire _zz__zz_decode_BRANCH_CTRL_2_52;
wire _zz__zz_decode_BRANCH_CTRL_2_53;
wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_54;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_55;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_56;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_57;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_58;
wire [6:0] _zz__zz_decode_BRANCH_CTRL_2_59;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_6;
wire [1:0] _zz__zz_decode_BRANCH_CTRL_2_60;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_61;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_62;
wire _zz__zz_decode_BRANCH_CTRL_2_63;
wire _zz__zz_decode_BRANCH_CTRL_2_64;
wire _zz__zz_decode_BRANCH_CTRL_2_65;
wire _zz__zz_decode_BRANCH_CTRL_2_66;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_67;
wire [2:0] _zz__zz_decode_BRANCH_CTRL_2_68;
wire _zz__zz_decode_BRANCH_CTRL_2_69;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_7;
wire [3:0] _zz__zz_decode_BRANCH_CTRL_2_70;
wire _zz__zz_decode_BRANCH_CTRL_2_71;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_72;
wire _zz__zz_decode_BRANCH_CTRL_2_73;
wire _zz__zz_decode_BRANCH_CTRL_2_74;
wire _zz__zz_decode_BRANCH_CTRL_2_75;
wire _zz__zz_decode_BRANCH_CTRL_2_76;
wire _zz__zz_decode_BRANCH_CTRL_2_77;
wire _zz__zz_decode_BRANCH_CTRL_2_78;
wire _zz__zz_decode_BRANCH_CTRL_2_79;
wire _zz__zz_decode_BRANCH_CTRL_2_8;
wire _zz__zz_decode_BRANCH_CTRL_2_80;
wire _zz__zz_decode_BRANCH_CTRL_2_81;
wire _zz__zz_decode_BRANCH_CTRL_2_82;
wire [31:0] _zz__zz_decode_BRANCH_CTRL_2_9;
wire [2:0] _zz__zz_decode_SRC1_1;
wire [4:0] _zz__zz_decode_SRC1_1_1;
wire [11:0] _zz__zz_decode_SRC2_4;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz__zz_execute_REGFILE_WRITE_DATA;
wire [31:0] _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1;
wire [32:0] _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1;
wire [31:0] _zz_dBus_cmd_payload_data;
wire _zz_dBus_cmd_valid;
wire [1:0] _zz_decode_ALU_BITWISE_CTRL;
wire [1:0] _zz_decode_ALU_BITWISE_CTRL_1;
wire [1:0] _zz_decode_ALU_BITWISE_CTRL_2;
wire [1:0] _zz_decode_ALU_CTRL;
wire [1:0] _zz_decode_ALU_CTRL_1;
wire [1:0] _zz_decode_ALU_CTRL_2;
wire [1:0] _zz_decode_BRANCH_CTRL;
wire [1:0] _zz_decode_BRANCH_CTRL_1;
wire [25:0] _zz_decode_BRANCH_CTRL_2;
wire _zz_decode_BRANCH_CTRL_3;
wire _zz_decode_BRANCH_CTRL_4;
wire _zz_decode_BRANCH_CTRL_5;
wire _zz_decode_BRANCH_CTRL_6;
wire _zz_decode_BRANCH_CTRL_7;
wire _zz_decode_BRANCH_CTRL_8;
wire [1:0] _zz_decode_BRANCH_CTRL_9;
wire _zz_decode_ENV_CTRL;
wire _zz_decode_ENV_CTRL_1;
wire _zz_decode_ENV_CTRL_2;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [1:0] _zz_decode_SHIFT_CTRL;
wire [1:0] _zz_decode_SHIFT_CTRL_1;
wire [1:0] _zz_decode_SHIFT_CTRL_2;
wire [31:0] _zz_decode_SRC1;
wire [31:0] _zz_decode_SRC1_1;
wire [1:0] _zz_decode_SRC1_CTRL;
wire [1:0] _zz_decode_SRC1_CTRL_1;
wire [1:0] _zz_decode_SRC1_CTRL_2;
wire [31:0] _zz_decode_SRC2;
wire [31:0] _zz_decode_SRC2_1;
wire _zz_decode_SRC2_2;
wire [19:0] _zz_decode_SRC2_3;
wire _zz_decode_SRC2_4;
wire [19:0] _zz_decode_SRC2_5;
wire [31:0] _zz_decode_SRC2_6;
wire [1:0] _zz_decode_SRC2_CTRL;
wire [1:0] _zz_decode_SRC2_CTRL_1;
wire [1:0] _zz_decode_SRC2_CTRL_2;
wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire [1:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire [1:0] _zz_decode_to_execute_ALU_CTRL;
wire [1:0] _zz_decode_to_execute_ALU_CTRL_1;
wire [1:0] _zz_decode_to_execute_BRANCH_CTRL;
wire [1:0] _zz_decode_to_execute_BRANCH_CTRL_1;
wire _zz_decode_to_execute_ENV_CTRL;
wire _zz_decode_to_execute_ENV_CTRL_1;
wire [1:0] _zz_decode_to_execute_SHIFT_CTRL;
wire [1:0] _zz_decode_to_execute_SHIFT_CTRL_1;
wire [1:0] _zz_execute_ALU_BITWISE_CTRL;
wire [1:0] _zz_execute_ALU_CTRL;
wire [1:0] _zz_execute_BRANCH_CTRL;
wire _zz_execute_BRANCH_DO;
wire _zz_execute_BRANCH_DO_1;
wire _zz_execute_BranchPlugin_branch_src2;
wire [10:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
wire [19:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
wire [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_ENV_CTRL;
wire [31:0] _zz_execute_REGFILE_WRITE_DATA;
wire [1:0] _zz_execute_SHIFT_CTRL;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire _zz_execute_to_memory_ENV_CTRL;
wire _zz_execute_to_memory_ENV_CTRL_1;
wire [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA;
wire [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA_1;
wire [29:0] _zz_lastStageRegFileWrite_payload_address;
wire [31:0] _zz_lastStageRegFileWrite_payload_data;
wire _zz_lastStageRegFileWrite_valid;
wire _zz_memory_ENV_CTRL;
wire _zz_memory_to_writeBack_ENV_CTRL;
wire _zz_memory_to_writeBack_ENV_CTRL_1;
wire _zz_when_CsrPlugin_l952;
wire _zz_when_CsrPlugin_l952_1;
wire _zz_when_CsrPlugin_l952_2;
wire _zz_when_DebugPlugin_l244;
wire _zz_writeBack_DBusSimplePlugin_rspFormated;
wire [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_1;
wire _zz_writeBack_DBusSimplePlugin_rspFormated_2;
wire [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_3;
wire _zz_writeBack_ENV_CTRL;
wire contextSwitching;
output [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_address;
output [31:0] dBus_cmd_payload_data;
wire [31:0] dBus_cmd_payload_data;
output [1:0] dBus_cmd_payload_size;
wire [1:0] dBus_cmd_payload_size;
output dBus_cmd_payload_wr;
wire dBus_cmd_payload_wr;
input dBus_cmd_ready;
wire dBus_cmd_ready;
output dBus_cmd_valid;
wire dBus_cmd_valid;
input [31:0] dBus_rsp_data;
wire [31:0] dBus_rsp_data;
input dBus_rsp_error;
wire dBus_rsp_error;
input dBus_rsp_ready;
wire dBus_rsp_ready;
input [7:0] debug_bus_cmd_payload_address;
wire [7:0] debug_bus_cmd_payload_address;
input [31:0] debug_bus_cmd_payload_data;
wire [31:0] debug_bus_cmd_payload_data;
input debug_bus_cmd_payload_wr;
wire debug_bus_cmd_payload_wr;
output debug_bus_cmd_ready;
wire debug_bus_cmd_ready;
input debug_bus_cmd_valid;
wire debug_bus_cmd_valid;
output [31:0] debug_bus_rsp_data;
wire [31:0] debug_bus_rsp_data;
output debug_resetOut;
wire debug_resetOut;
wire [1:0] decode_ALU_BITWISE_CTRL;
wire [1:0] decode_ALU_CTRL;
wire [1:0] decode_BRANCH_CTRL;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_CSR_WRITE_OPCODE;
wire decode_DO_EBREAK;
wire decode_ENV_CTRL;
wire [31:0] decode_INSTRUCTION;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
wire decode_IS_CSR;
wire decode_IS_EBREAK;
wire decode_MEMORY_ENABLE;
wire decode_MEMORY_STORE;
wire [31:0] decode_PC;
wire [31:0] decode_RS1;
wire decode_RS1_USE;
wire [31:0] decode_RS2;
wire decode_RS2_USE;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
wire [1:0] decode_SHIFT_CTRL;
wire [31:0] decode_SRC1;
wire [1:0] decode_SRC1_CTRL;
wire [31:0] decode_SRC2;
wire [1:0] decode_SRC2_CTRL;
wire decode_SRC2_FORCE_ZERO;
wire decode_SRC_ADD_ZERO;
wire decode_SRC_LESS_UNSIGNED;
wire decode_SRC_USE_SUB_LESS;
wire decode_arbitration_flushIt;
wire decode_arbitration_flushNext;
wire decode_arbitration_haltByOther;
wire decode_arbitration_haltItself;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isValid;
wire decode_arbitration_removeIt;
wire [1:0] decode_to_execute_ALU_BITWISE_CTRL;
wire [1:0] decode_to_execute_ALU_CTRL;
wire [1:0] decode_to_execute_BRANCH_CTRL;
wire decode_to_execute_CSR_WRITE_OPCODE;
wire decode_to_execute_DO_EBREAK;
wire decode_to_execute_ENV_CTRL;
wire [31:0] decode_to_execute_INSTRUCTION;
wire decode_to_execute_IS_CSR;
wire decode_to_execute_MEMORY_ENABLE;
wire decode_to_execute_MEMORY_STORE;
wire [31:0] decode_to_execute_PC;
wire decode_to_execute_REGFILE_WRITE_VALID;
wire [31:0] decode_to_execute_RS1;
wire [31:0] decode_to_execute_RS2;
wire [1:0] decode_to_execute_SHIFT_CTRL;
wire [31:0] decode_to_execute_SRC1;
wire [31:0] decode_to_execute_SRC2;
wire decode_to_execute_SRC2_FORCE_ZERO;
wire decode_to_execute_SRC_LESS_UNSIGNED;
wire decode_to_execute_SRC_USE_SUB_LESS;
wire execute_ALIGNEMENT_FAULT;
wire [1:0] execute_ALU_BITWISE_CTRL;
wire [1:0] execute_ALU_CTRL;
wire [31:0] execute_BRANCH_CALC;
wire [1:0] execute_BRANCH_CTRL;
wire execute_BRANCH_DO;
wire [31:0] execute_BranchPlugin_branchAdder;
wire [31:0] execute_BranchPlugin_branch_src1;
wire [31:0] execute_BranchPlugin_branch_src2;
wire execute_BranchPlugin_eq;
wire execute_CSR_WRITE_OPCODE;
wire execute_CsrPlugin_blockedBySideEffects;
wire [11:0] execute_CsrPlugin_csrAddress;
wire execute_CsrPlugin_csr_768;
wire execute_CsrPlugin_csr_772;
wire execute_CsrPlugin_csr_834;
wire execute_CsrPlugin_csr_836;
wire [31:0] execute_CsrPlugin_readToWriteData;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_writeInstruction;
wire execute_DBusSimplePlugin_skipCmd;
wire execute_DO_EBREAK;
wire execute_ENV_CTRL;
wire [31:0] execute_INSTRUCTION;
wire execute_IS_CSR;
wire [31:0] execute_IntAluPlugin_bitwise;
wire [4:0] execute_LightShifterPlugin_amplitude;
wire [4:0] execute_LightShifterPlugin_amplitudeReg;
wire execute_LightShifterPlugin_done;
wire execute_LightShifterPlugin_isActive;
wire execute_LightShifterPlugin_isShift;
wire [31:0] execute_LightShifterPlugin_shiftInput;
wire [1:0] execute_MEMORY_ADDRESS_LOW;
wire execute_MEMORY_ENABLE;
wire execute_MEMORY_STORE;
wire [31:0] execute_PC;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire execute_REGFILE_WRITE_VALID;
wire [31:0] execute_RS1;
wire [31:0] execute_RS2;
wire [1:0] execute_SHIFT_CTRL;
wire [31:0] execute_SRC1;
wire [31:0] execute_SRC2;
wire execute_SRC2_FORCE_ZERO;
wire [31:0] execute_SRC_ADD;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire execute_arbitration_flushIt;
wire execute_arbitration_flushNext;
wire execute_arbitration_haltByOther;
wire execute_arbitration_haltItself;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isValid;
wire execute_arbitration_removeIt;
wire [31:0] execute_to_memory_BRANCH_CALC;
wire execute_to_memory_BRANCH_DO;
wire execute_to_memory_ENV_CTRL;
wire [29:0] execute_to_memory_INSTRUCTION;
wire [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
wire execute_to_memory_MEMORY_ENABLE;
wire execute_to_memory_MEMORY_STORE;
wire [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire execute_to_memory_REGFILE_WRITE_VALID;
input externalInterrupt;
wire externalInterrupt;
output [31:0] iBus_cmd_payload_pc;
wire [31:0] iBus_cmd_payload_pc;
input iBus_cmd_ready;
wire iBus_cmd_ready;
output iBus_cmd_valid;
wire iBus_cmd_valid;
input iBus_rsp_payload_error;
wire iBus_rsp_payload_error;
input [31:0] iBus_rsp_payload_inst;
wire [31:0] iBus_rsp_payload_inst;
wire iBus_rsp_toStream_payload_error;
wire [31:0] iBus_rsp_toStream_payload_inst;
wire iBus_rsp_toStream_ready;
wire iBus_rsp_toStream_valid;
input iBus_rsp_valid;
wire iBus_rsp_valid;
input io_mainClk;
wire io_mainClk;
wire [31:0] lastStageInstruction;
wire lastStageIsFiring;
wire lastStageIsValid;
wire [4:0] lastStageRegFileWrite_payload_address;
wire [31:0] lastStageRegFileWrite_payload_data;
wire lastStageRegFileWrite_valid;
wire [31:0] memory_BRANCH_CALC;
wire memory_BRANCH_DO;
wire memory_ENV_CTRL;
wire [31:0] memory_INSTRUCTION;
wire [1:0] memory_MEMORY_ADDRESS_LOW;
wire memory_MEMORY_ENABLE;
wire [31:0] memory_MEMORY_READ_DATA;
wire memory_MEMORY_STORE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_REGFILE_WRITE_VALID;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
wire memory_arbitration_haltByOther;
wire memory_arbitration_haltItself;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isValid;
wire memory_arbitration_removeIt;
wire memory_to_writeBack_ENV_CTRL;
wire [31:0] memory_to_writeBack_INSTRUCTION;
wire [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW;
wire memory_to_writeBack_MEMORY_ENABLE;
wire [31:0] memory_to_writeBack_MEMORY_READ_DATA;
wire [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire memory_to_writeBack_REGFILE_WRITE_VALID;
input resetCtrl_mainClkReset;
wire resetCtrl_mainClkReset;
input resetCtrl_systemReset;
wire resetCtrl_systemReset;
input softwareInterrupt;
wire softwareInterrupt;
wire [1:0] switch_CsrPlugin_l1068;
wire [5:0] switch_DebugPlugin_l267;
wire [2:0] switch_Fetcher_l362;
wire [1:0] switch_Misc_l211;
wire switch_Misc_l211_1;
wire [2:0] switch_Misc_l211_2;
input timerInterrupt;
wire timerInterrupt;
wire when_CsrPlugin_l1019;
wire when_CsrPlugin_l1064;
wire when_CsrPlugin_l1116;
wire when_CsrPlugin_l1176;
wire when_CsrPlugin_l1180;
wire when_CsrPlugin_l946;
wire when_CsrPlugin_l952;
wire when_CsrPlugin_l952_1;
wire when_CsrPlugin_l952_2;
wire when_CsrPlugin_l980_2;
wire when_CsrPlugin_l985;
wire when_DBusSimplePlugin_l428;
wire when_DBusSimplePlugin_l482;
wire when_DBusSimplePlugin_l558;
wire when_DebugPlugin_l271;
wire when_DebugPlugin_l271_1;
wire when_DebugPlugin_l272;
wire when_DebugPlugin_l272_1;
wire when_DebugPlugin_l273;
wire when_DebugPlugin_l274;
wire when_DebugPlugin_l275;
wire when_DebugPlugin_l275_1;
wire when_DebugPlugin_l295;
wire when_DebugPlugin_l311;
wire when_DebugPlugin_l327;
wire when_Fetcher_l131;
wire when_Fetcher_l131_1;
wire when_Fetcher_l158;
wire when_Fetcher_l240;
wire when_Fetcher_l329;
wire when_Fetcher_l329_1;
wire when_Fetcher_l329_5;
wire when_Fetcher_l398;
wire when_HazardSimplePlugin_l113;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l59;
wire when_HazardSimplePlugin_l59_1;
wire when_HazardSimplePlugin_l59_2;
wire when_HazardSimplePlugin_l62;
wire when_HazardSimplePlugin_l62_1;
wire when_HazardSimplePlugin_l62_2;
wire when_IBusSimplePlugin_l305;
wire when_Pipeline_l124_14;
wire when_Pipeline_l124_17;
wire when_Pipeline_l124_2;
wire when_Pipeline_l124_26;
wire when_Pipeline_l124_39;
wire when_Pipeline_l124_40;
wire when_Pipeline_l124_41;
wire when_Pipeline_l124_44;
wire when_Pipeline_l124_5;
wire when_Pipeline_l124_8;
wire when_Pipeline_l151;
wire when_Pipeline_l151_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154;
wire when_Pipeline_l154_1;
wire when_Pipeline_l154_2;
wire when_RegFilePlugin_l63;
wire when_ShiftPlugins_l169;
wire [31:0] writeBack_DBusSimplePlugin_rspFormated;
wire [31:0] writeBack_DBusSimplePlugin_rspShifted;
wire writeBack_ENV_CTRL;
wire [31:0] writeBack_INSTRUCTION;
wire [1:0] writeBack_MEMORY_ADDRESS_LOW;
wire writeBack_MEMORY_ENABLE;
wire [31:0] writeBack_MEMORY_READ_DATA;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire writeBack_REGFILE_WRITE_VALID;
wire writeBack_arbitration_flushIt;
wire writeBack_arbitration_flushNext;
wire writeBack_arbitration_haltByOther;
wire writeBack_arbitration_haltItself;
wire writeBack_arbitration_isFiring;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isValid;
wire writeBack_arbitration_removeIt;
reg [31:0] RegFilePlugin_regFile [31:0];
always @(posedge io_mainClk) begin
if (_000_[31])
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
reg [31:0] _774_;
reg [31:0] _775_;
always @(posedge io_mainClk) begin
_774_ <= RegFilePlugin_regFile[decode_INSTRUCTION_ANTICIPATED[24:20]];
_775_ <= RegFilePlugin_regFile[decode_INSTRUCTION_ANTICIPATED[19:15]];
end
assign _zz_RegFilePlugin_regFile_port1 = _774_;
assign _zz_RegFilePlugin_regFile_port0 = _775_;
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _248_ (
.A(CsrPlugin_jumpInterface_valid),
.B(_108_[0]),
.Y(_zz_IBusSimplePlugin_jump_pcLoad_payload_1)
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd32),
.B_SIGNED(32'd0),
.B_WIDTH(32'd32),
.Y_WIDTH(32'd32)
) _249_ (
.A(decode_to_execute_SRC1),
.B(decode_to_execute_SRC2),
.Y(_061_)
);
\$macc #(
.A_WIDTH(32'd66),
.B_WIDTH(32'd0),
.CONFIG(46'h008100240816),
.CONFIG_WIDTH(32'd46),
.Y_WIDTH(32'd32)
) _250_ (
.A({ _zz_execute_SrcPlugin_addSub_3, 1'h0, _zz_execute_SrcPlugin_addSub_4, decode_to_execute_SRC1 }),
.B(),
.Y(_zz_execute_SrcPlugin_addSub)
);
\$macc #(
.A_WIDTH(32'd4),
.B_WIDTH(32'd1),
.CONFIG(16'h18c2),
.CONFIG_WIDTH(32'd16),
.Y_WIDTH(32'd3)
) _251_ (
.A({ IBusSimplePlugin_pending_dec, IBusSimplePlugin_pending_value }),
.B(IBusSimplePlugin_cmd_fire),
.Y(IBusSimplePlugin_pending_next)
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd3)
) _252_ (
.A(IBusSimplePlugin_rspJoin_rspBuffer_discardCounter),
.B(_zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1),
.BI(1'h1),
.CI(1'h1),
.CO(_067_),
.X(_062_),
.Y(_243_)
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd5)
) _253_ (
.A(execute_LightShifterPlugin_amplitude),
.B(1'h1),
.BI(1'h1),
.CI(1'h1),
.CO(_068_),
.X(_063_),
.Y(_244_)
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd30),
.Y_WIDTH(32'd30)
) _254_ (
.A(IBusSimplePlugin_fetchPc_inc),
.B(IBusSimplePlugin_fetchPc_pcReg[31:2]),
.BI(1'h0),
.CI(1'h0),
.CO(_069_[31:2]),
.X(_064_[31:2]),
.Y(_059_[31:2])
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd32),
.B_SIGNED(32'd0),
.B_WIDTH(32'd32),
.Y_WIDTH(32'd32)
) _255_ (
.A(execute_BranchPlugin_branch_src1),
.B({ decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], execute_BranchPlugin_branch_src2[19:11], decode_to_execute_INSTRUCTION[30:25], execute_BranchPlugin_branch_src2[4:0] }),
.BI(1'h0),
.CI(1'h0),
.CO(_070_),
.X(_065_),
.Y(execute_BranchPlugin_branchAdder)
);
\$alu #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _256_ (
.A(CsrPlugin_jumpInterface_valid),
.B(1'h1),
.BI(1'h1),
.CI(1'h1),
.CO(_071_),
.X(_066_),
.Y(_zz_IBusSimplePlugin_jump_pcLoad_payload_2[0])
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(3'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd3)
) _257_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_022_),
.EN(_091_),
.Q(switch_Fetcher_l362)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) execute_LightShifterPlugin_isActive_reg /* _258_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_019_),
.EN(_092_),
.Q(execute_LightShifterPlugin_isActive)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) CsrPlugin_pipelineLiberator_pcValids_2_reg /* _259_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_008_),
.EN(_077_),
.Q(CsrPlugin_pipelineLiberator_pcValids_2)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) CsrPlugin_pipelineLiberator_pcValids_1_reg /* _260_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_007_),
.EN(_093_),
.Q(CsrPlugin_pipelineLiberator_pcValids_1)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) CsrPlugin_pipelineLiberator_pcValids_0_reg /* _261_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_006_),
.EN(_094_),
.Q(CsrPlugin_pipelineLiberator_pcValids_0)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) CsrPlugin_mie_MSIE_reg /* _262_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(CsrPlugin_csrMapping_writeDataSignal[3]),
.EN(_095_),
.Q(CsrPlugin_mie_MSIE)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) CsrPlugin_mie_MTIE_reg /* _263_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(CsrPlugin_csrMapping_writeDataSignal[7]),
.EN(_095_),
.Q(CsrPlugin_mie_MTIE)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) CsrPlugin_mie_MEIE_reg /* _264_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(CsrPlugin_csrMapping_writeDataSignal[11]),
.EN(_095_),
.Q(CsrPlugin_mie_MEIE)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) _zz_IBusSimplePlugin_injector_decodeInput_valid_reg /* _265_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_018_),
.EN(_080_),
.Q(_zz_IBusSimplePlugin_injector_decodeInput_valid)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid_reg /* _266_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_016_),
.EN(_081_),
.Q(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2_reg /* _267_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_015_),
.EN(_082_),
.Q(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) IBusSimplePlugin_fetchPc_inc_reg /* _268_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_013_),
.EN(_083_),
.Q(IBusSimplePlugin_fetchPc_inc)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) memory_arbitration_isValid_reg /* _269_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_021_),
.EN(_084_),
.Q(memory_arbitration_isValid)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) execute_arbitration_isValid_reg /* _270_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_020_),
.EN(_085_),
.Q(execute_arbitration_isValid)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) execute_CsrPlugin_csr_834_reg /* _271_ */ (
.CLK(io_mainClk),
.D(_127_),
.EN(execute_arbitration_isStuck),
.Q(execute_CsrPlugin_csr_834)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) execute_CsrPlugin_csr_772_reg /* _272_ */ (
.CLK(io_mainClk),
.D(_126_),
.EN(execute_arbitration_isStuck),
.Q(execute_CsrPlugin_csr_772)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) execute_CsrPlugin_csr_836_reg /* _273_ */ (
.CLK(io_mainClk),
.D(_125_),
.EN(execute_arbitration_isStuck),
.Q(execute_CsrPlugin_csr_836)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) execute_CsrPlugin_csr_768_reg /* _274_ */ (
.CLK(io_mainClk),
.D(_124_),
.EN(execute_arbitration_isStuck),
.Q(execute_CsrPlugin_csr_768)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) execute_to_memory_BRANCH_DO_reg /* _275_ */ (
.CLK(io_mainClk),
.D(_zz_execute_BRANCH_DO_1),
.EN(memory_arbitration_isStuck),
.Q(execute_to_memory_BRANCH_DO)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd32)
) _276_ (
.CLK(io_mainClk),
.D(_zz_execute_to_memory_REGFILE_WRITE_DATA),
.EN(when_Pipeline_l124_40),
.Q(execute_to_memory_REGFILE_WRITE_DATA)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd2)
) _277_ (
.CLK(io_mainClk),
.D(execute_SrcPlugin_addSub[1:0]),
.EN(memory_arbitration_isStuck),
.Q(execute_to_memory_MEMORY_ADDRESS_LOW)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) decode_to_execute_DO_EBREAK_reg /* _278_ */ (
.CLK(io_mainClk),
.D(decode_DO_EBREAK),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_DO_EBREAK)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd32)
) _279_ (
.CLK(io_mainClk),
.D(_zz_decode_SRC2_6),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_SRC2)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd32)
) _280_ (
.CLK(io_mainClk),
.D(_zz_decode_SRC1_1),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_SRC1)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) decode_to_execute_SRC2_FORCE_ZERO_reg /* _281_ */ (
.CLK(io_mainClk),
.D(decode_SRC2_FORCE_ZERO),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_SRC2_FORCE_ZERO)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd32)
) _282_ (
.CLK(io_mainClk),
.D(_zz_RegFilePlugin_regFile_port1),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_RS2)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd32)
) _283_ (
.CLK(io_mainClk),
.D(_zz_RegFilePlugin_regFile_port0),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_RS1)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd2)
) _284_ (
.CLK(io_mainClk),
.D(_zz_decode_BRANCH_CTRL),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_BRANCH_CTRL)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd2)
) _285_ (
.CLK(io_mainClk),
.D({ _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] }),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_SHIFT_CTRL)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd2)
) _286_ (
.CLK(io_mainClk),
.D({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 }),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_ALU_BITWISE_CTRL)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) decode_to_execute_SRC_LESS_UNSIGNED_reg /* _287_ */ (
.CLK(io_mainClk),
.D(decode_SRC_LESS_UNSIGNED),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_SRC_LESS_UNSIGNED)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd2)
) _288_ (
.CLK(io_mainClk),
.D({ _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 }),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_ALU_CTRL)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) execute_to_memory_ENV_CTRL_reg /* _289_ */ (
.CLK(io_mainClk),
.D(decode_to_execute_ENV_CTRL),
.EN(memory_arbitration_isStuck),
.Q(execute_to_memory_ENV_CTRL)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) decode_to_execute_ENV_CTRL_reg /* _290_ */ (
.CLK(io_mainClk),
.D(_zz__zz_decode_BRANCH_CTRL_2_28),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_ENV_CTRL)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) decode_to_execute_IS_CSR_reg /* _291_ */ (
.CLK(io_mainClk),
.D(decode_IS_CSR),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_IS_CSR)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) execute_to_memory_MEMORY_STORE_reg /* _292_ */ (
.CLK(io_mainClk),
.D(decode_to_execute_MEMORY_STORE),
.EN(memory_arbitration_isStuck),
.Q(execute_to_memory_MEMORY_STORE)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) decode_to_execute_MEMORY_STORE_reg /* _293_ */ (
.CLK(io_mainClk),
.D(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5]),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_MEMORY_STORE)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) execute_to_memory_REGFILE_WRITE_VALID_reg /* _294_ */ (
.CLK(io_mainClk),
.D(decode_to_execute_REGFILE_WRITE_VALID),
.EN(memory_arbitration_isStuck),
.Q(execute_to_memory_REGFILE_WRITE_VALID)
);
\$sdffce #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.SRST_POLARITY(32'd1),
.SRST_VALUE(1'h0),
.WIDTH(32'd1)
) decode_to_execute_REGFILE_WRITE_VALID_reg /* _295_ */ (
.CLK(io_mainClk),
.D(_zz__zz_decode_BRANCH_CTRL_2_47),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_REGFILE_WRITE_VALID),
.SRST(when_RegFilePlugin_l63)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) execute_to_memory_MEMORY_ENABLE_reg /* _296_ */ (
.CLK(io_mainClk),
.D(decode_to_execute_MEMORY_ENABLE),
.EN(memory_arbitration_isStuck),
.Q(execute_to_memory_MEMORY_ENABLE)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) decode_to_execute_MEMORY_ENABLE_reg /* _297_ */ (
.CLK(io_mainClk),
.D(_zz__zz_decode_BRANCH_CTRL_2_71),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_MEMORY_ENABLE)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) decode_to_execute_SRC_USE_SUB_LESS_reg /* _298_ */ (
.CLK(io_mainClk),
.D(decode_SRC_USE_SUB_LESS),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_SRC_USE_SUB_LESS)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd1)
) decode_to_execute_CSR_WRITE_OPCODE_reg /* _299_ */ (
.CLK(io_mainClk),
.D(decode_CSR_WRITE_OPCODE),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_CSR_WRITE_OPCODE)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd30)
) _300_ (
.CLK(io_mainClk),
.D(decode_to_execute_INSTRUCTION[29:0]),
.EN(memory_arbitration_isStuck),
.Q(execute_to_memory_INSTRUCTION)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd32)
) _301_ (
.CLK(io_mainClk),
.D(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_INSTRUCTION)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd5)
) _302_ (
.CLK(io_mainClk),
.D(_244_),
.EN(_096_),
.Q(execute_LightShifterPlugin_amplitudeReg)
);
\$sdffce #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.SRST_POLARITY(32'd1),
.SRST_VALUE(1'h0),
.WIDTH(32'd1)
) \CsrPlugin_interrupt_code_reg[2] /* _303_ */ (
.CLK(io_mainClk),
.D(1'h1),
.EN(_097_),
.Q(CsrPlugin_interrupt_code[2]),
.SRST(_101_)
);
\$sdffce #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.SRST_POLARITY(32'd1),
.SRST_VALUE(1'h1),
.WIDTH(32'd1)
) \CsrPlugin_interrupt_code_reg[3] /* _304_ */ (
.CLK(io_mainClk),
.D(1'h0),
.EN(_097_),
.Q(CsrPlugin_interrupt_code[3]),
.SRST(_zz_when_CsrPlugin_l952_2)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd22)
) _305_ (
.CLK(io_mainClk),
.D({ _017_[31:25], _017_[14:0] }),
.EN(_087_),
.Q({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:25], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:0] })
);
\$dff #(
.CLK_POLARITY(32'd1),
.WIDTH(32'd10)
) _306_ (
.CLK(io_mainClk),
.D(_017_[24:15]),
.Q(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:15])
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) DebugPlugin_disableEbreak_reg /* _307_ */ (
.ARST(resetCtrl_mainClkReset),
.CLK(io_mainClk),
.D(_178_),
.EN(_098_),
.Q(DebugPlugin_disableEbreak)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) DebugPlugin_debugUsed_reg /* _308_ */ (
.ARST(resetCtrl_mainClkReset),
.CLK(io_mainClk),
.D(1'h1),
.EN(debug_bus_cmd_valid),
.Q(DebugPlugin_debugUsed)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) DebugPlugin_stepIt_reg /* _309_ */ (
.ARST(resetCtrl_mainClkReset),
.CLK(io_mainClk),
.D(debug_bus_cmd_payload_data[4]),
.EN(_099_),
.Q(DebugPlugin_stepIt)
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd1)
) DebugPlugin_resetIt_reg /* _310_ */ (
.ARST(resetCtrl_mainClkReset),
.CLK(io_mainClk),
.D(_193_),
.EN(_100_),
.Q(DebugPlugin_resetIt)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd31)
) _311_ (
.CLK(io_mainClk),
.D(execute_BranchPlugin_branchAdder[31:1]),
.EN(memory_arbitration_isStuck),
.Q(execute_to_memory_BRANCH_CALC[31:1])
);
\$adffe #(
.ARST_POLARITY(32'd1),
.ARST_VALUE(30'h20000000),
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd30)
) _312_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(IBusSimplePlugin_fetchPc_pc[31:2]),
.EN(when_Fetcher_l158),
.Q(IBusSimplePlugin_fetchPc_pcReg[31:2])
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd2)
) _313_ (
.CLK(io_mainClk),
.D(CsrPlugin_interrupt_code[3:2]),
.EN(CsrPlugin_interruptJump),
.Q(CsrPlugin_mcause_exceptionCode[3:2])
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd30)
) _314_ (
.CLK(io_mainClk),
.D(IBusSimplePlugin_fetchPc_pcReg[31:2]),
.EN(IBusSimplePlugin_iBusRsp_stages_1_output_ready),
.Q(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2])
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd30)
) _315_ (
.CLK(io_mainClk),
.D(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2]),
.EN(decode_arbitration_isStuck),
.Q(_zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2])
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd0),
.WIDTH(32'd30)
) _316_ (
.CLK(io_mainClk),
.D(_zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2]),
.EN(execute_arbitration_isStuck),
.Q(decode_to_execute_PC[31:2])
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd30)
) _317_ (
.CLK(io_mainClk),
.D(_zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2]),
.EN(CsrPlugin_interruptJump),
.Q(CsrPlugin_mepc[31:2])
);
\$sdffce #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.SRST_POLARITY(32'd1),
.SRST_VALUE(2'h0),
.WIDTH(32'd2)
) _318_ (
.CLK(io_mainClk),
.D(_zz_lastStageRegFileWrite_payload_data[1:0]),
.EN(_088_),
.Q(DebugPlugin_busReadDataReg[1:0]),
.SRST(when_DebugPlugin_l295)
);
\$dffe #(
.CLK_POLARITY(32'd1),
.EN_POLARITY(32'd1),
.WIDTH(32'd30)
) _319_ (
.CLK(io_mainClk),
.D(_009_[31:2]),
.EN(_088_),
.Q(DebugPlugin_busReadDataReg[31:2])
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _320_ (
.A({ _200_, decode_arbitration_isStuck }),
.B(2'h3),
.Y(_072_)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _321_ (
.A({ _203_, IBusSimplePlugin_injectionPort_valid }),
.B(2'h2),
.Y(_073_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _322_ (
.A({ _203_, _202_, _201_, _200_, _199_ }),
.Y(_074_)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _323_ (
.A({ when_ShiftPlugins_l169, execute_arbitration_isStuckByOthers, execute_arbitration_removeIt }),
.B(3'h6),
.Y(_075_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _324_ (
.A({ when_ShiftPlugins_l169, execute_arbitration_removeIt }),
.Y(_076_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _325_ (
.A({ when_CsrPlugin_l985, CsrPlugin_pipelineLiberator_active }),
.Y(_077_)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _326_ (
.A({ when_CsrPlugin_l985, CsrPlugin_pipelineLiberator_active, memory_arbitration_isStuck }),
.B(2'h3),
.Y(_078_)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _327_ (
.A({ when_CsrPlugin_l985, CsrPlugin_pipelineLiberator_active, execute_arbitration_isStuck }),
.B(2'h3),
.Y(_079_)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _328_ (
.A({ decode_arbitration_isStuck, decode_arbitration_removeIt }),
.B(2'h2),
.Y(_080_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _329_ (
.A({ IBusSimplePlugin_iBusRsp_stages_1_output_ready, IBusSimplePlugin_externalFlush }),
.Y(_081_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _330_ (
.A({ IBusSimplePlugin_fetchPc_output_ready, IBusSimplePlugin_externalFlush }),
.Y(_082_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _331_ (
.A({ when_Fetcher_l131_1, IBusSimplePlugin_fetchPc_output_fire_1, when_Fetcher_l131 }),
.Y(_083_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _332_ (
.A({ when_Pipeline_l154_1, when_Pipeline_l151_1 }),
.Y(_084_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _333_ (
.A({ when_Pipeline_l154, when_Pipeline_l151 }),
.Y(_085_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _334_ (
.A({ _zz_when_CsrPlugin_l952_2, _zz_when_CsrPlugin_l952_1, _zz_when_CsrPlugin_l952 }),
.Y(_086_)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _335_ (
.A({ when_Fetcher_l398, decode_arbitration_isStuck }),
.B(1'h1),
.Y(_087_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _336_ (
.A({ when_DebugPlugin_l295, writeBack_arbitration_isValid }),
.Y(_088_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _337_ (
.A({ debug_bus_cmd_payload_data[26], debug_bus_cmd_payload_data[18] }),
.Y(_089_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _338_ (
.A({ debug_bus_cmd_payload_data[24], debug_bus_cmd_payload_data[16] }),
.Y(_090_)
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _339_ (
.A(execute_arbitration_isStuckByOthers),
.Y(_107_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _340_ (
.A({ _073_, _072_, _074_ }),
.Y(_091_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _341_ (
.A({ _076_, _075_ }),
.Y(_092_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _342_ (
.A({ _078_, _077_ }),
.Y(_093_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _343_ (
.A({ _079_, _077_ }),
.Y(_094_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _344_ (
.A({ execute_CsrPlugin_csr_772, execute_CsrPlugin_writeEnable }),
.Y(_095_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _345_ (
.A({ when_ShiftPlugins_l169, _107_ }),
.Y(_096_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _346_ (
.A({ _086_, CsrPlugin_mstatus_MIE }),
.Y(_097_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.Y_WIDTH(32'd1)
) _347_ (
.A({ _089_, _179_, debug_bus_cmd_payload_wr, debug_bus_cmd_valid }),
.Y(_098_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _348_ (
.A({ _179_, debug_bus_cmd_payload_wr, debug_bus_cmd_valid }),
.Y(_099_)
);
\$reduce_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.Y_WIDTH(32'd1)
) _349_ (
.A({ _090_, _179_, debug_bus_cmd_payload_wr, debug_bus_cmd_valid }),
.Y(_100_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _350_ (
.A({ _zz_when_CsrPlugin_l952_2, _zz_when_CsrPlugin_l952_1 }),
.Y(_101_)
);
\$or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd3)
) _351_ (
.A({ _zz_CsrPlugin_csrMapping_readDataInit[11], _zz_CsrPlugin_csrMapping_readDataInit[7], _zz_CsrPlugin_csrMapping_readDataInit[3] }),
.B({ _zz_CsrPlugin_csrMapping_readDataInit_1[11], _zz_CsrPlugin_csrMapping_readDataInit_1[7], _zz_CsrPlugin_csrMapping_readDataInit_1[3] }),
.Y(_102_)
);
\$or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _352_ (
.A(_zz_CsrPlugin_csrMapping_readDataInit_2[3]),
.B(_zz_CsrPlugin_csrMapping_readDataInit_3[3]),
.Y(_103_)
);
\$or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd3)
) _353_ (
.A(_102_),
.B({ _zz_CsrPlugin_csrMapping_readDataInit_2[11], _zz_CsrPlugin_csrMapping_readDataInit_2[7], _103_ }),
.Y({ execute_CsrPlugin_readToWriteData[11], execute_CsrPlugin_readToWriteData[7], execute_CsrPlugin_readToWriteData[3] })
);
\$and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd7),
.B_SIGNED(32'd0),
.B_WIDTH(32'd7),
.Y_WIDTH(32'd7)
) _354_ (
.A({ execute_CsrPlugin_readToWriteData[11], execute_CsrPlugin_readToWriteData[7], execute_CsrPlugin_readToWriteData[3], _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1], _zz_CsrPlugin_csrMapping_readDataInit[12] }),
.B({ _109_[11], _109_[7], _109_[3:0], _109_[12] }),
.Y({ _060_[11], _060_[7], _060_[3:0], _060_[12] })
);
\$or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd7),
.B_SIGNED(32'd0),
.B_WIDTH(32'd7),
.Y_WIDTH(32'd7)
) _355_ (
.A({ execute_CsrPlugin_readToWriteData[11], execute_CsrPlugin_readToWriteData[7], execute_CsrPlugin_readToWriteData[3], _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1], _zz_CsrPlugin_csrMapping_readDataInit[12] }),
.B({ decode_to_execute_SRC1[11], decode_to_execute_SRC1[7], decode_to_execute_SRC1[3:0], decode_to_execute_SRC1[12] }),
.Y(_104_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _356_ (
.A({ _220_, _123_ }),
.Y(_105_)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _357_ (
.A({ _201_, _200_ }),
.Y(_106_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _358_ (
.A(decode_to_execute_SHIFT_CTRL),
.B(2'h3),
.Y(_110_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd6),
.B_SIGNED(32'd0),
.B_WIDTH(32'd6),
.Y_WIDTH(32'd1)
) _359_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(6'h2a),
.Y(_zz__zz_decode_BRANCH_CTRL_2_4)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd6),
.B_SIGNED(32'd0),
.B_WIDTH(32'd6),
.Y_WIDTH(32'd1)
) _360_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(6'h0a),
.Y(_zz__zz_decode_BRANCH_CTRL_2_5[0])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd6),
.B_SIGNED(32'd0),
.B_WIDTH(32'd6),
.Y_WIDTH(32'd1)
) _361_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(6'h2a),
.Y(_zz__zz_decode_BRANCH_CTRL_2_5[1])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _362_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(5'h0a),
.Y(_111_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _363_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:5], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(3'h3),
.Y(_112_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _364_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12]),
.B(2'h2),
.Y(_zz__zz_decode_BRANCH_CTRL_2_17)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _365_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12] }),
.B(2'h1),
.Y(_zz__zz_decode_BRANCH_CTRL_2_18[0])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _366_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }),
.B(2'h2),
.Y(_zz__zz_decode_BRANCH_CTRL_2_18[1])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _367_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(3'h4),
.Y(_113_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _368_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(3'h6),
.Y(_114_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _369_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }),
.B(5'h03),
.Y(_zz__zz_decode_BRANCH_CTRL_2_28)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _370_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }),
.B(3'h7),
.Y(_zz__zz_decode_BRANCH_CTRL_2_29[0])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _371_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }),
.B(3'h7),
.Y(_zz__zz_decode_BRANCH_CTRL_2_29[1])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _372_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:5], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(3'h2),
.Y(_115_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _373_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5:4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(3'h4),
.Y(_116_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _374_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }),
.B(2'h3),
.Y(_zz__zz_decode_BRANCH_CTRL_2_49[4])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _375_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:4]),
.B(3'h2),
.Y(_zz__zz_decode_BRANCH_CTRL_2_60[0])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _376_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }),
.B(2'h3),
.Y(_zz__zz_decode_BRANCH_CTRL_2_52)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _377_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] }),
.Y(_zz__zz_decode_BRANCH_CTRL_2_49[0])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _378_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3:2]),
.B(2'h1),
.Y(_zz__zz_decode_BRANCH_CTRL_2_49[1])
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _379_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5]),
.Y(_zz__zz_decode_BRANCH_CTRL_2_64)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _380_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.Y(_zz__zz_decode_BRANCH_CTRL_2_66)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _381_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:3] }),
.Y(_zz__zz_decode_BRANCH_CTRL_2_71)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _382_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(3'h2),
.Y(_zz__zz_decode_BRANCH_CTRL_2_69)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _383_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(2'h2),
.Y(_zz__zz_decode_BRANCH_CTRL_2_74)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _384_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(3'h6),
.Y(_zz__zz_decode_BRANCH_CTRL_2_75)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _385_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5:4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(5'h16),
.Y(_zz__zz_decode_BRANCH_CTRL_2_76)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _386_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(2'h1),
.Y(_zz__zz_decode_BRANCH_CTRL_2_78)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _387_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(2'h1),
.Y(_zz__zz_decode_BRANCH_CTRL_2_81)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _388_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:13]),
.B(1'h1),
.Y(_117_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _389_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15]),
.Y(_118_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _390_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:13]),
.B(2'h3),
.Y(_119_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _391_ (
.A(IBusSimplePlugin_rspJoin_rspBuffer_discardCounter),
.Y(_120_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _392_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }),
.B(3'h7),
.Y(_zz__zz_decode_BRANCH_CTRL_2_79)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _393_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:13], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] }),
.B(3'h2),
.Y(_zz__zz_decode_BRANCH_CTRL_2_26)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _394_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:3]),
.Y(_zz__zz_decode_BRANCH_CTRL_2_39)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _395_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }),
.B(2'h1),
.Y(_zz__zz_decode_BRANCH_CTRL_2_46)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _396_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] }),
.B(2'h3),
.Y(_zz__zz_decode_BRANCH_CTRL_2_48)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _397_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:3] }),
.B(3'h4),
.Y(_zz_decode_BRANCH_CTRL[0])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _398_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:2]),
.B(3'h1),
.Y(_121_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _399_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] }),
.B(5'h03),
.Y(decode_IS_EBREAK)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _400_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11:7]),
.Y(when_RegFilePlugin_l63)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _401_ (
.A(decode_to_execute_SRC1[31]),
.B(decode_to_execute_SRC2[31]),
.Y(_122_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.Y_WIDTH(32'd1)
) _402_ (
.A(execute_LightShifterPlugin_amplitude[4:1]),
.Y(execute_LightShifterPlugin_done)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _403_ (
.A(HazardSimplePlugin_writeBackBuffer_payload_address),
.B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15]),
.Y(HazardSimplePlugin_addr0Match)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _404_ (
.A(HazardSimplePlugin_writeBackBuffer_payload_address),
.B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:20]),
.Y(HazardSimplePlugin_addr1Match)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _405_ (
.A(memory_to_writeBack_INSTRUCTION[11:7]),
.B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15]),
.Y(when_HazardSimplePlugin_l59)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _406_ (
.A(memory_to_writeBack_INSTRUCTION[11:7]),
.B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:20]),
.Y(when_HazardSimplePlugin_l62)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _407_ (
.A(execute_to_memory_INSTRUCTION[11:7]),
.B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15]),
.Y(when_HazardSimplePlugin_l59_1)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _408_ (
.A(execute_to_memory_INSTRUCTION[11:7]),
.B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:20]),
.Y(when_HazardSimplePlugin_l62_1)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _409_ (
.A(decode_to_execute_INSTRUCTION[11:7]),
.B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15]),
.Y(when_HazardSimplePlugin_l59_2)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.B_SIGNED(32'd0),
.B_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _410_ (
.A(decode_to_execute_INSTRUCTION[11:7]),
.B(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:20]),
.Y(when_HazardSimplePlugin_l62_2)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd32),
.B_SIGNED(32'd0),
.B_WIDTH(32'd32),
.Y_WIDTH(32'd1)
) _411_ (
.A(decode_to_execute_SRC1),
.B(decode_to_execute_SRC2),
.Y(execute_BranchPlugin_eq)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _412_ (
.A(decode_to_execute_BRANCH_CTRL),
.B(2'h3),
.Y(_123_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd12),
.B_SIGNED(32'd0),
.B_WIDTH(32'd10),
.Y_WIDTH(32'd1)
) _413_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:20]),
.B(10'h300),
.Y(_124_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd12),
.B_SIGNED(32'd0),
.B_WIDTH(32'd10),
.Y_WIDTH(32'd1)
) _414_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:20]),
.B(10'h344),
.Y(_125_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd12),
.B_SIGNED(32'd0),
.B_WIDTH(32'd10),
.Y_WIDTH(32'd1)
) _415_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:20]),
.B(10'h304),
.Y(_126_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd12),
.B_SIGNED(32'd0),
.B_WIDTH(32'd10),
.Y_WIDTH(32'd1)
) _416_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:20]),
.B(10'h342),
.Y(_127_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _417_ (
.A(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid),
.B(_170_),
.Y(_zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _418_ (
.A(_110_),
.B(execute_LightShifterPlugin_shiftInput[31]),
.Y(_zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1[31])
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _419_ (
.A(_142_),
.B(decode_IS_EBREAK),
.Y(_128_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _420_ (
.A(_128_),
.B(DebugPlugin_allowEBreak),
.Y(decode_DO_EBREAK)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _421_ (
.A(decode_SRC_ADD_ZERO),
.B(_143_),
.Y(decode_SRC2_FORCE_ZERO)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _422_ (
.A(_117_),
.B(_118_),
.Y(_129_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _423_ (
.A(_119_),
.B(_118_),
.Y(_130_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _424_ (
.A(IBusSimplePlugin_fetchPc_output_valid),
.B(IBusSimplePlugin_fetchPc_output_ready),
.Y(IBusSimplePlugin_fetchPc_output_fire_1)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _425_ (
.A(_144_),
.B(IBusSimplePlugin_fetchPc_output_ready),
.Y(when_Fetcher_l131_1)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _426_ (
.A(IBusSimplePlugin_fetchPc_booted),
.B(_166_),
.Y(when_Fetcher_l158)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _427_ (
.A(_145_),
.B(IBusSimplePlugin_fetchPc_booted),
.Y(IBusSimplePlugin_fetchPc_output_valid)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _428_ (
.A(IBusSimplePlugin_iBusRsp_stages_1_output_ready),
.B(_zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready),
.Y(IBusSimplePlugin_fetchPc_output_ready)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _429_ (
.A(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2),
.B(_zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready),
.Y(IBusSimplePlugin_iBusRsp_stages_1_output_valid)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _430_ (
.A(IBusSimplePlugin_iBusRsp_stages_1_output_ready),
.B(_171_),
.Y(IBusSimplePlugin_cmdFork_canEmit)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _431_ (
.A(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2),
.B(_167_),
.Y(when_IBusSimplePlugin_l305)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _432_ (
.A(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2),
.B(IBusSimplePlugin_cmdFork_canEmit),
.Y(IBusSimplePlugin_cmd_valid)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _433_ (
.A(IBusSimplePlugin_cmd_valid),
.B(iBus_cmd_ready),
.Y(IBusSimplePlugin_cmd_fire)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _434_ (
.A(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid),
.B(_120_),
.Y(IBusSimplePlugin_rspJoin_rspBuffer_output_valid)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _435_ (
.A(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid),
.B(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready),
.Y(IBusSimplePlugin_pending_dec)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _436_ (
.A(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid),
.B(IBusSimplePlugin_rspJoin_rspBuffer_output_valid),
.Y(IBusSimplePlugin_iBusRsp_output_valid)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _437_ (
.A(IBusSimplePlugin_iBusRsp_output_valid),
.B(IBusSimplePlugin_rspJoin_join_ready),
.Y(IBusSimplePlugin_rspJoin_join_fire)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _438_ (
.A(execute_arbitration_isValid),
.B(decode_to_execute_MEMORY_ENABLE),
.Y(_131_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _439_ (
.A(_131_),
.B(_148_),
.Y(_132_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _440_ (
.A(_132_),
.B(_149_),
.Y(dBus_cmd_valid)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _441_ (
.A(_131_),
.B(_150_),
.Y(when_DBusSimplePlugin_l428)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _442_ (
.A(memory_arbitration_isValid),
.B(execute_to_memory_MEMORY_ENABLE),
.Y(_133_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _443_ (
.A(_133_),
.B(_151_),
.Y(_134_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _444_ (
.A(_134_),
.B(_152_),
.Y(when_DBusSimplePlugin_l482)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _445_ (
.A(_zz_writeBack_DBusSimplePlugin_rspFormated_1[7]),
.B(_153_),
.Y(_zz_writeBack_DBusSimplePlugin_rspFormated)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _446_ (
.A(_zz_writeBack_DBusSimplePlugin_rspFormated_3[15]),
.B(_153_),
.Y(_zz_writeBack_DBusSimplePlugin_rspFormated_2)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _447_ (
.A(writeBack_arbitration_isValid),
.B(memory_to_writeBack_MEMORY_ENABLE),
.Y(when_DBusSimplePlugin_l558)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _448_ (
.A(CsrPlugin_mip_MTIP),
.B(CsrPlugin_mie_MTIE),
.Y(_zz_when_CsrPlugin_l952)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _449_ (
.A(CsrPlugin_mip_MSIP),
.B(CsrPlugin_mie_MSIE),
.Y(_zz_when_CsrPlugin_l952_1)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _450_ (
.A(CsrPlugin_mip_MEIP),
.B(CsrPlugin_mie_MEIE),
.Y(_zz_when_CsrPlugin_l952_2)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _451_ (
.A(CsrPlugin_interrupt_valid),
.B(CsrPlugin_allowInterrupts),
.Y(_135_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _452_ (
.A(_135_),
.B(decode_arbitration_isValid),
.Y(CsrPlugin_pipelineLiberator_active)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _453_ (
.A(CsrPlugin_interrupt_valid),
.B(CsrPlugin_pipelineLiberator_pcValids_2),
.Y(_136_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _454_ (
.A(_136_),
.B(CsrPlugin_allowInterrupts),
.Y(CsrPlugin_interruptJump)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _455_ (
.A(writeBack_arbitration_isValid),
.B(memory_to_writeBack_ENV_CTRL),
.Y(when_CsrPlugin_l1064)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _456_ (
.A(execute_arbitration_isValid),
.B(decode_to_execute_ENV_CTRL),
.Y(_137_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _457_ (
.A(memory_arbitration_isValid),
.B(execute_to_memory_ENV_CTRL),
.Y(_138_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _458_ (
.A(execute_arbitration_isValid),
.B(decode_to_execute_IS_CSR),
.Y(when_CsrPlugin_l1176)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _459_ (
.A(when_CsrPlugin_l1176),
.B(decode_to_execute_CSR_WRITE_OPCODE),
.Y(execute_CsrPlugin_writeInstruction)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _460_ (
.A(execute_CsrPlugin_writeInstruction),
.B(_155_),
.Y(execute_CsrPlugin_writeEnable)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _461_ (
.A(memory_to_writeBack_REGFILE_WRITE_VALID),
.B(writeBack_arbitration_isValid),
.Y(HazardSimplePlugin_writeBackWrites_valid)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _462_ (
.A(execute_arbitration_isValid),
.B(execute_LightShifterPlugin_isShift),
.Y(_139_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _463_ (
.A(_139_),
.B(_172_),
.Y(when_ShiftPlugins_l169)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _464_ (
.A(memory_arbitration_isValid),
.B(execute_to_memory_REGFILE_WRITE_VALID),
.Y(when_HazardSimplePlugin_l57_1)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _465_ (
.A(execute_arbitration_isValid),
.B(decode_to_execute_REGFILE_WRITE_VALID),
.Y(when_HazardSimplePlugin_l57_2)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _466_ (
.A(decode_arbitration_isValid),
.B(_168_),
.Y(when_HazardSimplePlugin_l113)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _467_ (
.A(memory_arbitration_isValid),
.B(execute_to_memory_BRANCH_DO),
.Y(BranchPlugin_jumpInterface_valid)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _468_ (
.A(DebugPlugin_debugUsed),
.B(_158_),
.Y(DebugPlugin_allowEBreak)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _469_ (
.A(execute_arbitration_isValid),
.B(decode_to_execute_DO_EBREAK),
.Y(when_DebugPlugin_l295)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _470_ (
.A(DebugPlugin_stepIt),
.B(IBusSimplePlugin_incomingInstruction),
.Y(when_DebugPlugin_l311)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _471_ (
.A(_159_),
.B(_148_),
.Y(when_Pipeline_l124_40)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _472_ (
.A(IBusSimplePlugin_rspJoin_join_ready),
.B(_160_),
.Y(when_Pipeline_l154)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _473_ (
.A(_155_),
.B(_161_),
.Y(when_Pipeline_l154_1)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _474_ (
.A(_159_),
.B(_162_),
.Y(when_Pipeline_l154_2)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _475_ (
.A(IBusSimplePlugin_iBusRsp_stages_1_output_valid),
.B(_163_),
.Y(_140_)
);
\$logic_and #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _476_ (
.A(IBusSimplePlugin_iBusRsp_output_valid),
.B(_163_),
.Y(_141_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _477_ (
.A(DebugPlugin_haltIt),
.Y(_142_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _478_ (
.A(decode_SRC_USE_SUB_LESS),
.Y(_143_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _479_ (
.A(_164_),
.Y(decode_CSR_WRITE_OPCODE)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _480_ (
.A(IBusSimplePlugin_fetchPc_output_valid),
.Y(_144_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _481_ (
.A(IBusSimplePlugin_fetcherHalt),
.Y(_145_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _482_ (
.A(IBusSimplePlugin_iBusRsp_stages_1_halt),
.Y(_zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _483_ (
.A(decode_arbitration_isStuck),
.Y(IBusSimplePlugin_rspJoin_join_ready)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _484_ (
.A(IBusSimplePlugin_cmdFork_canEmit),
.Y(_146_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _485_ (
.A(iBus_cmd_ready),
.Y(_147_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _486_ (
.A(execute_arbitration_isStuckByOthers),
.Y(_148_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _487_ (
.A(execute_arbitration_isFlushed),
.Y(_149_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _488_ (
.A(dBus_cmd_ready),
.Y(_150_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _489_ (
.A(execute_to_memory_MEMORY_STORE),
.Y(_151_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _490_ (
.A(dBus_rsp_ready),
.Y(_152_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _491_ (
.A(memory_to_writeBack_INSTRUCTION[14]),
.Y(_153_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _492_ (
.A(CsrPlugin_pipelineLiberator_active),
.Y(_154_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _493_ (
.A(execute_arbitration_isStuck),
.Y(_155_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _494_ (
.A(execute_BranchPlugin_eq),
.Y(_156_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _495_ (
.A(execute_SRC_LESS),
.Y(_157_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _496_ (
.A(DebugPlugin_disableEbreak),
.Y(_158_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _497_ (
.A(memory_arbitration_isStuck),
.Y(_159_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _498_ (
.A(decode_arbitration_removeIt),
.Y(_160_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _499_ (
.A(execute_arbitration_removeIt),
.Y(_161_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _500_ (
.A(memory_arbitration_removeIt),
.Y(_162_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _501_ (
.A(IBusSimplePlugin_externalFlush),
.Y(_163_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _502_ (
.A(_129_),
.B(_130_),
.Y(_164_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _503_ (
.A(IBusSimplePlugin_fetchPc_correction),
.B(IBusSimplePlugin_fetchPc_pcRegPropagate),
.Y(when_Fetcher_l131)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _504_ (
.A(IBusSimplePlugin_fetchPc_output_ready),
.B(IBusSimplePlugin_fetchPc_correction),
.Y(_165_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _505_ (
.A(_165_),
.B(IBusSimplePlugin_fetchPc_pcRegPropagate),
.Y(_166_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _506_ (
.A(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2),
.B(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid),
.Y(when_Fetcher_l240)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _507_ (
.A(_146_),
.B(_147_),
.Y(_167_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _508_ (
.A(_170_),
.B(IBusSimplePlugin_externalFlush),
.Y(IBusSimplePlugin_rspJoin_rspBuffer_flush)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _509_ (
.A(IBusSimplePlugin_rspJoin_join_fire),
.B(IBusSimplePlugin_rspJoin_rspBuffer_flush),
.Y(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _510_ (
.A(_154_),
.B(decode_arbitration_removeIt),
.Y(when_CsrPlugin_l985)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _511_ (
.A(HazardSimplePlugin_src0Hazard),
.B(HazardSimplePlugin_src1Hazard),
.Y(_168_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _512_ (
.A(DebugPlugin_haltIt),
.B(DebugPlugin_stepIt),
.Y(when_DebugPlugin_l327)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _513_ (
.A(IBusSimplePlugin_externalFlush),
.B(execute_arbitration_flushIt),
.Y(decode_arbitration_isFlushed)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _514_ (
.A(_174_),
.B(execute_arbitration_flushIt),
.Y(execute_arbitration_isFlushed)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _515_ (
.A(execute_arbitration_isStuck),
.B(memory_arbitration_isStuck),
.Y(_169_)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _516_ (
.A(decode_arbitration_haltByOther),
.B(_169_),
.Y(decode_arbitration_isStuckByOthers)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _517_ (
.A(decode_arbitration_haltItself),
.B(decode_arbitration_isStuckByOthers),
.Y(decode_arbitration_isStuck)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _518_ (
.A(execute_arbitration_haltByOther),
.B(memory_arbitration_isStuck),
.Y(execute_arbitration_isStuckByOthers)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _519_ (
.A(execute_arbitration_haltItself),
.B(execute_arbitration_isStuckByOthers),
.Y(execute_arbitration_isStuck)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _520_ (
.A(_155_),
.B(execute_arbitration_removeIt),
.Y(when_Pipeline_l151)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _521_ (
.A(_159_),
.B(memory_arbitration_removeIt),
.Y(when_Pipeline_l151_1)
);
\$logic_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _522_ (
.A(_175_),
.B(IBusSimplePlugin_incomingInstruction),
.Y(_012_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _523_ (
.A(IBusSimplePlugin_rspJoin_rspBuffer_discardCounter),
.Y(_170_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _524_ (
.A({ CsrPlugin_jumpInterface_valid, memory_arbitration_flushNext, execute_arbitration_flushIt }),
.Y(IBusSimplePlugin_externalFlush)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _525_ (
.A({ BranchPlugin_jumpInterface_valid, CsrPlugin_jumpInterface_valid }),
.Y(IBusSimplePlugin_jump_pcLoad_valid)
);
\$ne #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _526_ (
.A(IBusSimplePlugin_pending_value),
.B(3'h7),
.Y(_171_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _527_ (
.A(decode_to_execute_SHIFT_CTRL),
.Y(execute_LightShifterPlugin_isShift)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd5),
.Y_WIDTH(32'd1)
) _528_ (
.A(decode_to_execute_SRC2[4:0]),
.Y(_172_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _529_ (
.A({ writeBack_arbitration_isValid, memory_arbitration_isValid }),
.Y(_173_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _530_ (
.A({ CsrPlugin_jumpInterface_valid, memory_arbitration_flushNext }),
.Y(_174_)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _531_ (
.A(switch_Fetcher_l362),
.Y(when_Fetcher_l398)
);
\$reduce_bool #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.Y_WIDTH(32'd1)
) _532_ (
.A({ writeBack_arbitration_isValid, memory_arbitration_isValid, execute_arbitration_isValid, decode_arbitration_isValid }),
.Y(_175_)
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _533_ (
.A(_zz_IBusSimplePlugin_jump_pcLoad_payload_2[0]),
.Y(_108_[0])
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd32),
.Y_WIDTH(32'd32)
) _534_ (
.A(decode_to_execute_SRC2),
.Y(_176_)
);
\$not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd13),
.Y_WIDTH(32'd13)
) _535_ (
.A(decode_to_execute_SRC1[12:0]),
.Y(_109_[12:0])
);
\$or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd32),
.B_SIGNED(32'd0),
.B_WIDTH(32'd32),
.Y_WIDTH(32'd32)
) _536_ (
.A(decode_to_execute_SRC1),
.B(decode_to_execute_SRC2),
.Y(_177_)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) DebugPlugin_haltIt_reg /* _537_ */ (
.ARST(resetCtrl_mainClkReset),
.CLK(io_mainClk),
.D(_010_),
.Q(DebugPlugin_haltIt)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) DebugPlugin_haltedByBreak_reg /* _538_ */ (
.ARST(resetCtrl_mainClkReset),
.CLK(io_mainClk),
.D(_011_),
.Q(DebugPlugin_haltedByBreak)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) DebugPlugin_isPipBusy_reg /* _539_ */ (
.CLK(io_mainClk),
.D(_012_),
.Q(DebugPlugin_isPipBusy)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) _zz_when_DebugPlugin_l244_reg /* _540_ */ (
.CLK(io_mainClk),
.D(debug_bus_cmd_payload_address[2]),
.Q(_zz_when_DebugPlugin_l244)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) DebugPlugin_resetIt_regNext_reg /* _541_ */ (
.CLK(io_mainClk),
.D(DebugPlugin_resetIt),
.Q(DebugPlugin_resetIt_regNext)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) CsrPlugin_mip_MEIP_reg /* _542_ */ (
.CLK(io_mainClk),
.D(externalInterrupt),
.Q(CsrPlugin_mip_MEIP)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) CsrPlugin_mip_MTIP_reg /* _543_ */ (
.CLK(io_mainClk),
.D(timerInterrupt),
.Q(CsrPlugin_mip_MTIP)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) CsrPlugin_mip_MSIP_reg /* _544_ */ (
.CLK(io_mainClk),
.D(_002_),
.Q(CsrPlugin_mip_MSIP)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd5)
) _545_ (
.CLK(io_mainClk),
.D(memory_to_writeBack_INSTRUCTION[11:7]),
.Q(HazardSimplePlugin_writeBackBuffer_payload_address)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd30)
) _546_ (
.CLK(io_mainClk),
.D(execute_to_memory_INSTRUCTION),
.Q(memory_to_writeBack_INSTRUCTION[29:0])
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) memory_to_writeBack_MEMORY_ENABLE_reg /* _547_ */ (
.CLK(io_mainClk),
.D(execute_to_memory_MEMORY_ENABLE),
.Q(memory_to_writeBack_MEMORY_ENABLE)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) memory_to_writeBack_REGFILE_WRITE_VALID_reg /* _548_ */ (
.CLK(io_mainClk),
.D(execute_to_memory_REGFILE_WRITE_VALID),
.Q(memory_to_writeBack_REGFILE_WRITE_VALID)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) memory_to_writeBack_ENV_CTRL_reg /* _549_ */ (
.CLK(io_mainClk),
.D(execute_to_memory_ENV_CTRL),
.Q(memory_to_writeBack_ENV_CTRL)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd2)
) _550_ (
.CLK(io_mainClk),
.D(execute_to_memory_MEMORY_ADDRESS_LOW),
.Q(memory_to_writeBack_MEMORY_ADDRESS_LOW)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd32)
) _551_ (
.CLK(io_mainClk),
.D(execute_to_memory_REGFILE_WRITE_DATA),
.Q(memory_to_writeBack_REGFILE_WRITE_DATA)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd32)
) _552_ (
.CLK(io_mainClk),
.D(dBus_rsp_data),
.Q(memory_to_writeBack_MEMORY_READ_DATA)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) writeBack_arbitration_isValid_reg /* _553_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_023_),
.Q(writeBack_arbitration_isValid)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) IBusSimplePlugin_fetchPc_booted_reg /* _554_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(1'h1),
.Q(IBusSimplePlugin_fetchPc_booted)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(3'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd3)
) _555_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(IBusSimplePlugin_pending_next),
.Q(IBusSimplePlugin_pending_value)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(3'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd3)
) _556_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_014_),
.Q(IBusSimplePlugin_rspJoin_rspBuffer_discardCounter)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) CsrPlugin_mstatus_MIE_reg /* _557_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_003_),
.Q(CsrPlugin_mstatus_MIE)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) CsrPlugin_mstatus_MPIE_reg /* _558_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_004_),
.Q(CsrPlugin_mstatus_MPIE)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(2'h3),
.CLK_POLARITY(1'h1),
.WIDTH(32'd2)
) _559_ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_005_),
.Q(CsrPlugin_mstatus_MPP)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) CsrPlugin_interrupt_valid_reg /* _560_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(_001_),
.Q(CsrPlugin_interrupt_valid)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h1),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) _zz_2_reg /* _561_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(1'h0),
.Q(_zz_2)
);
\$adff #(
.ARST_POLARITY(1'h1),
.ARST_VALUE(1'h0),
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) HazardSimplePlugin_writeBackBuffer_valid_reg /* _562_ */ (
.ARST(resetCtrl_systemReset),
.CLK(io_mainClk),
.D(HazardSimplePlugin_writeBackWrites_valid),
.Q(HazardSimplePlugin_writeBackBuffer_valid)
);
\$mux #(
.WIDTH(32'd1)
) _563_ (
.A(1'h1),
.B(1'h0),
.S(debug_bus_cmd_payload_data[26]),
.Y(_178_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd6),
.Y_WIDTH(32'd1)
) _564_ (
.A(debug_bus_cmd_payload_address[7:2]),
.Y(_179_)
);
\$mux #(
.WIDTH(32'd1)
) _565_ (
.A(DebugPlugin_haltedByBreak),
.B(1'h0),
.S(debug_bus_cmd_payload_data[25]),
.Y(_180_)
);
\$mux #(
.WIDTH(32'd1)
) _566_ (
.A(DebugPlugin_haltedByBreak),
.B(_180_),
.S(debug_bus_cmd_payload_wr),
.Y(_181_)
);
\$mux #(
.WIDTH(32'd1)
) _567_ (
.A(DebugPlugin_haltedByBreak),
.B(_181_),
.S(_179_),
.Y(_182_)
);
\$mux #(
.WIDTH(32'd1)
) _568_ (
.A(DebugPlugin_haltedByBreak),
.B(_182_),
.S(debug_bus_cmd_valid),
.Y(_183_)
);
\$mux #(
.WIDTH(32'd1)
) _569_ (
.A(1'h1),
.B(_183_),
.S(_173_),
.Y(_184_)
);
\$mux #(
.WIDTH(32'd1)
) _570_ (
.A(_183_),
.B(_184_),
.S(when_DebugPlugin_l295),
.Y(_011_)
);
\$mux #(
.WIDTH(32'd1)
) _571_ (
.A(DebugPlugin_haltIt),
.B(1'h1),
.S(debug_bus_cmd_payload_data[17]),
.Y(_185_)
);
\$mux #(
.WIDTH(32'd1)
) _572_ (
.A(_185_),
.B(1'h0),
.S(debug_bus_cmd_payload_data[25]),
.Y(_186_)
);
\$mux #(
.WIDTH(32'd1)
) _573_ (
.A(DebugPlugin_haltIt),
.B(_186_),
.S(debug_bus_cmd_payload_wr),
.Y(_187_)
);
\$mux #(
.WIDTH(32'd1)
) _574_ (
.A(DebugPlugin_haltIt),
.B(_187_),
.S(_179_),
.Y(_188_)
);
\$mux #(
.WIDTH(32'd1)
) _575_ (
.A(DebugPlugin_haltIt),
.B(_188_),
.S(debug_bus_cmd_valid),
.Y(_189_)
);
\$mux #(
.WIDTH(32'd1)
) _576_ (
.A(1'h1),
.B(_189_),
.S(_173_),
.Y(_190_)
);
\$mux #(
.WIDTH(32'd1)
) _577_ (
.A(_189_),
.B(_190_),
.S(when_DebugPlugin_l295),
.Y(_191_)
);
\$mux #(
.WIDTH(32'd1)
) _578_ (
.A(_191_),
.B(1'h1),
.S(decode_arbitration_isValid),
.Y(_192_)
);
\$mux #(
.WIDTH(32'd1)
) _579_ (
.A(_191_),
.B(_192_),
.S(when_DebugPlugin_l311),
.Y(_010_)
);
\$mux #(
.WIDTH(32'd1)
) _580_ (
.A(1'h1),
.B(1'h0),
.S(debug_bus_cmd_payload_data[24]),
.Y(_193_)
);
\$mux #(
.WIDTH(32'd32)
) _581_ (
.A(_zz_lastStageRegFileWrite_payload_data),
.B({ decode_to_execute_PC[31:2], 2'h0 }),
.S(when_DebugPlugin_l295),
.Y(_009_)
);
\$mux #(
.WIDTH(32'd1)
) _582_ (
.A(softwareInterrupt),
.B(CsrPlugin_csrMapping_writeDataSignal[3]),
.S(execute_CsrPlugin_writeEnable),
.Y(_194_)
);
\$mux #(
.WIDTH(32'd1)
) _583_ (
.A(softwareInterrupt),
.B(_194_),
.S(execute_CsrPlugin_csr_836),
.Y(_002_)
);
\$mux #(
.WIDTH(32'd25)
) _584_ (
.A(IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[24:0]),
.B({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24:15], 15'hxxxx }),
.S(decode_arbitration_isStuck),
.Y(decode_INSTRUCTION_ANTICIPATED[24:0])
);
\$mux #(
.WIDTH(32'd32)
) _585_ (
.A({ IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[31:25], decode_INSTRUCTION_ANTICIPATED[24:0] }),
.B(debug_bus_cmd_payload_data),
.S(when_Fetcher_l398),
.Y(_017_)
);
\$mux #(
.WIDTH(32'd1)
) _586_ (
.A(1'h0),
.B(1'h1),
.S(_zz_when_CsrPlugin_l952),
.Y(_195_)
);
\$mux #(
.WIDTH(32'd1)
) _587_ (
.A(_195_),
.B(1'h1),
.S(_zz_when_CsrPlugin_l952_1),
.Y(_196_)
);
\$mux #(
.WIDTH(32'd1)
) _588_ (
.A(_196_),
.B(1'h1),
.S(_zz_when_CsrPlugin_l952_2),
.Y(_197_)
);
\$mux #(
.WIDTH(32'd1)
) _589_ (
.A(1'h0),
.B(_197_),
.S(CsrPlugin_mstatus_MIE),
.Y(_198_)
);
\$mux #(
.WIDTH(32'd1)
) _590_ (
.A(_198_),
.B(1'h0),
.S(CsrPlugin_interruptJump),
.Y(_001_)
);
\$mux #(
.WIDTH(32'd3)
) _591_ (
.A(_243_),
.B(IBusSimplePlugin_pending_next),
.S(IBusSimplePlugin_externalFlush),
.Y(_014_)
);
\$pmux #(
.S_WIDTH(32'd5),
.WIDTH(32'd3)
) _592_ (
.A(3'hx),
.B(15'h14e0),
.S({ _203_, _202_, _201_, _200_, _199_ }),
.Y(_022_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _593_ (
.A(switch_Fetcher_l362),
.B(3'h4),
.Y(_199_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _594_ (
.A(switch_Fetcher_l362),
.B(2'h3),
.Y(_200_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _595_ (
.A(switch_Fetcher_l362),
.B(2'h2),
.Y(_201_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _596_ (
.A(switch_Fetcher_l362),
.B(1'h1),
.Y(_202_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _597_ (
.A(switch_Fetcher_l362),
.Y(_203_)
);
\$mux #(
.WIDTH(32'd1)
) _598_ (
.A(1'h1),
.B(1'h0),
.S(execute_LightShifterPlugin_done),
.Y(_204_)
);
\$mux #(
.WIDTH(32'd1)
) _599_ (
.A(_204_),
.B(1'h0),
.S(execute_arbitration_removeIt),
.Y(_019_)
);
\$mux #(
.WIDTH(32'd1)
) _600_ (
.A(CsrPlugin_pipelineLiberator_pcValids_1),
.B(1'h0),
.S(when_CsrPlugin_l985),
.Y(_008_)
);
\$mux #(
.WIDTH(32'd1)
) _601_ (
.A(CsrPlugin_pipelineLiberator_pcValids_0),
.B(1'h0),
.S(when_CsrPlugin_l985),
.Y(_007_)
);
\$mux #(
.WIDTH(32'd1)
) _602_ (
.A(1'h1),
.B(1'h0),
.S(when_CsrPlugin_l985),
.Y(_006_)
);
\$mux #(
.WIDTH(32'd2)
) _603_ (
.A(CsrPlugin_mstatus_MPP),
.B(2'h3),
.S(CsrPlugin_interruptJump),
.Y(_205_)
);
\$mux #(
.WIDTH(32'd2)
) _604_ (
.A(_205_),
.B(2'h0),
.S(_207_),
.Y(_206_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _605_ (
.A(memory_to_writeBack_INSTRUCTION[29:28]),
.B(2'h3),
.Y(_207_)
);
\$mux #(
.WIDTH(32'd2)
) _606_ (
.A(_205_),
.B(_206_),
.S(when_CsrPlugin_l1064),
.Y(_208_)
);
\$mux #(
.WIDTH(32'd2)
) _607_ (
.A(_208_),
.B(CsrPlugin_csrMapping_writeDataSignal[12:11]),
.S(execute_CsrPlugin_writeEnable),
.Y(_209_)
);
\$mux #(
.WIDTH(32'd2)
) _608_ (
.A(_208_),
.B(_209_),
.S(execute_CsrPlugin_csr_768),
.Y(_005_)
);
\$mux #(
.WIDTH(32'd1)
) _609_ (
.A(CsrPlugin_mstatus_MPIE),
.B(CsrPlugin_mstatus_MIE),
.S(CsrPlugin_interruptJump),
.Y(_210_)
);
\$mux #(
.WIDTH(32'd1)
) _610_ (
.A(_210_),
.B(1'h1),
.S(_207_),
.Y(_211_)
);
\$mux #(
.WIDTH(32'd1)
) _611_ (
.A(_210_),
.B(_211_),
.S(when_CsrPlugin_l1064),
.Y(_212_)
);
\$mux #(
.WIDTH(32'd1)
) _612_ (
.A(_212_),
.B(CsrPlugin_csrMapping_writeDataSignal[7]),
.S(execute_CsrPlugin_writeEnable),
.Y(_213_)
);
\$mux #(
.WIDTH(32'd1)
) _613_ (
.A(_212_),
.B(_213_),
.S(execute_CsrPlugin_csr_768),
.Y(_004_)
);
\$mux #(
.WIDTH(32'd1)
) _614_ (
.A(CsrPlugin_mstatus_MIE),
.B(1'h0),
.S(CsrPlugin_interruptJump),
.Y(_214_)
);
\$mux #(
.WIDTH(32'd1)
) _615_ (
.A(_214_),
.B(CsrPlugin_mstatus_MPIE),
.S(_207_),
.Y(_215_)
);
\$mux #(
.WIDTH(32'd1)
) _616_ (
.A(_214_),
.B(_215_),
.S(when_CsrPlugin_l1064),
.Y(_216_)
);
\$mux #(
.WIDTH(32'd1)
) _617_ (
.A(_216_),
.B(CsrPlugin_csrMapping_writeDataSignal[3]),
.S(execute_CsrPlugin_writeEnable),
.Y(_217_)
);
\$mux #(
.WIDTH(32'd1)
) _618_ (
.A(_216_),
.B(_217_),
.S(execute_CsrPlugin_csr_768),
.Y(_003_)
);
\$mux #(
.WIDTH(32'd1)
) _619_ (
.A(_141_),
.B(1'h0),
.S(decode_arbitration_isStuck),
.Y(_018_)
);
\$mux #(
.WIDTH(32'd1)
) _620_ (
.A(1'h0),
.B(_140_),
.S(IBusSimplePlugin_iBusRsp_stages_1_output_ready),
.Y(_016_)
);
\$mux #(
.WIDTH(32'd1)
) _621_ (
.A(1'h0),
.B(IBusSimplePlugin_fetchPc_output_valid),
.S(IBusSimplePlugin_fetchPc_output_ready),
.Y(_015_)
);
\$mux #(
.WIDTH(32'd1)
) _622_ (
.A(1'h0),
.B(1'h1),
.S(IBusSimplePlugin_fetchPc_output_fire_1),
.Y(_218_)
);
\$mux #(
.WIDTH(32'd1)
) _623_ (
.A(_218_),
.B(1'h0),
.S(when_Fetcher_l131_1),
.Y(_013_)
);
\$mux #(
.WIDTH(32'd1)
) _624_ (
.A(1'h0),
.B(memory_arbitration_isValid),
.S(when_Pipeline_l154_2),
.Y(_023_)
);
\$mux #(
.WIDTH(32'd1)
) _625_ (
.A(1'h0),
.B(execute_arbitration_isValid),
.S(when_Pipeline_l154_1),
.Y(_021_)
);
\$mux #(
.WIDTH(32'd1)
) _626_ (
.A(1'h0),
.B(decode_arbitration_isValid),
.S(when_Pipeline_l154),
.Y(_020_)
);
\$mux #(
.WIDTH(32'd3)
) _627_ (
.A(3'h0),
.B({ CsrPlugin_mcause_exceptionCode[3:2], 1'h1 }),
.S(execute_CsrPlugin_csr_834),
.Y(_zz_CsrPlugin_csrMapping_readDataInit_3[3:1])
);
\$mux #(
.WIDTH(32'd1)
) _628_ (
.A(1'h0),
.B(1'h1),
.S(execute_CsrPlugin_csr_834),
.Y(_zz_CsrPlugin_csrMapping_readDataInit_3[31])
);
\$mux #(
.WIDTH(32'd1)
) _629_ (
.A(1'h0),
.B(CsrPlugin_mie_MSIE),
.S(execute_CsrPlugin_csr_772),
.Y(_zz_CsrPlugin_csrMapping_readDataInit_2[3])
);
\$mux #(
.WIDTH(32'd1)
) _630_ (
.A(1'h0),
.B(CsrPlugin_mie_MTIE),
.S(execute_CsrPlugin_csr_772),
.Y(_zz_CsrPlugin_csrMapping_readDataInit_2[7])
);
\$mux #(
.WIDTH(32'd1)
) _631_ (
.A(1'h0),
.B(CsrPlugin_mie_MEIE),
.S(execute_CsrPlugin_csr_772),
.Y(_zz_CsrPlugin_csrMapping_readDataInit_2[11])
);
\$mux #(
.WIDTH(32'd1)
) _632_ (
.A(1'h0),
.B(CsrPlugin_mip_MSIP),
.S(execute_CsrPlugin_csr_836),
.Y(_zz_CsrPlugin_csrMapping_readDataInit_1[3])
);
\$mux #(
.WIDTH(32'd1)
) _633_ (
.A(1'h0),
.B(CsrPlugin_mip_MTIP),
.S(execute_CsrPlugin_csr_836),
.Y(_zz_CsrPlugin_csrMapping_readDataInit_1[7])
);
\$mux #(
.WIDTH(32'd1)
) _634_ (
.A(1'h0),
.B(CsrPlugin_mip_MEIP),
.S(execute_CsrPlugin_csr_836),
.Y(_zz_CsrPlugin_csrMapping_readDataInit_1[11])
);
\$mux #(
.WIDTH(32'd1)
) _635_ (
.A(1'h0),
.B(CsrPlugin_mstatus_MIE),
.S(execute_CsrPlugin_csr_768),
.Y(_zz_CsrPlugin_csrMapping_readDataInit[3])
);
\$mux #(
.WIDTH(32'd1)
) _636_ (
.A(1'h0),
.B(CsrPlugin_mstatus_MPIE),
.S(execute_CsrPlugin_csr_768),
.Y(_zz_CsrPlugin_csrMapping_readDataInit[7])
);
\$mux #(
.WIDTH(32'd2)
) _637_ (
.A(2'h0),
.B(CsrPlugin_mstatus_MPP),
.S(execute_CsrPlugin_csr_768),
.Y(_zz_CsrPlugin_csrMapping_readDataInit[12:11])
);
\$mux #(
.WIDTH(32'd1)
) _638_ (
.A(1'h0),
.B(1'h1),
.S(_199_),
.Y(IBusSimplePlugin_injectionPort_ready)
);
\$mux #(
.WIDTH(32'd1)
) _639_ (
.A(1'h0),
.B(1'h1),
.S(debug_bus_cmd_payload_wr),
.Y(_045_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd6),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _640_ (
.A(debug_bus_cmd_payload_address[7:2]),
.B(1'h1),
.Y(_219_)
);
\$mux #(
.WIDTH(32'd1)
) _641_ (
.A(1'h0),
.B(_045_),
.S(_219_),
.Y(_036_)
);
\$mux #(
.WIDTH(32'd1)
) _642_ (
.A(1'h0),
.B(_036_),
.S(debug_bus_cmd_valid),
.Y(IBusSimplePlugin_injectionPort_valid)
);
\$mux #(
.WIDTH(32'd1)
) _643_ (
.A(DebugPlugin_stepIt),
.B(DebugPlugin_busReadDataReg[4]),
.S(_zz_when_DebugPlugin_l244),
.Y(debug_bus_rsp_data[4])
);
\$mux #(
.WIDTH(32'd1)
) _644_ (
.A(DebugPlugin_isPipBusy),
.B(DebugPlugin_busReadDataReg[2]),
.S(_zz_when_DebugPlugin_l244),
.Y(debug_bus_rsp_data[2])
);
\$mux #(
.WIDTH(32'd1)
) _645_ (
.A(DebugPlugin_haltIt),
.B(DebugPlugin_busReadDataReg[1]),
.S(_zz_when_DebugPlugin_l244),
.Y(debug_bus_rsp_data[1])
);
\$mux #(
.WIDTH(32'd1)
) _646_ (
.A(DebugPlugin_resetIt),
.B(DebugPlugin_busReadDataReg[0]),
.S(_zz_when_DebugPlugin_l244),
.Y(debug_bus_rsp_data[0])
);
\$mux #(
.WIDTH(32'd1)
) _647_ (
.A(DebugPlugin_haltedByBreak),
.B(DebugPlugin_busReadDataReg[3]),
.S(_zz_when_DebugPlugin_l244),
.Y(debug_bus_rsp_data[3])
);
\$mux #(
.WIDTH(32'd1)
) _648_ (
.A(1'h1),
.B(IBusSimplePlugin_injectionPort_ready),
.S(debug_bus_cmd_payload_wr),
.Y(_046_)
);
\$mux #(
.WIDTH(32'd1)
) _649_ (
.A(1'h1),
.B(_046_),
.S(_219_),
.Y(_037_)
);
\$mux #(
.WIDTH(32'd1)
) _650_ (
.A(1'h1),
.B(_037_),
.S(debug_bus_cmd_valid),
.Y(debug_bus_cmd_ready)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd14)
) _651_ (
.A({ decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[7], decode_to_execute_INSTRUCTION[11:8], 1'h0 }),
.B({ decode_to_execute_INSTRUCTION[19:12], decode_to_execute_INSTRUCTION[20], decode_to_execute_INSTRUCTION[24:21], 1'h0, decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[24:20] }),
.S({ _220_, _123_ }),
.Y({ execute_BranchPlugin_branch_src2[19:11], execute_BranchPlugin_branch_src2[4:0] })
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _652_ (
.A(decode_to_execute_BRANCH_CTRL),
.B(2'h2),
.Y(_220_)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd1)
) _653_ (
.A(_zz_execute_BRANCH_DO),
.B(2'h1),
.S({ _221_, _105_ }),
.Y(_zz_execute_BRANCH_DO_1)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _654_ (
.A(decode_to_execute_BRANCH_CTRL),
.Y(_221_)
);
\$pmux #(
.S_WIDTH(32'd3),
.WIDTH(32'd1)
) _655_ (
.A(execute_SRC_LESS),
.B({ execute_BranchPlugin_eq, _156_, _157_ }),
.S({ _224_, _223_, _222_ }),
.Y(_zz_execute_BRANCH_DO)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _656_ (
.A({ decode_to_execute_INSTRUCTION[14], decode_to_execute_INSTRUCTION[12] }),
.B(2'h3),
.Y(_222_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _657_ (
.A(decode_to_execute_INSTRUCTION[14:12]),
.B(1'h1),
.Y(_223_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _658_ (
.A(decode_to_execute_INSTRUCTION[14:12]),
.Y(_224_)
);
\$mux #(
.WIDTH(32'd1)
) _659_ (
.A(1'h0),
.B(_058_),
.S(_zz__zz_decode_BRANCH_CTRL_2_32),
.Y(HazardSimplePlugin_src1Hazard)
);
\$mux #(
.WIDTH(32'd1)
) _660_ (
.A(_054_),
.B(1'h1),
.S(when_HazardSimplePlugin_l62_2),
.Y(_025_)
);
\$mux #(
.WIDTH(32'd1)
) _661_ (
.A(_054_),
.B(_025_),
.S(when_HazardSimplePlugin_l57_2),
.Y(_058_)
);
\$mux #(
.WIDTH(32'd1)
) _662_ (
.A(_043_),
.B(1'h1),
.S(when_HazardSimplePlugin_l62_1),
.Y(_056_)
);
\$mux #(
.WIDTH(32'd1)
) _663_ (
.A(_043_),
.B(_056_),
.S(when_HazardSimplePlugin_l57_1),
.Y(_054_)
);
\$mux #(
.WIDTH(32'd1)
) _664_ (
.A(_028_),
.B(1'h1),
.S(when_HazardSimplePlugin_l62),
.Y(_049_)
);
\$mux #(
.WIDTH(32'd1)
) _665_ (
.A(_028_),
.B(_049_),
.S(HazardSimplePlugin_writeBackWrites_valid),
.Y(_043_)
);
\$mux #(
.WIDTH(32'd1)
) _666_ (
.A(1'h0),
.B(1'h1),
.S(HazardSimplePlugin_addr1Match),
.Y(_035_)
);
\$mux #(
.WIDTH(32'd1)
) _667_ (
.A(1'h0),
.B(_035_),
.S(HazardSimplePlugin_writeBackBuffer_valid),
.Y(_028_)
);
\$mux #(
.WIDTH(32'd1)
) _668_ (
.A(1'h0),
.B(_057_),
.S(_zz__zz_decode_BRANCH_CTRL_2_65),
.Y(HazardSimplePlugin_src0Hazard)
);
\$mux #(
.WIDTH(32'd1)
) _669_ (
.A(_053_),
.B(1'h1),
.S(when_HazardSimplePlugin_l59_2),
.Y(_024_)
);
\$mux #(
.WIDTH(32'd1)
) _670_ (
.A(_053_),
.B(_024_),
.S(when_HazardSimplePlugin_l57_2),
.Y(_057_)
);
\$mux #(
.WIDTH(32'd1)
) _671_ (
.A(_042_),
.B(1'h1),
.S(when_HazardSimplePlugin_l59_1),
.Y(_055_)
);
\$mux #(
.WIDTH(32'd1)
) _672_ (
.A(_042_),
.B(_055_),
.S(when_HazardSimplePlugin_l57_1),
.Y(_053_)
);
\$mux #(
.WIDTH(32'd1)
) _673_ (
.A(_027_),
.B(1'h1),
.S(when_HazardSimplePlugin_l59),
.Y(_048_)
);
\$mux #(
.WIDTH(32'd1)
) _674_ (
.A(_027_),
.B(_048_),
.S(HazardSimplePlugin_writeBackWrites_valid),
.Y(_042_)
);
\$mux #(
.WIDTH(32'd1)
) _675_ (
.A(1'h0),
.B(1'h1),
.S(HazardSimplePlugin_addr0Match),
.Y(_034_)
);
\$mux #(
.WIDTH(32'd1)
) _676_ (
.A(1'h0),
.B(_034_),
.S(HazardSimplePlugin_writeBackBuffer_valid),
.Y(_027_)
);
\$mux #(
.WIDTH(32'd32)
) _677_ (
.A({ _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1[31], execute_LightShifterPlugin_shiftInput[31:1] }),
.B({ execute_LightShifterPlugin_shiftInput[30:0], 1'h0 }),
.S(_225_),
.Y(_zz_execute_to_memory_REGFILE_WRITE_DATA_1)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _678_ (
.A(decode_to_execute_SHIFT_CTRL),
.B(1'h1),
.Y(_225_)
);
\$mux #(
.WIDTH(32'd32)
) _679_ (
.A(_zz_execute_SrcPlugin_addSub),
.B(decode_to_execute_SRC1),
.S(decode_to_execute_SRC2_FORCE_ZERO),
.Y(execute_SrcPlugin_addSub)
);
\$pmux #(
.S_WIDTH(32'd3),
.WIDTH(32'd32)
) _680_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2], 2'h0 }),
.B({ _zz_RegFilePlugin_regFile_port1, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:20], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:25], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11:7] }),
.S({ _228_, _227_, _226_ }),
.Y(_zz_decode_SRC2_6)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _681_ (
.A({ decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 }),
.B(2'h2),
.Y(_226_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _682_ (
.A({ decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 }),
.B(1'h1),
.Y(_227_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _683_ (
.A({ decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 }),
.Y(_228_)
);
\$pmux #(
.S_WIDTH(32'd3),
.WIDTH(32'd32)
) _684_ (
.A({ 27'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15] }),
.B({ _zz_RegFilePlugin_regFile_port0, 32'h00000004, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:12], 12'h000 }),
.S({ _231_, _230_, _229_ }),
.Y(_zz_decode_SRC1_1)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _685_ (
.A({ _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }),
.B(1'h1),
.Y(_229_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _686_ (
.A({ _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }),
.B(2'h2),
.Y(_230_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _687_ (
.A({ _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 }),
.Y(_231_)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd32)
) _688_ (
.A(execute_SrcPlugin_addSub),
.B({ execute_IntAluPlugin_bitwise, 31'h00000000, execute_SRC_LESS }),
.S({ _233_, _232_ }),
.Y(_zz_execute_REGFILE_WRITE_DATA)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _689_ (
.A(decode_to_execute_ALU_CTRL),
.B(1'h1),
.Y(_232_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _690_ (
.A(decode_to_execute_ALU_CTRL),
.B(2'h2),
.Y(_233_)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd32)
) _691_ (
.A(_247_),
.B({ _061_, _177_ }),
.S({ _235_, _234_ }),
.Y(execute_IntAluPlugin_bitwise)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _692_ (
.A(decode_to_execute_ALU_BITWISE_CTRL),
.B(1'h1),
.Y(_234_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _693_ (
.A(decode_to_execute_ALU_BITWISE_CTRL),
.B(2'h2),
.Y(_235_)
);
\$mux #(
.WIDTH(32'd32)
) _694_ (
.A(_zz_lastStageRegFileWrite_payload_data),
.B(32'd0),
.S(_zz_2),
.Y(lastStageRegFileWrite_payload_data)
);
\$mux #(
.WIDTH(32'd5)
) _695_ (
.A(memory_to_writeBack_INSTRUCTION[11:7]),
.B(5'h00),
.S(_zz_2),
.Y(lastStageRegFileWrite_payload_address)
);
\$mux #(
.WIDTH(32'd1)
) _696_ (
.A(HazardSimplePlugin_writeBackWrites_valid),
.B(1'h1),
.S(_zz_2),
.Y(lastStageRegFileWrite_valid)
);
\$mux #(
.WIDTH(32'd13)
) _697_ (
.A(decode_to_execute_SRC1[12:0]),
.B(_245_[12:0]),
.S(decode_to_execute_INSTRUCTION[13]),
.Y(CsrPlugin_csrMapping_writeDataSignal)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd24)
) _698_ (
.A({ memory_to_writeBack_MEMORY_READ_DATA[31:16], _zz_writeBack_DBusSimplePlugin_rspFormated_3[15:8] }),
.B({ _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_3[15:8] }),
.S({ _237_, _236_ }),
.Y(writeBack_DBusSimplePlugin_rspFormated[31:8])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _699_ (
.A(memory_to_writeBack_INSTRUCTION[13:12]),
.B(1'h1),
.Y(_236_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _700_ (
.A(memory_to_writeBack_INSTRUCTION[13:12]),
.Y(_237_)
);
\$mux #(
.WIDTH(32'd8)
) _701_ (
.A(memory_to_writeBack_MEMORY_READ_DATA[15:8]),
.B(memory_to_writeBack_MEMORY_READ_DATA[31:24]),
.S(_238_),
.Y(_zz_writeBack_DBusSimplePlugin_rspFormated_3[15:8])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _702_ (
.A(memory_to_writeBack_MEMORY_ADDRESS_LOW),
.B(2'h2),
.Y(_238_)
);
\$pmux #(
.S_WIDTH(32'd3),
.WIDTH(32'd8)
) _703_ (
.A(memory_to_writeBack_MEMORY_READ_DATA[7:0]),
.B({ memory_to_writeBack_MEMORY_READ_DATA[15:8], memory_to_writeBack_MEMORY_READ_DATA[23:16], memory_to_writeBack_MEMORY_READ_DATA[31:24] }),
.S({ _240_, _238_, _239_ }),
.Y(_zz_writeBack_DBusSimplePlugin_rspFormated_1[7:0])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _704_ (
.A(memory_to_writeBack_MEMORY_ADDRESS_LOW),
.B(2'h3),
.Y(_239_)
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _705_ (
.A(memory_to_writeBack_MEMORY_ADDRESS_LOW),
.B(1'h1),
.Y(_240_)
);
\$pmux #(
.S_WIDTH(32'd2),
.WIDTH(32'd24)
) _706_ (
.A(decode_to_execute_RS2[31:8]),
.B({ decode_to_execute_RS2[7:0], decode_to_execute_RS2[7:0], decode_to_execute_RS2[7:0], decode_to_execute_RS2[15:0], decode_to_execute_RS2[15:8] }),
.S({ _242_, _241_ }),
.Y(dBus_cmd_payload_data[31:8])
);
\$eq #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.B_SIGNED(32'd0),
.B_WIDTH(32'd1),
.Y_WIDTH(32'd1)
) _707_ (
.A(decode_to_execute_INSTRUCTION[13:12]),
.B(1'h1),
.Y(_241_)
);
\$logic_not #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _708_ (
.A(decode_to_execute_INSTRUCTION[13:12]),
.Y(_242_)
);
\$mux #(
.WIDTH(32'd1)
) _709_ (
.A(_zz_IBusSimplePlugin_injector_decodeInput_valid),
.B(1'h1),
.S(_106_),
.Y(decode_arbitration_isValid)
);
\$mux #(
.WIDTH(32'd1)
) _710_ (
.A(1'h0),
.B(1'h1),
.S(when_IBusSimplePlugin_l305),
.Y(IBusSimplePlugin_iBusRsp_stages_1_halt)
);
\$mux #(
.WIDTH(32'd31)
) _711_ (
.A({ _059_[31:2], 1'h0 }),
.B(IBusSimplePlugin_jump_pcLoad_payload[31:1]),
.S(IBusSimplePlugin_jump_pcLoad_valid),
.Y({ IBusSimplePlugin_fetchPc_pc[31:2], _029_[1] })
);
\$mux #(
.WIDTH(32'd1)
) _712_ (
.A(1'h0),
.B(1'h1),
.S(IBusSimplePlugin_fetchPc_output_ready),
.Y(IBusSimplePlugin_fetchPc_pcRegPropagate)
);
\$mux #(
.WIDTH(32'd1)
) _713_ (
.A(1'h0),
.B(1'h1),
.S(IBusSimplePlugin_jump_pcLoad_valid),
.Y(IBusSimplePlugin_fetchPc_correction)
);
\$mux #(
.WIDTH(32'd1)
) _714_ (
.A(1'h1),
.B(1'h0),
.S(when_DebugPlugin_l327),
.Y(CsrPlugin_allowInterrupts)
);
\$mux #(
.WIDTH(32'd30)
) _715_ (
.A(30'h20000008),
.B(CsrPlugin_mepc[31:2]),
.S(_207_),
.Y(_041_[31:2])
);
\$mux #(
.WIDTH(32'd30)
) _716_ (
.A(30'h20000008),
.B(_041_[31:2]),
.S(when_CsrPlugin_l1064),
.Y(CsrPlugin_jumpInterface_payload[31:2])
);
\$mux #(
.WIDTH(32'd1)
) _717_ (
.A(_026_),
.B(1'h1),
.S(when_CsrPlugin_l1064),
.Y(CsrPlugin_jumpInterface_valid)
);
\$mux #(
.WIDTH(32'd1)
) _718_ (
.A(1'h0),
.B(1'h1),
.S(CsrPlugin_interruptJump),
.Y(_026_)
);
\$mux #(
.WIDTH(32'd1)
) _719_ (
.A(_030_),
.B(1'h1),
.S(_zz_IBusSimplePlugin_injector_decodeInput_valid),
.Y(IBusSimplePlugin_incomingInstruction)
);
\$mux #(
.WIDTH(32'd1)
) _720_ (
.A(1'h0),
.B(1'h1),
.S(when_Fetcher_l240),
.Y(_030_)
);
\$mux #(
.WIDTH(32'd1)
) _721_ (
.A(_051_),
.B(1'h1),
.S(when_DebugPlugin_l311),
.Y(IBusSimplePlugin_fetcherHalt)
);
\$mux #(
.WIDTH(32'd1)
) _722_ (
.A(_044_),
.B(1'h1),
.S(DebugPlugin_haltIt),
.Y(_051_)
);
\$mux #(
.WIDTH(32'd1)
) _723_ (
.A(1'h1),
.B(CsrPlugin_jumpInterface_valid),
.S(_173_),
.Y(_050_)
);
\$mux #(
.WIDTH(32'd1)
) _724_ (
.A(CsrPlugin_jumpInterface_valid),
.B(_050_),
.S(when_DebugPlugin_l295),
.Y(_044_)
);
\$mux #(
.WIDTH(32'd1)
) _725_ (
.A(1'h0),
.B(1'h1),
.S(BranchPlugin_jumpInterface_valid),
.Y(memory_arbitration_flushNext)
);
\$mux #(
.WIDTH(32'd1)
) _726_ (
.A(1'h0),
.B(1'h1),
.S(CsrPlugin_jumpInterface_valid),
.Y(memory_arbitration_removeIt)
);
\$mux #(
.WIDTH(32'd1)
) _727_ (
.A(1'h0),
.B(1'h1),
.S(when_DBusSimplePlugin_l482),
.Y(memory_arbitration_isStuck)
);
\$mux #(
.WIDTH(32'd1)
) _728_ (
.A(1'h1),
.B(1'h0),
.S(_173_),
.Y(_039_)
);
\$mux #(
.WIDTH(32'd1)
) _729_ (
.A(1'h0),
.B(_039_),
.S(when_DebugPlugin_l295),
.Y(execute_arbitration_flushIt)
);
\$mux #(
.WIDTH(32'd1)
) _730_ (
.A(1'h0),
.B(1'h1),
.S(execute_arbitration_isFlushed),
.Y(execute_arbitration_removeIt)
);
\$mux #(
.WIDTH(32'd1)
) _731_ (
.A(1'h0),
.B(1'h1),
.S(when_DebugPlugin_l295),
.Y(execute_arbitration_haltByOther)
);
\$mux #(
.WIDTH(32'd1)
) _732_ (
.A(1'h1),
.B(_040_),
.S(execute_LightShifterPlugin_done),
.Y(_052_)
);
\$mux #(
.WIDTH(32'd1)
) _733_ (
.A(_040_),
.B(_052_),
.S(when_ShiftPlugins_l169),
.Y(execute_arbitration_haltItself)
);
\$mux #(
.WIDTH(32'd1)
) _734_ (
.A(_033_),
.B(1'h1),
.S(execute_CsrPlugin_blockedBySideEffects),
.Y(_047_)
);
\$mux #(
.WIDTH(32'd1)
) _735_ (
.A(_033_),
.B(_047_),
.S(when_CsrPlugin_l1176),
.Y(_040_)
);
\$mux #(
.WIDTH(32'd1)
) _736_ (
.A(1'h0),
.B(1'h1),
.S(when_DBusSimplePlugin_l428),
.Y(_033_)
);
\$mux #(
.WIDTH(32'd1)
) _737_ (
.A(1'h0),
.B(1'h1),
.S(decode_arbitration_isFlushed),
.Y(decode_arbitration_removeIt)
);
\$mux #(
.WIDTH(32'd1)
) _738_ (
.A(_038_),
.B(1'h1),
.S(when_HazardSimplePlugin_l113),
.Y(decode_arbitration_haltByOther)
);
\$mux #(
.WIDTH(32'd1)
) _739_ (
.A(_032_),
.B(1'h1),
.S(when_CsrPlugin_l1116),
.Y(_038_)
);
\$mux #(
.WIDTH(32'd1)
) _740_ (
.A(1'h0),
.B(1'h1),
.S(CsrPlugin_pipelineLiberator_active),
.Y(_032_)
);
\$mux #(
.WIDTH(32'd1)
) _741_ (
.A(1'h0),
.B(1'h1),
.S(_201_),
.Y(decode_arbitration_haltItself)
);
\$mux #(
.WIDTH(32'd32)
) _742_ (
.A(memory_to_writeBack_REGFILE_WRITE_DATA),
.B({ writeBack_DBusSimplePlugin_rspFormated[31:8], _zz_writeBack_DBusSimplePlugin_rspFormated_1[7:0] }),
.S(when_DBusSimplePlugin_l558),
.Y(_zz_lastStageRegFileWrite_payload_data)
);
\$mux #(
.WIDTH(32'd32)
) _743_ (
.A(_031_),
.B(_zz_execute_to_memory_REGFILE_WRITE_DATA_1),
.S(when_ShiftPlugins_l169),
.Y(_zz_execute_to_memory_REGFILE_WRITE_DATA)
);
\$mux #(
.WIDTH(32'd32)
) _744_ (
.A(_zz_execute_REGFILE_WRITE_DATA),
.B({ _zz_CsrPlugin_csrMapping_readDataInit_3[31], 18'h00000, _zz_CsrPlugin_csrMapping_readDataInit[12], execute_CsrPlugin_readToWriteData[11], 3'h0, execute_CsrPlugin_readToWriteData[7], 3'h0, execute_CsrPlugin_readToWriteData[3], _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1] }),
.S(when_CsrPlugin_l1176),
.Y(_031_)
);
\$mux #(
.WIDTH(32'd1)
) _745_ (
.A(1'h0),
.B(1'h1),
.S(lastStageRegFileWrite_valid),
.Y(_zz_1)
);
\$mux #(
.WIDTH(32'd1)
) _746_ (
.A(1'h0),
.B(1'h1),
.S(_zz_1),
.Y(_000_[31])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _747_ (
.A({ _112_, _111_ }),
.Y(decode_SRC_ADD_ZERO)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _748_ (
.A(_zz__zz_decode_BRANCH_CTRL_2_18),
.Y(decode_SRC_LESS_UNSIGNED)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _749_ (
.A({ _114_, _113_ }),
.Y(_zz__zz_decode_BRANCH_CTRL_2_21)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _750_ (
.A(_zz__zz_decode_BRANCH_CTRL_2_29),
.Y(decode_IS_CSR)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _751_ (
.A({ _116_, _115_ }),
.Y(_zz__zz_decode_BRANCH_CTRL_2_32)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd6),
.Y_WIDTH(32'd1)
) _752_ (
.A({ _zz__zz_decode_BRANCH_CTRL_2_52, _zz__zz_decode_BRANCH_CTRL_2_49[4], _zz__zz_decode_BRANCH_CTRL_2_49[1:0], _zz__zz_decode_BRANCH_CTRL_2_48, _zz__zz_decode_BRANCH_CTRL_2_46 }),
.Y(_zz__zz_decode_BRANCH_CTRL_2_47)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _753_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], _zz__zz_decode_BRANCH_CTRL_2_60[0] }),
.Y(decode_SRC2_CTRL[1])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _754_ (
.A({ _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], _zz__zz_decode_BRANCH_CTRL_2_64 }),
.Y(_zz__zz_decode_BRANCH_CTRL_2_63)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd4),
.Y_WIDTH(32'd1)
) _755_ (
.A({ _zz__zz_decode_BRANCH_CTRL_2_69, _zz__zz_decode_BRANCH_CTRL_2_66, _zz__zz_decode_BRANCH_CTRL_2_39, _zz__zz_decode_BRANCH_CTRL_2_26 }),
.Y(_zz__zz_decode_BRANCH_CTRL_2_65)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _756_ (
.A({ _zz__zz_decode_BRANCH_CTRL_2_76, _zz__zz_decode_BRANCH_CTRL_2_75, _zz__zz_decode_BRANCH_CTRL_2_74 }),
.Y(decode_SRC_USE_SUB_LESS)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _757_ (
.A({ _zz__zz_decode_BRANCH_CTRL_2_79, _zz__zz_decode_BRANCH_CTRL_2_78 }),
.Y(_zz__zz_decode_BRANCH_CTRL_2_77)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _758_ (
.A({ _zz__zz_decode_BRANCH_CTRL_2_81, _zz__zz_decode_BRANCH_CTRL_2_79 }),
.Y(_zz__zz_decode_BRANCH_CTRL_2_80)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd3),
.Y_WIDTH(32'd1)
) _759_ (
.A({ _138_, _137_, when_CsrPlugin_l1064 }),
.Y(when_CsrPlugin_l1116)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _760_ (
.A({ writeBack_arbitration_isValid, memory_arbitration_isValid }),
.Y(execute_CsrPlugin_blockedBySideEffects)
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _761_ (
.A(_zz__zz_decode_BRANCH_CTRL_2_5),
.Y(_zz_decode_BRANCH_CTRL_2[21])
);
\$reduce_or #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd2),
.Y_WIDTH(32'd1)
) _762_ (
.A({ _121_, _zz__zz_decode_BRANCH_CTRL_2_48 }),
.Y(_zz_decode_BRANCH_CTRL[1])
);
\$mux #(
.WIDTH(32'd32)
) _763_ (
.A(decode_to_execute_SRC2),
.B(_176_),
.S(decode_to_execute_SRC_USE_SUB_LESS),
.Y(_zz_execute_SrcPlugin_addSub_3)
);
\$mux #(
.WIDTH(32'd1)
) _764_ (
.A(1'h0),
.B(1'h1),
.S(decode_to_execute_SRC_USE_SUB_LESS),
.Y(_zz_execute_SrcPlugin_addSub_4)
);
\$mux #(
.WIDTH(32'd31)
) _765_ (
.A(execute_to_memory_BRANCH_CALC[31:1]),
.B({ CsrPlugin_jumpInterface_payload[31:2], 1'h0 }),
.S(_zz_IBusSimplePlugin_jump_pcLoad_payload_1),
.Y(IBusSimplePlugin_jump_pcLoad_payload[31:1])
);
\$mux #(
.WIDTH(32'd1)
) _766_ (
.A(IBusSimplePlugin_rspJoin_join_ready),
.B(IBusSimplePlugin_rspJoin_join_fire),
.S(_zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid),
.Y(IBusSimplePlugin_iBusRsp_stages_1_output_ready)
);
\$mux #(
.WIDTH(32'd13)
) _767_ (
.A({ _104_[0], _104_[6], decode_to_execute_SRC1[10:8], _104_[5], decode_to_execute_SRC1[6:4], _104_[4:1] }),
.B({ _060_[12:11], 3'h0, _060_[7], 3'h0, _060_[3:0] }),
.S(decode_to_execute_INSTRUCTION[12]),
.Y(_245_[12:0])
);
\$mux #(
.WIDTH(32'd1)
) _768_ (
.A(decode_to_execute_SRC1[31]),
.B(decode_to_execute_SRC2[31]),
.S(decode_to_execute_SRC_LESS_UNSIGNED),
.Y(_246_)
);
\$mux #(
.WIDTH(32'd1)
) _769_ (
.A(_246_),
.B(execute_SrcPlugin_addSub[31]),
.S(_122_),
.Y(execute_SRC_LESS)
);
\$mux #(
.WIDTH(32'd5)
) _770_ (
.A(decode_to_execute_SRC2[4:0]),
.B(execute_LightShifterPlugin_amplitudeReg),
.S(execute_LightShifterPlugin_isActive),
.Y(execute_LightShifterPlugin_amplitude)
);
\$mux #(
.WIDTH(32'd32)
) _771_ (
.A(decode_to_execute_SRC1),
.B(execute_to_memory_REGFILE_WRITE_DATA),
.S(execute_LightShifterPlugin_isActive),
.Y(execute_LightShifterPlugin_shiftInput)
);
\$mux #(
.WIDTH(32'd32)
) _772_ (
.A({ decode_to_execute_PC[31:2], 2'h0 }),
.B(decode_to_execute_RS1),
.S(_123_),
.Y(execute_BranchPlugin_branch_src1)
);
\$xor #(
.A_SIGNED(32'd0),
.A_WIDTH(32'd32),
.B_SIGNED(32'd0),
.B_WIDTH(32'd32),
.Y_WIDTH(32'd32)
) _773_ (
.A(decode_to_execute_SRC1),
.B(decode_to_execute_SRC2),
.Y(_247_)
);
StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c (
.io_flush(1'h0),
.io_mainClk(io_mainClk),
.io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy),
.io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error),
.io_pop_payload_inst(IBusSimplePlugin_iBusRsp_output_payload_rsp_inst),
.io_pop_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready),
.io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid),
.io_push_payload_error(iBus_rsp_payload_error),
.io_push_payload_inst(iBus_rsp_payload_inst),
.io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready),
.io_push_valid(iBus_rsp_valid),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign _000_[30:0] = { _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31], _000_[31] };
assign { _029_[31:2], _029_[0] } = { IBusSimplePlugin_fetchPc_pc[31:2], 1'h0 };
assign _041_[1:0] = 2'h0;
assign _059_[1:0] = 2'h0;
assign { _060_[10:8], _060_[6:4] } = 6'h00;
assign _064_[1:0] = 2'h0;
assign _069_[1:0] = 2'h0;
assign _245_[31:13] = 19'hxxxxx;
assign BranchPlugin_jumpInterface_payload = { execute_to_memory_BRANCH_CALC[31:1], 1'h0 };
assign CsrPlugin_csrMapping_allowCsrSignal = 1'h0;
assign CsrPlugin_csrMapping_readDataInit = { _zz_CsrPlugin_csrMapping_readDataInit_3[31], 18'h00000, _zz_CsrPlugin_csrMapping_readDataInit[12], execute_CsrPlugin_readToWriteData[11], 3'h0, execute_CsrPlugin_readToWriteData[7], 3'h0, execute_CsrPlugin_readToWriteData[3], _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1] };
assign CsrPlugin_csrMapping_readDataSignal = { _zz_CsrPlugin_csrMapping_readDataInit_3[31], 18'h00000, _zz_CsrPlugin_csrMapping_readDataInit[12], execute_CsrPlugin_readToWriteData[11], 3'h0, execute_CsrPlugin_readToWriteData[7], 3'h0, execute_CsrPlugin_readToWriteData[3], _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1] };
assign CsrPlugin_exception = 1'h0;
assign CsrPlugin_hadException = 1'h0;
assign CsrPlugin_inWfi = 1'h0;
assign CsrPlugin_interrupt_code[1:0] = 2'h3;
assign CsrPlugin_interrupt_targetPrivilege = 2'h3;
assign CsrPlugin_jumpInterface_payload[1:0] = 2'h0;
assign CsrPlugin_lastStageWasWfi = 1'h0;
assign CsrPlugin_mcause_exceptionCode[1:0] = 2'h3;
assign CsrPlugin_mcause_interrupt = 1'h1;
assign CsrPlugin_mepc[1:0] = 2'h0;
assign CsrPlugin_misa_base = 2'h1;
assign CsrPlugin_misa_extensions = 26'h0000042;
assign CsrPlugin_mtvec_base = 30'h20000008;
assign CsrPlugin_mtvec_mode = 2'h0;
assign CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
assign CsrPlugin_privilege = 2'h3;
assign CsrPlugin_targetPrivilege = 2'h3;
assign CsrPlugin_trapCause = { CsrPlugin_interrupt_code[3:2], 2'h3 };
assign CsrPlugin_xtvec_base = 30'h20000008;
assign HazardSimplePlugin_writeBackWrites_payload_address = memory_to_writeBack_INSTRUCTION[11:7];
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_lastStageRegFileWrite_payload_data;
assign IBusSimplePlugin_cmd_payload_pc = { IBusSimplePlugin_fetchPc_pcReg[31:2], 2'h0 };
assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready;
assign IBusSimplePlugin_fetchPc_output_payload = { IBusSimplePlugin_fetchPc_pc[31:2], 2'h0 };
assign IBusSimplePlugin_fetchPc_pc[1:0] = 2'h0;
assign IBusSimplePlugin_fetchPc_pcReg[1:0] = 2'h0;
assign IBusSimplePlugin_iBusRsp_flush = IBusSimplePlugin_externalFlush;
assign IBusSimplePlugin_iBusRsp_output_payload_pc = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 };
assign IBusSimplePlugin_iBusRsp_output_ready = IBusSimplePlugin_rspJoin_join_ready;
assign IBusSimplePlugin_iBusRsp_redoFetch = 1'h0;
assign IBusSimplePlugin_iBusRsp_stages_0_halt = 1'h0;
assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = { IBusSimplePlugin_fetchPc_pc[31:2], 2'h0 };
assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = IBusSimplePlugin_fetchPc_output_ready;
assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid;
assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = { IBusSimplePlugin_fetchPc_pc[31:2], 2'h0 };
assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = IBusSimplePlugin_fetchPc_output_ready;
assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = IBusSimplePlugin_fetchPc_output_valid;
assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = { IBusSimplePlugin_fetchPc_pcReg[31:2], 2'h0 };
assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = IBusSimplePlugin_fetchPc_output_ready;
assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2;
assign IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 };
assign IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusSimplePlugin_iBusRsp_stages_1_output_ready;
assign IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = { IBusSimplePlugin_fetchPc_pcReg[31:2], 2'h0 };
assign IBusSimplePlugin_iBusRsp_stages_2_halt = 1'h0;
assign IBusSimplePlugin_iBusRsp_stages_2_input_payload = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 };
assign IBusSimplePlugin_iBusRsp_stages_2_input_ready = IBusSimplePlugin_iBusRsp_stages_1_output_ready;
assign IBusSimplePlugin_iBusRsp_stages_2_input_valid = _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusSimplePlugin_iBusRsp_stages_2_output_payload = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 };
assign IBusSimplePlugin_iBusRsp_stages_2_output_ready = IBusSimplePlugin_iBusRsp_stages_1_output_ready;
assign IBusSimplePlugin_iBusRsp_stages_2_output_valid = _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusSimplePlugin_injectionPort_payload = debug_bus_cmd_payload_data;
assign IBusSimplePlugin_injector_decodeInput_payload_pc = { _zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2], 2'h0 };
assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
assign IBusSimplePlugin_injector_decodeInput_ready = IBusSimplePlugin_rspJoin_join_ready;
assign IBusSimplePlugin_injector_decodeInput_valid = _zz_IBusSimplePlugin_injector_decodeInput_valid;
assign IBusSimplePlugin_jump_pcLoad_payload[0] = 1'h0;
assign IBusSimplePlugin_pending_inc = IBusSimplePlugin_cmd_fire;
assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'h0;
assign IBusSimplePlugin_rspJoin_fetchRsp_pc = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 };
assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst;
assign IBusSimplePlugin_rspJoin_join_fire_1 = IBusSimplePlugin_rspJoin_join_fire;
assign IBusSimplePlugin_rspJoin_join_payload_pc = { _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[31:2], 2'h0 };
assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst;
assign IBusSimplePlugin_rspJoin_join_valid = IBusSimplePlugin_iBusRsp_output_valid;
assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire = IBusSimplePlugin_pending_dec;
assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst;
assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error;
assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst;
assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = IBusSimplePlugin_rspJoin_join_fire;
assign { _zz_CsrPlugin_csrMapping_readDataInit[10:8], _zz_CsrPlugin_csrMapping_readDataInit[6:4], _zz_CsrPlugin_csrMapping_readDataInit[2:0] } = 9'h000;
assign { _zz_CsrPlugin_csrMapping_readDataInit_1[10:8], _zz_CsrPlugin_csrMapping_readDataInit_1[6:4], _zz_CsrPlugin_csrMapping_readDataInit_1[2:0] } = 9'h000;
assign { _zz_CsrPlugin_csrMapping_readDataInit_2[10:8], _zz_CsrPlugin_csrMapping_readDataInit_2[6:4], _zz_CsrPlugin_csrMapping_readDataInit_2[2:0] } = 9'h000;
assign { _zz_CsrPlugin_csrMapping_readDataInit_3[30:4], _zz_CsrPlugin_csrMapping_readDataInit_3[0] } = { 27'h0000000, _zz_CsrPlugin_csrMapping_readDataInit_3[1] };
assign _zz_CsrPlugin_csrMapping_writeDataSignal = CsrPlugin_csrMapping_writeDataSignal;
assign _zz_IBusSimplePlugin_fetchPc_pc = { 29'h00000000, IBusSimplePlugin_fetchPc_inc, 2'h0 };
assign _zz_IBusSimplePlugin_fetchPc_pc_1 = { IBusSimplePlugin_fetchPc_inc, 2'h0 };
assign _zz_IBusSimplePlugin_iBusRsp_output_valid = 1'h1;
assign _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready = 1'h1;
assign _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready = IBusSimplePlugin_fetchPc_output_ready;
assign _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2;
assign _zz_IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_payload[1:0] = 2'h0;
assign _zz_IBusSimplePlugin_iBusRsp_stages_2_input_ready = 1'h1;
assign _zz_IBusSimplePlugin_injector_decodeInput_payload_pc[1:0] = 2'h0;
assign _zz_IBusSimplePlugin_jump_pcLoad_payload = { BranchPlugin_jumpInterface_valid, CsrPlugin_jumpInterface_valid };
assign _zz_IBusSimplePlugin_pending_next_1 = { 2'h0, IBusSimplePlugin_cmd_fire };
assign _zz_IBusSimplePlugin_pending_next_2 = IBusSimplePlugin_cmd_fire;
assign _zz_IBusSimplePlugin_pending_next_3 = { 2'h0, IBusSimplePlugin_pending_dec };
assign _zz_IBusSimplePlugin_pending_next_4 = IBusSimplePlugin_pending_dec;
assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter = { 2'h0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1 };
assign _zz__zz_decode_BRANCH_CTRL_2 = { 27'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:2], 2'h0 };
assign _zz__zz_decode_BRANCH_CTRL_2_1 = 32'd4;
assign _zz__zz_decode_BRANCH_CTRL_2_10 = 32'd36;
assign _zz__zz_decode_BRANCH_CTRL_2_11 = { 18'h00000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13:12], 5'h00, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 };
assign _zz__zz_decode_BRANCH_CTRL_2_12 = 32'd4112;
assign _zz__zz_decode_BRANCH_CTRL_2_13 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12];
assign _zz__zz_decode_BRANCH_CTRL_2_14 = { 19'h00000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], 12'h000 };
assign _zz__zz_decode_BRANCH_CTRL_2_15 = 32'd4096;
assign { _zz__zz_decode_BRANCH_CTRL_2_16[18:12], _zz__zz_decode_BRANCH_CTRL_2_16[10], _zz__zz_decode_BRANCH_CTRL_2_16[8:0] } = { _zz__zz_decode_BRANCH_CTRL_2_17, decode_SRC_LESS_UNSIGNED, _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26, _zz__zz_decode_BRANCH_CTRL_2_28, decode_IS_CSR, _zz__zz_decode_BRANCH_CTRL_2_32, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], _zz__zz_decode_BRANCH_CTRL_2_46, _zz__zz_decode_BRANCH_CTRL_2_47, decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63, _zz__zz_decode_BRANCH_CTRL_2_65, _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 };
assign _zz__zz_decode_BRANCH_CTRL_2_19 = 32'd8208;
assign _zz__zz_decode_BRANCH_CTRL_2_2 = { 25'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4:3], 3'h0 };
assign _zz__zz_decode_BRANCH_CTRL_2_20 = 32'd20480;
assign _zz__zz_decode_BRANCH_CTRL_2_22 = { 17'h00000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14:13], 10'h000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 };
assign _zz__zz_decode_BRANCH_CTRL_2_23 = 32'd24576;
assign _zz__zz_decode_BRANCH_CTRL_2_24 = { 17'h00000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], 9'h000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 };
assign _zz__zz_decode_BRANCH_CTRL_2_25 = 32'd16384;
assign _zz__zz_decode_BRANCH_CTRL_2_27 = { _zz__zz_decode_BRANCH_CTRL_2_28, decode_IS_CSR, _zz__zz_decode_BRANCH_CTRL_2_32, _zz__zz_decode_BRANCH_CTRL_2_16[11], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], _zz__zz_decode_BRANCH_CTRL_2_16[9], _zz__zz_decode_BRANCH_CTRL_2_46, _zz__zz_decode_BRANCH_CTRL_2_47, decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63, _zz__zz_decode_BRANCH_CTRL_2_65, _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 };
assign _zz__zz_decode_BRANCH_CTRL_2_3 = 32'd64;
assign _zz__zz_decode_BRANCH_CTRL_2_30 = 32'd4176;
assign _zz__zz_decode_BRANCH_CTRL_2_31 = 32'd8272;
assign _zz__zz_decode_BRANCH_CTRL_2_33 = { 26'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5:4], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 };
assign _zz__zz_decode_BRANCH_CTRL_2_34 = 32'd32;
assign _zz__zz_decode_BRANCH_CTRL_2_35 = { 25'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:5], 2'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 };
assign _zz__zz_decode_BRANCH_CTRL_2_36 = 32'd32;
assign _zz__zz_decode_BRANCH_CTRL_2_37 = _zz__zz_decode_BRANCH_CTRL_2_16[11];
assign _zz__zz_decode_BRANCH_CTRL_2_41 = 32'd1060928;
assign _zz__zz_decode_BRANCH_CTRL_2_42 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], _zz__zz_decode_BRANCH_CTRL_2_16[9], _zz__zz_decode_BRANCH_CTRL_2_46, _zz__zz_decode_BRANCH_CTRL_2_47, decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63, _zz__zz_decode_BRANCH_CTRL_2_65, _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 };
assign _zz__zz_decode_BRANCH_CTRL_2_43 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5];
assign _zz__zz_decode_BRANCH_CTRL_2_44 = _zz__zz_decode_BRANCH_CTRL_2_16[9];
assign _zz__zz_decode_BRANCH_CTRL_2_45 = 32'd16;
assign _zz__zz_decode_BRANCH_CTRL_2_49[3:2] = { _zz__zz_decode_BRANCH_CTRL_2_52, _zz__zz_decode_BRANCH_CTRL_2_46 };
assign _zz__zz_decode_BRANCH_CTRL_2_50 = { 19'h00000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], 7'h00, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4], 4'h0 };
assign _zz__zz_decode_BRANCH_CTRL_2_51 = 32'd4112;
assign _zz__zz_decode_BRANCH_CTRL_2_53 = _zz__zz_decode_BRANCH_CTRL_2_46;
assign _zz__zz_decode_BRANCH_CTRL_2_54 = _zz__zz_decode_BRANCH_CTRL_2_49[1:0];
assign _zz__zz_decode_BRANCH_CTRL_2_55 = { 28'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3:2], 2'h0 };
assign _zz__zz_decode_BRANCH_CTRL_2_56 = 32'd4;
assign _zz__zz_decode_BRANCH_CTRL_2_57 = { 26'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], 1'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3], 3'h0 };
assign _zz__zz_decode_BRANCH_CTRL_2_58 = 32'd0;
assign _zz__zz_decode_BRANCH_CTRL_2_59 = { decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63, _zz__zz_decode_BRANCH_CTRL_2_65, _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 };
assign _zz__zz_decode_BRANCH_CTRL_2_6 = 32'd1073754196;
assign _zz__zz_decode_BRANCH_CTRL_2_60[1] = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2];
assign _zz__zz_decode_BRANCH_CTRL_2_61 = { 25'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:4], 4'h0 };
assign _zz__zz_decode_BRANCH_CTRL_2_62 = 32'd32;
assign _zz__zz_decode_BRANCH_CTRL_2_67 = 32'd68;
assign _zz__zz_decode_BRANCH_CTRL_2_68 = { _zz__zz_decode_BRANCH_CTRL_2_39, _zz__zz_decode_BRANCH_CTRL_2_26, _zz__zz_decode_BRANCH_CTRL_2_69 };
assign _zz__zz_decode_BRANCH_CTRL_2_7 = 32'd28756;
assign _zz__zz_decode_BRANCH_CTRL_2_70 = { _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 };
assign _zz__zz_decode_BRANCH_CTRL_2_72 = 32'd88;
assign _zz__zz_decode_BRANCH_CTRL_2_73 = decode_SRC_USE_SUB_LESS;
assign _zz__zz_decode_BRANCH_CTRL_2_8 = decode_SRC_ADD_ZERO;
assign _zz__zz_decode_BRANCH_CTRL_2_82 = _zz__zz_decode_BRANCH_CTRL_2_79;
assign _zz__zz_decode_BRANCH_CTRL_2_9 = { 25'h0000000, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6:5], 2'h0, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2], 2'h0 };
assign _zz__zz_decode_SRC1_1 = 3'h4;
assign _zz__zz_decode_SRC1_1_1 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19:15];
assign _zz__zz_decode_SRC2_4 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:25], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11:7] };
assign _zz__zz_execute_BranchPlugin_branch_src2 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[19:12], decode_to_execute_INSTRUCTION[20], decode_to_execute_INSTRUCTION[30:21] };
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[7], decode_to_execute_INSTRUCTION[30:25], decode_to_execute_INSTRUCTION[11:8] };
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1[30:0] = execute_LightShifterPlugin_shiftInput[31:1];
assign _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1 = { _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1[31], execute_LightShifterPlugin_shiftInput };
assign _zz_dBus_cmd_payload_data = { dBus_cmd_payload_data[31:8], decode_to_execute_RS2[7:0] };
assign _zz_dBus_cmd_valid = 1'h0;
assign _zz_decode_ALU_BITWISE_CTRL = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 };
assign _zz_decode_ALU_BITWISE_CTRL_1 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 };
assign _zz_decode_ALU_BITWISE_CTRL_2 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 };
assign _zz_decode_ALU_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 };
assign _zz_decode_ALU_CTRL_1 = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 };
assign _zz_decode_ALU_CTRL_2 = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 };
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign { _zz_decode_BRANCH_CTRL_2[25:22], _zz_decode_BRANCH_CTRL_2[20:0] } = { decode_IS_EBREAK, _zz_decode_BRANCH_CTRL, _zz__zz_decode_BRANCH_CTRL_2_4, decode_SRC_ADD_ZERO, _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17, decode_SRC_LESS_UNSIGNED, _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26, _zz__zz_decode_BRANCH_CTRL_2_28, decode_IS_CSR, _zz__zz_decode_BRANCH_CTRL_2_32, _zz__zz_decode_BRANCH_CTRL_2_16[11], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5], _zz__zz_decode_BRANCH_CTRL_2_16[9], _zz__zz_decode_BRANCH_CTRL_2_46, _zz__zz_decode_BRANCH_CTRL_2_47, decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63, _zz__zz_decode_BRANCH_CTRL_2_65, _zz__zz_decode_BRANCH_CTRL_2_71, decode_SRC_USE_SUB_LESS, _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 };
assign _zz_decode_BRANCH_CTRL_3 = _zz__zz_decode_BRANCH_CTRL_2_79;
assign _zz_decode_BRANCH_CTRL_4 = _zz__zz_decode_BRANCH_CTRL_2_26;
assign _zz_decode_BRANCH_CTRL_5 = _zz__zz_decode_BRANCH_CTRL_2_39;
assign _zz_decode_BRANCH_CTRL_6 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2];
assign _zz_decode_BRANCH_CTRL_7 = _zz__zz_decode_BRANCH_CTRL_2_46;
assign _zz_decode_BRANCH_CTRL_8 = _zz__zz_decode_BRANCH_CTRL_2_48;
assign _zz_decode_BRANCH_CTRL_9 = _zz_decode_BRANCH_CTRL;
assign _zz_decode_ENV_CTRL = _zz__zz_decode_BRANCH_CTRL_2_28;
assign _zz_decode_ENV_CTRL_1 = _zz__zz_decode_BRANCH_CTRL_2_28;
assign _zz_decode_ENV_CTRL_2 = _zz__zz_decode_BRANCH_CTRL_2_28;
assign _zz_decode_RegFilePlugin_rs1Data = 1'h1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'h1;
assign _zz_decode_SHIFT_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] };
assign _zz_decode_SHIFT_CTRL_1 = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] };
assign _zz_decode_SHIFT_CTRL_2 = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] };
assign _zz_decode_SRC1 = _zz_RegFilePlugin_regFile_port0;
assign _zz_decode_SRC1_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 };
assign _zz_decode_SRC1_CTRL_1 = { _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 };
assign _zz_decode_SRC1_CTRL_2 = { _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 };
assign _zz_decode_SRC2 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2], 2'h0 };
assign _zz_decode_SRC2_1 = _zz_RegFilePlugin_regFile_port1;
assign _zz_decode_SRC2_2 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31];
assign _zz_decode_SRC2_3 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] };
assign _zz_decode_SRC2_4 = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31];
assign _zz_decode_SRC2_5 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31], _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] };
assign _zz_decode_SRC2_CTRL = { decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 };
assign _zz_decode_SRC2_CTRL_1 = { decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 };
assign _zz_decode_SRC2_CTRL_2 = { decode_SRC2_CTRL[1], _zz__zz_decode_BRANCH_CTRL_2_63 };
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 };
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 };
assign _zz_decode_to_execute_ALU_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 };
assign _zz_decode_to_execute_ALU_CTRL_1 = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 };
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_BRANCH_CTRL;
assign _zz_decode_to_execute_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign _zz_decode_to_execute_ENV_CTRL = _zz__zz_decode_BRANCH_CTRL_2_28;
assign _zz_decode_to_execute_ENV_CTRL_1 = _zz__zz_decode_BRANCH_CTRL_2_28;
assign _zz_decode_to_execute_SHIFT_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] };
assign _zz_decode_to_execute_SHIFT_CTRL_1 = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] };
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign _zz_execute_BranchPlugin_branch_src2 = decode_to_execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_1 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31] };
assign _zz_execute_BranchPlugin_branch_src2_2 = decode_to_execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_3 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31] };
assign _zz_execute_BranchPlugin_branch_src2_4 = decode_to_execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_5 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31] };
assign _zz_execute_BranchPlugin_branch_src2_6 = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], execute_BranchPlugin_branch_src2[19:11], decode_to_execute_INSTRUCTION[30:25], execute_BranchPlugin_branch_src2[4:0] };
assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign _zz_execute_SrcPlugin_addSub_2 = decode_to_execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_5 = 32'd1;
assign _zz_execute_SrcPlugin_addSub_6 = 32'd0;
assign _zz_execute_to_memory_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign _zz_execute_to_memory_ENV_CTRL_1 = decode_to_execute_ENV_CTRL;
assign _zz_lastStageRegFileWrite_payload_address = memory_to_writeBack_INSTRUCTION[29:0];
assign _zz_lastStageRegFileWrite_valid = memory_to_writeBack_REGFILE_WRITE_VALID;
assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL_1 = execute_to_memory_ENV_CTRL;
assign _zz_writeBack_DBusSimplePlugin_rspFormated_1[31:8] = { _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated, _zz_writeBack_DBusSimplePlugin_rspFormated };
assign { _zz_writeBack_DBusSimplePlugin_rspFormated_3[31:16], _zz_writeBack_DBusSimplePlugin_rspFormated_3[7:0] } = { _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_2, _zz_writeBack_DBusSimplePlugin_rspFormated_1[7:0] };
assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign dBus_cmd_payload_address = execute_SrcPlugin_addSub;
assign dBus_cmd_payload_data[7:0] = decode_to_execute_RS2[7:0];
assign dBus_cmd_payload_size = decode_to_execute_INSTRUCTION[13:12];
assign dBus_cmd_payload_wr = decode_to_execute_MEMORY_STORE;
assign debug_bus_rsp_data[31:5] = DebugPlugin_busReadDataReg[31:5];
assign debug_resetOut = DebugPlugin_resetIt_regNext;
assign decode_ALU_BITWISE_CTRL = { _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12], _zz__zz_decode_BRANCH_CTRL_2_17 };
assign decode_ALU_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_21, _zz__zz_decode_BRANCH_CTRL_2_26 };
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL;
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz__zz_decode_BRANCH_CTRL_2_46;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz__zz_decode_BRANCH_CTRL_2_16[9];
assign decode_ENV_CTRL = _zz__zz_decode_BRANCH_CTRL_2_28;
assign decode_INSTRUCTION = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst;
assign decode_INSTRUCTION_ANTICIPATED[31:25] = IBusSimplePlugin_iBusRsp_output_payload_rsp_inst[31:25];
assign decode_MEMORY_ENABLE = _zz__zz_decode_BRANCH_CTRL_2_71;
assign decode_MEMORY_STORE = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5];
assign decode_PC = { _zz_IBusSimplePlugin_injector_decodeInput_payload_pc[31:2], 2'h0 };
assign decode_RS1 = _zz_RegFilePlugin_regFile_port0;
assign decode_RS1_USE = _zz__zz_decode_BRANCH_CTRL_2_65;
assign decode_RS2 = _zz_RegFilePlugin_regFile_port1;
assign decode_RS2_USE = _zz__zz_decode_BRANCH_CTRL_2_32;
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19:15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24:20];
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;
assign decode_SHIFT_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_4, _zz_decode_BRANCH_CTRL_2[21] };
assign decode_SRC1 = _zz_decode_SRC1_1;
assign decode_SRC1_CTRL = { _zz__zz_decode_BRANCH_CTRL_2_77, _zz__zz_decode_BRANCH_CTRL_2_80 };
assign decode_SRC2 = _zz_decode_SRC2_6;
assign decode_SRC2_CTRL[0] = _zz__zz_decode_BRANCH_CTRL_2_63;
assign decode_arbitration_flushIt = 1'h0;
assign decode_arbitration_flushNext = 1'h0;
assign decode_to_execute_PC[1:0] = 2'h0;
assign execute_ALIGNEMENT_FAULT = 1'h0;
assign execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign execute_BRANCH_CALC = { execute_BranchPlugin_branchAdder[31:1], 1'h0 };
assign execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1;
assign { execute_BranchPlugin_branch_src2[31:20], execute_BranchPlugin_branch_src2[10:5] } = { decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31], decode_to_execute_INSTRUCTION[31:25] };
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_CsrPlugin_csrAddress = decode_to_execute_INSTRUCTION[31:20];
assign { execute_CsrPlugin_readToWriteData[31:12], execute_CsrPlugin_readToWriteData[10:8], execute_CsrPlugin_readToWriteData[6:4], execute_CsrPlugin_readToWriteData[2:0] } = { _zz_CsrPlugin_csrMapping_readDataInit_3[31], 18'h00000, _zz_CsrPlugin_csrMapping_readDataInit[12], 6'h00, _zz_CsrPlugin_csrMapping_readDataInit_3[2:1], _zz_CsrPlugin_csrMapping_readDataInit_3[1] };
assign execute_DBusSimplePlugin_skipCmd = 1'h0;
assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK;
assign execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign execute_MEMORY_ADDRESS_LOW = execute_SrcPlugin_addSub[1:0];
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE;
assign execute_PC = { decode_to_execute_PC[31:2], 2'h0 };
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign execute_SRC1 = decode_to_execute_SRC1;
assign execute_SRC2 = decode_to_execute_SRC2;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign execute_SrcPlugin_less = execute_SRC_LESS;
assign execute_arbitration_flushNext = execute_arbitration_flushIt;
assign execute_to_memory_BRANCH_CALC[0] = 1'h0;
assign iBus_cmd_payload_pc = { IBusSimplePlugin_fetchPc_pcReg[31:2], 2'h0 };
assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid;
assign iBus_rsp_toStream_payload_error = iBus_rsp_payload_error;
assign iBus_rsp_toStream_payload_inst = iBus_rsp_payload_inst;
assign iBus_rsp_toStream_ready = IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready;
assign iBus_rsp_toStream_valid = iBus_rsp_valid;
assign lastStageInstruction[29:0] = memory_to_writeBack_INSTRUCTION[29:0];
assign lastStageIsFiring = writeBack_arbitration_isValid;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign memory_BRANCH_CALC = { execute_to_memory_BRANCH_CALC[31:1], 1'h0 };
assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO;
assign memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign memory_INSTRUCTION[29:0] = execute_to_memory_INSTRUCTION;
assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign memory_MEMORY_READ_DATA = dBus_rsp_data;
assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_arbitration_flushIt = 1'h0;
assign memory_arbitration_haltByOther = 1'h0;
assign memory_arbitration_haltItself = memory_arbitration_isStuck;
assign memory_arbitration_isFlushed = CsrPlugin_jumpInterface_valid;
assign memory_arbitration_isStuckByOthers = 1'h0;
assign memory_to_writeBack_INSTRUCTION[31:30] = lastStageInstruction[31:30];
assign switch_CsrPlugin_l1068 = memory_to_writeBack_INSTRUCTION[29:28];
assign switch_DebugPlugin_l267 = debug_bus_cmd_payload_address[7:2];
assign switch_Misc_l211 = memory_to_writeBack_INSTRUCTION[13:12];
assign switch_Misc_l211_1 = decode_to_execute_INSTRUCTION[13];
assign switch_Misc_l211_2 = decode_to_execute_INSTRUCTION[14:12];
assign when_CsrPlugin_l1019 = CsrPlugin_interruptJump;
assign when_CsrPlugin_l1180 = when_CsrPlugin_l1176;
assign when_CsrPlugin_l946 = CsrPlugin_mstatus_MIE;
assign when_CsrPlugin_l952 = _zz_when_CsrPlugin_l952;
assign when_CsrPlugin_l952_1 = _zz_when_CsrPlugin_l952_1;
assign when_CsrPlugin_l952_2 = _zz_when_CsrPlugin_l952_2;
assign when_CsrPlugin_l980_2 = 1'h1;
assign when_DebugPlugin_l271 = debug_bus_cmd_payload_data[16];
assign when_DebugPlugin_l271_1 = debug_bus_cmd_payload_data[24];
assign when_DebugPlugin_l272 = debug_bus_cmd_payload_data[17];
assign when_DebugPlugin_l272_1 = debug_bus_cmd_payload_data[25];
assign when_DebugPlugin_l273 = debug_bus_cmd_payload_data[25];
assign when_DebugPlugin_l274 = debug_bus_cmd_payload_data[25];
assign when_DebugPlugin_l275 = debug_bus_cmd_payload_data[18];
assign when_DebugPlugin_l275_1 = debug_bus_cmd_payload_data[26];
assign when_Fetcher_l329 = IBusSimplePlugin_fetchPc_output_ready;
assign when_Fetcher_l329_1 = IBusSimplePlugin_iBusRsp_stages_1_output_ready;
assign when_Fetcher_l329_5 = 1'h1;
assign when_HazardSimplePlugin_l57 = HazardSimplePlugin_writeBackWrites_valid;
assign when_HazardSimplePlugin_l58 = 1'h1;
assign when_HazardSimplePlugin_l58_1 = 1'h1;
assign when_HazardSimplePlugin_l58_2 = 1'h1;
assign when_Pipeline_l124_14 = 1'h1;
assign when_Pipeline_l124_17 = 1'h1;
assign when_Pipeline_l124_2 = 1'h1;
assign when_Pipeline_l124_26 = 1'h1;
assign when_Pipeline_l124_39 = 1'h1;
assign when_Pipeline_l124_41 = 1'h1;
assign when_Pipeline_l124_44 = 1'h1;
assign when_Pipeline_l124_5 = 1'h1;
assign when_Pipeline_l124_8 = 1'h1;
assign when_Pipeline_l151_2 = 1'h1;
assign writeBack_DBusSimplePlugin_rspFormated[7:0] = _zz_writeBack_DBusSimplePlugin_rspFormated_1[7:0];
assign writeBack_DBusSimplePlugin_rspShifted = { memory_to_writeBack_MEMORY_READ_DATA[31:16], _zz_writeBack_DBusSimplePlugin_rspFormated_3[15:8], _zz_writeBack_DBusSimplePlugin_rspFormated_1[7:0] };
assign writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign writeBack_INSTRUCTION = { lastStageInstruction[31:30], memory_to_writeBack_INSTRUCTION[29:0] };
assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW;
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
assign writeBack_arbitration_flushIt = 1'h0;
assign writeBack_arbitration_flushNext = CsrPlugin_jumpInterface_valid;
assign writeBack_arbitration_haltByOther = 1'h0;
assign writeBack_arbitration_haltItself = 1'h0;
assign writeBack_arbitration_isFiring = writeBack_arbitration_isValid;
assign writeBack_arbitration_isFlushed = 1'h0;
assign writeBack_arbitration_isMoving = 1'h1;
assign writeBack_arbitration_isStuck = 1'h0;
assign writeBack_arbitration_isStuckByOthers = 1'h0;
assign writeBack_arbitration_removeIt = 1'h0;
endmodule
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