colin 1f222dd1e3 Split soc and verilator to two part system verilog.		2022-02-14 12:32:21 +00:00
.vscode	Set DCCM and ICCM size to 32KB	2022-02-11 12:17:21 +00:00
Cores-SweRV	Split soc and verilator to two part system verilog.	2022-02-14 12:32:21 +00:00
fpga	Add ram test and verilator in fpga DEMO.	2022-02-09 12:47:35 +00:00
jtag	add jtag to ESP32	2022-02-02 03:40:41 +00:00