133 lines
4.5 KiB
Systemverilog
133 lines
4.5 KiB
Systemverilog
//********************************************************************************
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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module mem
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import swerv_types::*;
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(
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input logic clk,
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input logic rst_l,
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input logic lsu_freeze_dc3,
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input logic dccm_clk_override,
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input logic icm_clk_override,
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input logic dec_tlu_core_ecc_disable,
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//DCCM ports
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input logic dccm_wren,
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input logic dccm_rden,
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input logic [`RV_DCCM_BITS-1:0] dccm_wr_addr,
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input logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_lo,
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input logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_hi,
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input logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_wr_data,
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output logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
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output logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
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`ifdef RV_ICCM_ENABLE
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//ICCM ports
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input logic [`RV_ICCM_BITS-1:2] iccm_rw_addr,
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input logic iccm_wren,
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input logic iccm_rden,
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input logic [2:0] iccm_wr_size,
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input logic [77:0] iccm_wr_data,
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output logic [155:0] iccm_rd_data,
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`endif
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// Icache and Itag Ports
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`ifdef RV_ICACHE_ENABLE //temp
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input logic [31:3] ic_rw_addr,
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input logic [3:0] ic_tag_valid,
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input logic [3:0] ic_wr_en,
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input logic ic_rd_en,
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input logic [127:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
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input logic ic_sel_premux_data, // Premux data sel
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`ifdef RV_ICACHE_ECC
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input logic [83:0] ic_wr_data, // Data to fill to the Icache. With ECC
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input logic [41:0] ic_debug_wr_data, // Debug wr cache.
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`else
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input logic [67:0] ic_wr_data, // Data to fill to the Icache. With Parity
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input logic [33:0] ic_debug_wr_data, // Debug wr cache.
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`endif
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input logic [15:2] ic_debug_addr, // Read/Write addresss to the Icache.
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input logic ic_debug_rd_en, // Icache debug rd
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input logic ic_debug_wr_en, // Icache debug wr
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input logic ic_debug_tag_array, // Debug tag array
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input logic [3:0] ic_debug_way, // Debug way. Rd or Wr.
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`endif
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`ifdef RV_ICACHE_ECC
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output logic [167:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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output logic [24:0] ictag_debug_rd_data,// Debug icache tag.
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`else
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output logic [135:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With Parity
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output logic [20:0] ictag_debug_rd_data,// Debug icache tag.
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`endif
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output logic [3:0] ic_rd_hit,
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output logic ic_tag_perr, // Icache Tag parity error
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input logic scan_mode
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);
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`include "global.h"
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`ifdef RV_DCCM_ENABLE
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localparam DCCM_ENABLE = 1'b1;
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`else
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localparam DCCM_ENABLE = 1'b0;
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`endif
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// DCCM Instantiation
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if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
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lsu_dccm_mem dccm (
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.clk_override(dccm_clk_override),
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.*
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);
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end else begin: Gen_dccm_disable
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assign dccm_rd_data_lo = '0;
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assign dccm_rd_data_hi = '0;
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end
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`ifdef RV_ICACHE_ENABLE
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ifu_ic_mem icm (
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.clk_override(icm_clk_override),
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.*
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);
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`else
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assign ic_rd_hit[3:0] = '0;
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assign ic_tag_perr = '0 ;
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assign ic_rd_data = '0 ;
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assign ictag_debug_rd_data = '0 ;
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`endif
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`ifdef RV_ICCM_ENABLE
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ifu_iccm_mem iccm (.*,
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.clk_override(icm_clk_override),
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.iccm_rw_addr(iccm_rw_addr[`RV_ICCM_BITS-1:2]),
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.iccm_rd_data(iccm_rd_data[155:0])
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);
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`endif
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endmodule
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