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colin 25a557365b Enable VexRiscv murax jtag simulator by verilator. 2022-02-26 14:34:25 +00:00
Cores-SweRV Add fpga demo in Cores. 2022-02-21 07:52:52 +00:00
VexRiscv Enable VexRiscv murax jtag simulator by verilator. 2022-02-26 14:34:25 +00:00
fpga Add clean before fpga ram make all 2022-02-17 06:21:42 +00:00
jtag add jtag to ESP32 2022-02-02 03:40:41 +00:00
opene906 Refine opene906 gdb sample. 2022-02-25 12:24:03 +00:00
xilinx Add xilinx readme. 2022-02-21 07:53:02 +00:00
.gitignore Enable VexRiscv murax jtag simulator by verilator. 2022-02-26 14:34:25 +00:00
Readme.md Enable VexRiscv murax jtag simulator by verilator. 2022-02-26 14:34:25 +00:00

Readme.md

Weekend group

不要小看自己

我们不卷，只是爱好

自由的参与方式

自由发挥，无限创作空间

理性的分歧决议方法