History

colin 27fade0b6d Add EL2 cores implement by Chisel in quaser.		2022-03-06 04:22:17 +00:00
..
fpga	Add fpga demo in Cores.	2022-02-21 07:52:52 +00:00
helloworld	Switch mem bus from ahb to axi.	2022-02-17 11:35:01 +00:00
jtag	Update riscv gcc version and usage.	2022-03-06 04:21:41 +00:00
jtag_quasar	Add EL2 cores implement by Chisel in quaser.	2022-03-06 04:22:17 +00:00
Readme.md	Update riscv gcc version and usage.	2022-03-06 04:21:41 +00:00

Readme.md

Demo

helloworld

This a demo for llvm build and sim with verilator.

jtag

This is a demo of jtag simulation by openocd running on verilator.

install verilator

sudo apt install verilator

install openocd

git clone https://github.com/riscv/riscv-openocd.git
cd riscv-openocd
./bootstrap
./configure --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --enable-ftdi --enable-jlink
make
sudo make install

may be install sv2v

https://github.com/zachjs/sv2v

install ninja

sudo apt-get install -y ninja-build

build and install riscv tools

Opetion1 :https://github.com/riscv-collab/riscv-gnu-toolchain.git

sudo make clean
./configure --prefix=/opt/riscv # build 64bit
sudo make -j12
sudo make clean
./configure --prefix=/opt/riscv --with-arch=rv32gc --with-abi=ilp32d
sudo make -j12

Opetion2 :

sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev libusb-1.0-0-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev device-tree-compiler pkg-config libexpat-dev libfl-dev
git clone https://github.com/chipsalliance/rocket-tools.git
git submodule update --init --recursive
# riscv-isa-sim and openocd may be checkout to main branch to avoid compile error
sudo su
export RISCV=/opt/riscv
export MAKEFLAGS="-j12"
./build-rv32ima.sh