323 lines
8.7 KiB
Plaintext
323 lines
8.7 KiB
Plaintext
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.definition
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add = [0000000..........000.....0110011]
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addi = [.................000.....0010011]
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sub = [0100000..........000.....0110011]
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and = [0000000..........111.....0110011]
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andi = [.................111.....0010011]
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or = [0000000..........110.....0110011]
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ori = [.................110.....0010011]
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xor = [0000000..........100.....0110011]
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xori = [.................100.....0010011]
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sll = [0000000..........001.....0110011]
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slli = [0000000..........001.....0010011]
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sra = [0100000..........101.....0110011]
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srai = [0100000..........101.....0010011]
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srl = [0000000..........101.....0110011]
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srli = [0000000..........101.....0010011]
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lui = [.........................0110111]
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auipc= [.........................0010111]
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slt = [0000000..........010.....0110011]
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sltu = [0000000..........011.....0110011]
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slti = [.................010.....0010011]
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sltiu= [.................011.....0010011]
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beq = [.................000.....1100011]
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bne = [.................001.....1100011]
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bge = [.................101.....1100011]
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blt = [.................100.....1100011]
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bgeu = [.................111.....1100011]
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bltu = [.................110.....1100011]
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jal = [.........................1101111]
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jalr = [.................000.....1100111]
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lb = [.................000.....0000011]
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lh = [.................001.....0000011]
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lw = [.................010.....0000011]
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sb = [.................000.....0100011]
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sh = [.................001.....0100011]
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sw = [.................010.....0100011]
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lbu = [.................100.....0000011]
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lhu = [.................101.....0000011]
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fence = [0000........00000000000000001111]
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fence.i = [00000000000000000001000000001111]
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ebreak = [00000000000100000000000001110011]
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ecall = [00000000000000000000000001110011]
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mret = [00110000001000000000000001110011]
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wfi = [00010000010100000000000001110011]
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csrrc_ro = [............00000011.....1110011]
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csrrc_rw0 = [............1....011.....1110011]
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csrrc_rw1 = [.............1...011.....1110011]
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csrrc_rw2 = [..............1..011.....1110011]
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csrrc_rw3 = [...............1.011.....1110011]
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csrrc_rw4 = [................1011.....1110011]
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csrrci_ro = [............00000111.....1110011]
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csrrci_rw0 = [............1....111.....1110011]
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csrrci_rw1 = [.............1...111.....1110011]
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csrrci_rw2 = [..............1..111.....1110011]
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csrrci_rw3 = [...............1.111.....1110011]
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csrrci_rw4 = [................1111.....1110011]
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csrrs_ro = [............00000010.....1110011]
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csrrs_rw0 = [............1....010.....1110011]
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csrrs_rw1 = [.............1...010.....1110011]
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csrrs_rw2 = [..............1..010.....1110011]
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csrrs_rw3 = [...............1.010.....1110011]
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csrrs_rw4 = [................1010.....1110011]
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csrrsi_ro = [............00000110.....1110011]
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csrrsi_rw0 = [............1....110.....1110011]
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csrrsi_rw1 = [.............1...110.....1110011]
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csrrsi_rw2 = [..............1..110.....1110011]
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csrrsi_rw3 = [...............1.110.....1110011]
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csrrsi_rw4 = [................1110.....1110011]
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csrw = [.................001000001110011]
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csrrw0 = [.................001....11110011]
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csrrw1 = [.................001...1.1110011]
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csrrw2 = [.................001..1..1110011]
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csrrw3 = [.................001.1...1110011]
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csrrw4 = [.................0011....1110011]
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csrwi = [.................101000001110011]
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csrrwi0 = [.................101....11110011]
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csrrwi1 = [.................101...1.1110011]
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csrrwi2 = [.................101..1..1110011]
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csrrwi3 = [.................101.1...1110011]
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csrrwi4 = [.................1011....1110011]
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mul = [0000001..........000.....0110011]
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mulh = [0000001..........001.....0110011]
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mulhsu = [0000001..........010.....0110011]
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mulhu = [0000001..........011.....0110011]
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div = [0000001..........100.....0110011]
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divu = [0000001..........101.....0110011]
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rem = [0000001..........110.....0110011]
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remu = [0000001..........111.....0110011]
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.input
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rv32i = {
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i[31]
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i[30]
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i[29]
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i[28]
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i[27]
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i[26]
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i[25]
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i[24]
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i[23]
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i[22]
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i[21]
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i[20]
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i[19]
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i[18]
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i[17]
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i[16]
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i[15]
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i[14]
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i[13]
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i[12]
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i[11]
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i[10]
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i[9]
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i[8]
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i[7]
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i[6]
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i[5]
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i[4]
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i[3]
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i[2]
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i[1]
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i[0]
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}
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.output
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rv32i = {
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alu
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rs1
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rs2
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imm12
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rd
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shimm5
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imm20
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pc
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load
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store
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lsu
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add
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sub
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land
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lor
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lxor
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sll
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sra
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srl
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slt
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unsign
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condbr
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beq
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bne
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bge
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blt
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jal
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by
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half
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word
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csr_read
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csr_clr
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csr_set
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csr_write
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csr_imm
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presync
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postsync
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ebreak
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ecall
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mret
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mul
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rs1_sign
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rs2_sign
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low
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div
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rem
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fence
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fence_i
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pm_alu
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}
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.decode
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rv32i[mul] = { mul rs1 rs2 rd low }
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rv32i[mulh] = { mul rs1 rs2 rd rs1_sign rs2_sign }
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rv32i[mulhu] = { mul rs1 rs2 rd }
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rv32i[mulhsu] = { mul rs1 rs2 rd rs1_sign }
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rv32i[div] = { div rs1 rs2 rd presync postsync}
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rv32i[divu] = { div rs1 rs2 rd unsign presync postsync}
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rv32i[rem] = { div rs1 rs2 rd presync postsync rem}
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rv32i[remu] = { div rs1 rs2 rd unsign presync postsync rem}
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rv32i[add] = { alu rs1 rs2 rd add pm_alu }
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rv32i[addi] = { alu rs1 imm12 rd add pm_alu }
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rv32i[sub] = { alu rs1 rs2 rd sub pm_alu }
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rv32i[and] = { alu rs1 rs2 rd land pm_alu }
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rv32i[andi] = { alu rs1 imm12 rd land pm_alu }
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rv32i[or] = { alu rs1 rs2 rd lor pm_alu }
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rv32i[ori] = { alu rs1 imm12 rd lor pm_alu }
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rv32i[xor] = { alu rs1 rs2 rd lxor pm_alu }
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rv32i[xori] = { alu rs1 imm12 rd lxor pm_alu }
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rv32i[sll] = { alu rs1 rs2 rd sll pm_alu }
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rv32i[slli] = { alu rs1 shimm5 rd sll pm_alu }
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rv32i[sra] = { alu rs1 rs2 rd sra pm_alu }
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rv32i[srai] = { alu rs1 shimm5 rd sra pm_alu }
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rv32i[srl] = { alu rs1 rs2 rd srl pm_alu }
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rv32i[srli] = { alu rs1 shimm5 rd srl pm_alu }
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rv32i[lui] = { alu imm20 rd lor pm_alu }
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rv32i[auipc] = { alu imm20 pc rd add pm_alu }
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rv32i[slt] = { alu rs1 rs2 rd sub slt pm_alu }
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rv32i[sltu] = { alu rs1 rs2 rd sub slt unsign pm_alu }
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rv32i[slti] = { alu rs1 imm12 rd sub slt pm_alu }
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rv32i[sltiu] = { alu rs1 imm12 rd sub slt unsign pm_alu }
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rv32i[beq] = { alu rs1 rs2 sub condbr beq }
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rv32i[bne] = { alu rs1 rs2 sub condbr bne }
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rv32i[bge] = { alu rs1 rs2 sub condbr bge }
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rv32i[blt] = { alu rs1 rs2 sub condbr blt }
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rv32i[bgeu] = { alu rs1 rs2 sub condbr bge unsign }
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rv32i[bltu] = { alu rs1 rs2 sub condbr blt unsign }
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rv32i[jal] = { alu imm20 rd pc jal }
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rv32i[jalr] = { alu rs1 rd imm12 jal }
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rv32i[lb] = { lsu load rs1 rd by }
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rv32i[lh] = { lsu load rs1 rd half }
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rv32i[lw] = { lsu load rs1 rd word }
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rv32i[lbu] = { lsu load rs1 rd by unsign }
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rv32i[lhu] = { lsu load rs1 rd half unsign }
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rv32i[sb] = { lsu store rs1 rs2 by }
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rv32i[sh] = { lsu store rs1 rs2 half }
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rv32i[sw] = { lsu store rs1 rs2 word }
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rv32i[fence] = { alu lor fence presync}
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# fence.i has fence effect in addtion to flush I$ and redirect
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rv32i[fence.i] = { alu lor fence fence_i presync postsync}
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# nops for now
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rv32i[ebreak] = { alu rs1 imm12 rd lor ebreak postsync}
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rv32i[ecall] = { alu rs1 imm12 rd lor ecall postsync}
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rv32i[mret] = { alu rs1 imm12 rd lor mret postsync}
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rv32i[wfi] = { alu rs1 imm12 rd lor pm_alu }
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# csr means read
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# csr_read - put csr on rs2 and rs1 0's
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rv32i[csrrc_ro] = { alu rd csr_read lor }
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# put csr on rs2 and make rs1 0's into alu. Save rs1 for csr_clr later
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rv32i[csrrc_rw{0-4}] = { alu rd csr_read rs1 csr_clr lor presync postsync }
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rv32i[csrrci_ro] = { alu rd csr_read lor }
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rv32i[csrrci_rw{0-4}] = { alu rd csr_read rs1 csr_clr csr_imm lor presync postsync }
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rv32i[csrrs_ro] = { alu rd csr_read lor }
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rv32i[csrrs_rw{0-4}] = { alu rd csr_read rs1 csr_set lor presync postsync }
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rv32i[csrrsi_ro] = { alu rd csr_read lor }
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rv32i[csrrsi_rw{0-4}] = { alu rd csr_read rs1 csr_set csr_imm lor presync postsync }
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rv32i[csrrw{0-4}] = { alu rd csr_read rs1 csr_write lor presync postsync }
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rv32i[csrrwi{0-4}] = { alu rd csr_read rs1 csr_write csr_imm lor presync postsync }
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# optimize csr write only - pipelined
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rv32i[csrw] = { alu rd rs1 csr_write }
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rv32i[csrwi] = { alu rd csr_write csr_imm }
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.end
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