52 lines
923 B
Verilog
52 lines
923 B
Verilog
module rst_gen (
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input clk_i,
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input rst_i,
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output rst_o
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);
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/* try to generate a reset */
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reg [2:0] rst_cpt;
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always @(posedge clk_i) begin
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if (rst_i)
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rst_cpt = 3'b0;
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else begin
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if (rst_cpt == 3'b100)
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rst_cpt = rst_cpt;
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else
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rst_cpt = rst_cpt + 3'b1;
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end
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end
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assign rst_o = !rst_cpt[2];
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endmodule
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module blink (
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input clk_i,
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output reg led_o
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);
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localparam MAX = 2_500_000_0;
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localparam WIDTH = $clog2(MAX);
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wire rst_s;
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wire clk_s;
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assign clk_s = clk_i;
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//pll_12_16 pll_inst (.clki(clk_i), .clko(clk_s), .rst(rst_s));
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rst_gen rst_inst (.clk_i(clk_s), .rst_i(1'b0), .rst_o(rst_s));
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reg [WIDTH-1:0] cpt_s;
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wire [WIDTH-1:0] cpt_next_s = cpt_s + 1'b1;
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wire end_s = cpt_s == MAX-1;
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always @(posedge clk_s) begin
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cpt_s <= (rst_s || end_s) ? {WIDTH{1'b0}} : cpt_next_s;
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if (rst_s)
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led_o <= 1'b0;
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else if (end_s)
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led_o <= ~led_o;
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end
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endmodule
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