111 lines
2.9 KiB
Systemverilog
111 lines
2.9 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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module axi_slv #(
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TAGW = 1
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) (
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input aclk,
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input rst_l,
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input arvalid,
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output reg arready,
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input [ 31:0] araddr,
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input [TAGW-1:0] arid,
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input [ 7:0] arlen,
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input [ 1:0] arburst,
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input [ 2:0] arsize,
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output reg rvalid,
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input rready,
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output reg [ 63:0] rdata,
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output reg [ 1:0] rresp,
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output reg [TAGW-1:0] rid,
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output rlast,
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input awvalid,
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output awready,
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input [ 31:0] awaddr,
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input [TAGW-1:0] awid,
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input [ 7:0] awlen,
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input [ 1:0] awburst,
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input [ 2:0] awsize,
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input [63:0] wdata,
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input [ 7:0] wstrb,
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input wvalid,
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output wready,
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output reg bvalid,
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input bready,
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output reg [ 1:0] bresp,
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output reg [TAGW-1:0] bid
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);
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parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k
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bit [7:0] mem[(1<<MEM_DEPTH)-1:0];
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bit [63:0] memdata;
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wire [MEM_DEPTH-1:0] saraddr = araddr[MEM_DEPTH-1:0];
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wire [MEM_DEPTH-1:0] sawaddr = awaddr[MEM_DEPTH-1:0];
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always @(posedge aclk or negedge rst_l) begin
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if (!rst_l) begin
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rvalid <= 0;
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bvalid <= 0;
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end else begin
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bid <= awid;
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rid <= arid;
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rvalid <= arvalid;
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bvalid <= awvalid;
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rdata <= memdata;
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end
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end
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always @(negedge aclk) begin
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if (arvalid)
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memdata <= {
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mem[saraddr+7],
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mem[saraddr+6],
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mem[saraddr+5],
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mem[saraddr+4],
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mem[saraddr+3],
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mem[saraddr+2],
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mem[saraddr+1],
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mem[saraddr]
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};
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if (awvalid) begin
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if (wstrb[7]) mem[sawaddr+7] = wdata[63:56];
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if (wstrb[6]) mem[sawaddr+6] = wdata[55:48];
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if (wstrb[5]) mem[sawaddr+5] = wdata[47:40];
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if (wstrb[4]) mem[sawaddr+4] = wdata[39:32];
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if (wstrb[3]) mem[sawaddr+3] = wdata[31:24];
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if (wstrb[2]) mem[sawaddr+2] = wdata[23:16];
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if (wstrb[1]) mem[sawaddr+1] = wdata[15:08];
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if (wstrb[0]) mem[sawaddr+0] = wdata[07:00];
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end
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end
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assign arready = 1'b1;
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assign awready = 1'b1;
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assign wready = 1'b1;
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assign rresp = 2'b0;
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assign bresp = 2'b0;
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assign rlast = 1'b1;
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endmodule
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