420 lines
20 KiB
Systemverilog
420 lines
20 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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//
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// Owner:
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// Function: Store Buffer
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// Comments: Dual writes and single drain
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//
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//
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// DC1 -> DC2 -> DC3 -> DC4 (Commit)
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//
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// //********************************************************************************
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module el2_lsu_stbuf
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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) (
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input logic clk, // core clock
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input logic rst_l, // reset
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input logic lsu_stbuf_c1_clk, // stbuf clock
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input logic lsu_free_c2_clk, // free clk
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// Store Buffer input
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input logic store_stbuf_reqvld_r, // core instruction goes to stbuf
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input logic lsu_commit_r, // lsu commits
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input logic dec_lsu_valid_raw_d, // Speculative decode valid
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input logic [pt.DCCM_DATA_WIDTH-1:0] store_data_hi_r, // merged data from the dccm for stores. This is used for fwding
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input logic [pt.DCCM_DATA_WIDTH-1:0] store_data_lo_r, // merged data from the dccm for stores. This is used for fwding
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input logic [pt.DCCM_DATA_WIDTH-1:0] store_datafn_hi_r, // merged data from the dccm for stores
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input logic [pt.DCCM_DATA_WIDTH-1:0] store_datafn_lo_r, // merged data from the dccm for stores
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// Store Buffer output
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output logic stbuf_reqvld_any, // stbuf is draining
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output logic stbuf_reqvld_flushed_any, // Top entry is flushed
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output logic [ pt.LSU_SB_BITS-1:0] stbuf_addr_any, // address
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output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any, // stbuf data
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input logic lsu_stbuf_commit_any, // pop the stbuf as it commite
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output logic lsu_stbuf_full_any, // stbuf is full
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output logic lsu_stbuf_empty_any, // stbuf is empty
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output logic ldst_stbuf_reqvld_r, // needed for clocking
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input logic [pt.LSU_SB_BITS-1:0] lsu_addr_d, // lsu address D-stage
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input logic [ 31:0] lsu_addr_m, // lsu address M-stage
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input logic [ 31:0] lsu_addr_r, // lsu address R-stage
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input logic [pt.LSU_SB_BITS-1:0] end_addr_d, // lsu end address D-stage - needed to check unaligned
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input logic [31:0] end_addr_m, // lsu end address M-stage - needed to check unaligned
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input logic [31:0] end_addr_r, // lsu end address R-stage - needed to check unaligned
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input logic ldst_dual_d,
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ldst_dual_m,
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ldst_dual_r,
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input logic addr_in_dccm_m, // address is in dccm
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input logic addr_in_dccm_r, // address is in dccm
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// Forwarding signals
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input logic lsu_cmpen_m, // needed for forwarding stbuf - load
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input el2_lsu_pkt_t lsu_pkt_m, // LSU packet M-stage
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input el2_lsu_pkt_t lsu_pkt_r, // LSU packet R-stage
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output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_m, // stbuf data
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output logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_m, // stbuf data
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output logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_m, // stbuf data
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output logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_m, // stbuf data
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input logic scan_mode // Scan mode
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);
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localparam DEPTH = pt.LSU_STBUF_DEPTH;
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localparam DATA_WIDTH = pt.DCCM_DATA_WIDTH;
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localparam BYTE_WIDTH = pt.DCCM_BYTE_WIDTH;
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localparam DEPTH_LOG2 = $clog2(DEPTH);
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// These are the fields in the store queue
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logic [ DEPTH-1:0] stbuf_vld;
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logic [ DEPTH-1:0] stbuf_dma_kill;
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logic [ DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addr;
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logic [ DEPTH-1:0][ BYTE_WIDTH-1:0] stbuf_byteen;
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logic [ DEPTH-1:0][ DATA_WIDTH-1:0] stbuf_data;
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logic [ DEPTH-1:0] sel_lo;
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logic [ DEPTH-1:0] stbuf_wr_en;
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logic [ DEPTH-1:0] stbuf_dma_kill_en;
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logic [ DEPTH-1:0] stbuf_reset;
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logic [ DEPTH-1:0][pt.LSU_SB_BITS-1:0] stbuf_addrin;
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logic [ DEPTH-1:0][ DATA_WIDTH-1:0] stbuf_datain;
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logic [ DEPTH-1:0][ BYTE_WIDTH-1:0] stbuf_byteenin;
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logic [ 7:0] store_byteen_ext_r;
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logic [BYTE_WIDTH-1:0] store_byteen_hi_r;
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logic [BYTE_WIDTH-1:0] store_byteen_lo_r;
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logic WrPtrEn, RdPtrEn;
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logic [DEPTH_LOG2-1:0] WrPtr, RdPtr;
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logic [DEPTH_LOG2-1:0] NxtWrPtr, NxtRdPtr;
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logic [DEPTH_LOG2-1:0] WrPtrPlus1, WrPtrPlus2, RdPtrPlus1;
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logic dual_stbuf_write_r;
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logic isdccmst_m, isdccmst_r;
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logic [3:0] stbuf_numvld_any, stbuf_specvld_any;
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logic [1:0] stbuf_specvld_m, stbuf_specvld_r;
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logic [pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m, cmpaddr_lo_m;
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// variables to detect matching from the store queue
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logic [DEPTH-1:0] stbuf_match_hi, stbuf_match_lo;
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logic [DEPTH-1:0][BYTE_WIDTH-1:0] stbuf_fwdbyteenvec_hi, stbuf_fwdbyteenvec_lo;
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logic [DATA_WIDTH-1:0] stbuf_fwddata_hi_pre_m, stbuf_fwddata_lo_pre_m;
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logic [BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_pre_m, stbuf_fwdbyteen_lo_pre_m;
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// logic to detect matching from the pipe - needed for store - load forwarding
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logic [BYTE_WIDTH-1:0]
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ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;
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logic ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;
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logic [BYTE_WIDTH-1:0] ld_byte_hit_lo, ld_byte_rhit_lo;
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logic [BYTE_WIDTH-1:0] ld_byte_hit_hi, ld_byte_rhit_hi;
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logic [BYTE_WIDTH-1:0] ldst_byteen_hi_r;
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logic [BYTE_WIDTH-1:0] ldst_byteen_lo_r;
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// byte_en flowing down
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logic [ 7:0] ldst_byteen_r;
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logic [ 7:0] ldst_byteen_ext_r;
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// fwd data through the pipe
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logic [ 31:0] ld_fwddata_rpipe_lo;
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logic [ 31:0] ld_fwddata_rpipe_hi;
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// coalescing signals
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logic [DEPTH-1:0] store_matchvec_lo_r, store_matchvec_hi_r;
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logic store_coalesce_lo_r, store_coalesce_hi_r;
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//----------------------------------------
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// Logic starts here
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//----------------------------------------
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// Create high/low byte enables
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assign store_byteen_ext_r[7:0] = ldst_byteen_r[7:0] << lsu_addr_r[1:0];
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assign store_byteen_hi_r[BYTE_WIDTH-1:0] = store_byteen_ext_r[7:4] & {4{lsu_pkt_r.store}};
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assign store_byteen_lo_r[BYTE_WIDTH-1:0] = store_byteen_ext_r[3:0] & {4{lsu_pkt_r.store}};
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assign RdPtrPlus1[DEPTH_LOG2-1:0] = RdPtr[DEPTH_LOG2-1:0] + 1'b1;
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assign WrPtrPlus1[DEPTH_LOG2-1:0] = WrPtr[DEPTH_LOG2-1:0] + 1'b1;
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assign WrPtrPlus2[DEPTH_LOG2-1:0] = WrPtr[DEPTH_LOG2-1:0] + 2'b10;
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// ecc error on both hi/lo
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assign dual_stbuf_write_r = ldst_dual_r & store_stbuf_reqvld_r;
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assign ldst_stbuf_reqvld_r = ((lsu_commit_r | lsu_pkt_r.dma) & store_stbuf_reqvld_r);
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// Store Buffer coalescing
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for (genvar i = 0; i < DEPTH; i++) begin : FindMatchEntry
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assign store_matchvec_lo_r[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(
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BYTE_WIDTH
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)] == lsu_addr_r[pt.LSU_SB_BITS-1:$clog2(
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BYTE_WIDTH
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)]) & stbuf_vld[i] & ~stbuf_dma_kill[i] & ~stbuf_reset[i];
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assign store_matchvec_hi_r[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(
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BYTE_WIDTH
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)] == end_addr_r[pt.LSU_SB_BITS-1:$clog2(
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BYTE_WIDTH
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)]) & stbuf_vld[i] & ~stbuf_dma_kill[i] & dual_stbuf_write_r & ~stbuf_reset[i];
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end : FindMatchEntry
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assign store_coalesce_lo_r = |store_matchvec_lo_r[DEPTH-1:0];
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assign store_coalesce_hi_r = |store_matchvec_hi_r[DEPTH-1:0];
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if (pt.DCCM_ENABLE == 1) begin : Gen_dccm_enable
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// Allocate new in this entry if :
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// 1. wrptr, single allocate, lo did not coalesce
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// 2. wrptr, double allocate, lo ^ hi coalesced
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// 3. wrptr + 1, double alloacte, niether lo or hi coalesced
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// Also update if there is a hi or a lo coalesce to this entry
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// Store Buffer instantiation
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for (genvar i = 0; i < DEPTH; i++) begin : GenStBuf
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assign stbuf_wr_en[i] = ldst_stbuf_reqvld_r & (
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( (i == WrPtr[DEPTH_LOG2-1:0]) & ~store_coalesce_lo_r) | // Allocate : new Lo
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( (i == WrPtr[DEPTH_LOG2-1:0]) & dual_stbuf_write_r & ~store_coalesce_hi_r) | // Allocate : only 1 new Write Either
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( (i == WrPtrPlus1[DEPTH_LOG2-1:0]) & dual_stbuf_write_r & ~(store_coalesce_lo_r | store_coalesce_hi_r)) | // Allocate2 : 2 new so Write Hi
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store_matchvec_lo_r[i] | store_matchvec_hi_r[i]); // Coalesced Write Lo or Hi
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assign stbuf_reset[i] = (lsu_stbuf_commit_any | stbuf_reqvld_flushed_any) & (i == RdPtr[DEPTH_LOG2-1:0]);
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// Mux select for start/end address
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assign sel_lo[i] = ((~ldst_dual_r | store_stbuf_reqvld_r) & (i == WrPtr[DEPTH_LOG2-1:0]) & ~store_coalesce_lo_r) | // lo allocated new entry
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store_matchvec_lo_r[i]; // lo coalesced in to this entry
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assign stbuf_addrin[i][pt.LSU_SB_BITS-1:0] = sel_lo[i] ? lsu_addr_r[pt.LSU_SB_BITS-1:0] : end_addr_r[pt.LSU_SB_BITS-1:0];
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assign stbuf_byteenin[i][BYTE_WIDTH-1:0] = sel_lo[i] ? (stbuf_byteen[i][BYTE_WIDTH-1:0] | store_byteen_lo_r[BYTE_WIDTH-1:0]) : (stbuf_byteen[i][BYTE_WIDTH-1:0] | store_byteen_hi_r[BYTE_WIDTH-1:0]);
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assign stbuf_datain[i][7:0] = sel_lo[i] ? ((~stbuf_byteen[i][0] | store_byteen_lo_r[0]) ? store_datafn_lo_r[7:0] : stbuf_data[i][7:0]) :
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((~stbuf_byteen[i][0] | store_byteen_hi_r[0]) ? store_datafn_hi_r[7:0] : stbuf_data[i][7:0]);
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assign stbuf_datain[i][15:8] = sel_lo[i] ? ((~stbuf_byteen[i][1] | store_byteen_lo_r[1]) ? store_datafn_lo_r[15:8] : stbuf_data[i][15:8]) :
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((~stbuf_byteen[i][1] | store_byteen_hi_r[1]) ? store_datafn_hi_r[15:8] : stbuf_data[i][15:8]);
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assign stbuf_datain[i][23:16] = sel_lo[i] ? ((~stbuf_byteen[i][2] | store_byteen_lo_r[2]) ? store_datafn_lo_r[23:16] : stbuf_data[i][23:16]) :
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((~stbuf_byteen[i][2] | store_byteen_hi_r[2]) ? store_datafn_hi_r[23:16] : stbuf_data[i][23:16]);
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assign stbuf_datain[i][31:24] = sel_lo[i] ? ((~stbuf_byteen[i][3] | store_byteen_lo_r[3]) ? store_datafn_lo_r[31:24] : stbuf_data[i][31:24]) :
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((~stbuf_byteen[i][3] | store_byteen_hi_r[3]) ? store_datafn_hi_r[31:24] : stbuf_data[i][31:24]);
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rvdffsc #(
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.WIDTH(1)
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) stbuf_vldff (
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.din(1'b1),
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.dout(stbuf_vld[i]),
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.en(stbuf_wr_en[i]),
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.clear(stbuf_reset[i]),
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.clk(lsu_free_c2_clk),
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.*
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);
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rvdffsc #(
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.WIDTH(1)
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) stbuf_killff (
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.din(1'b1),
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.dout(stbuf_dma_kill[i]),
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.en(stbuf_dma_kill_en[i]),
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.clear(stbuf_reset[i]),
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.clk(lsu_free_c2_clk),
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.*
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);
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rvdffe #(
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.WIDTH(pt.LSU_SB_BITS)
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) stbuf_addrff (
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.din (stbuf_addrin[i][pt.LSU_SB_BITS-1:0]),
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.dout(stbuf_addr[i][pt.LSU_SB_BITS-1:0]),
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.en (stbuf_wr_en[i]),
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.*
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);
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rvdffsc #(
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.WIDTH(BYTE_WIDTH)
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) stbuf_byteenff (
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.din(stbuf_byteenin[i][BYTE_WIDTH-1:0]),
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.dout(stbuf_byteen[i][BYTE_WIDTH-1:0]),
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.en(stbuf_wr_en[i]),
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.clear(stbuf_reset[i]),
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.clk(lsu_stbuf_c1_clk),
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.*
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);
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rvdffe #(
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.WIDTH(DATA_WIDTH)
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) stbuf_dataff (
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.din (stbuf_datain[i][DATA_WIDTH-1:0]),
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.dout(stbuf_data[i][DATA_WIDTH-1:0]),
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.en (stbuf_wr_en[i]),
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.*
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);
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end
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end else begin : Gen_dccm_disable
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assign stbuf_wr_en[DEPTH-1:0] = '0;
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assign stbuf_reset[DEPTH-1:0] = '0;
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assign stbuf_vld[DEPTH-1:0] = '0;
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assign stbuf_dma_kill[DEPTH-1:0] = '0;
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assign stbuf_addr[DEPTH-1:0] = '0;
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assign stbuf_byteen[DEPTH-1:0] = '0;
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assign stbuf_data[DEPTH-1:0] = '0;
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end
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// Store Buffer drain logic
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assign stbuf_reqvld_flushed_any = stbuf_vld[RdPtr] & stbuf_dma_kill[RdPtr];
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assign stbuf_reqvld_any = stbuf_vld[RdPtr] & ~stbuf_dma_kill[RdPtr] & ~(|stbuf_dma_kill_en[DEPTH-1:0]); // Don't drain if some kill bit is being set this cycle
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assign stbuf_addr_any[pt.LSU_SB_BITS-1:0] = stbuf_addr[RdPtr][pt.LSU_SB_BITS-1:0];
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assign stbuf_data_any[DATA_WIDTH-1:0] = stbuf_data[RdPtr][DATA_WIDTH-1:0];
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// Update the RdPtr/WrPtr logic
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// Need to revert the WrPtr for flush cases. Also revert the pipe WrPtrs
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assign WrPtrEn = (ldst_stbuf_reqvld_r & ~dual_stbuf_write_r & ~(store_coalesce_hi_r | store_coalesce_lo_r)) | // writing 1 and did not coalesce
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(ldst_stbuf_reqvld_r & dual_stbuf_write_r & ~(store_coalesce_hi_r & store_coalesce_lo_r)); // writing 2 and atleast 1 did not coalesce
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assign NxtWrPtr[DEPTH_LOG2-1:0] = (ldst_stbuf_reqvld_r & dual_stbuf_write_r & ~(store_coalesce_hi_r | store_coalesce_lo_r)) ? WrPtrPlus2[DEPTH_LOG2-1:0] : WrPtrPlus1[DEPTH_LOG2-1:0];
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assign RdPtrEn = lsu_stbuf_commit_any | stbuf_reqvld_flushed_any;
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assign NxtRdPtr[DEPTH_LOG2-1:0] = RdPtrPlus1[DEPTH_LOG2-1:0];
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always_comb begin
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stbuf_numvld_any[3:0] = '0;
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for (int i = 0; i < DEPTH; i++) begin
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stbuf_numvld_any[3:0] += {3'b0, stbuf_vld[i]};
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end
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end
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// These go to store buffer to detect full
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assign isdccmst_m = lsu_pkt_m.valid & lsu_pkt_m.store & addr_in_dccm_m & ~lsu_pkt_m.dma;
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assign isdccmst_r = lsu_pkt_r.valid & lsu_pkt_r.store & addr_in_dccm_r & ~lsu_pkt_r.dma;
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assign stbuf_specvld_m[1:0] = {1'b0, isdccmst_m} << (isdccmst_m & ldst_dual_m);
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assign stbuf_specvld_r[1:0] = {1'b0, isdccmst_r} << (isdccmst_r & ldst_dual_r);
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assign stbuf_specvld_any[3:0] = stbuf_numvld_any[3:0] + {2'b0, stbuf_specvld_m[1:0]} + {2'b0, stbuf_specvld_r[1:0]};
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assign lsu_stbuf_full_any = (~ldst_dual_d & dec_lsu_valid_raw_d) ? (stbuf_specvld_any[3:0] >= DEPTH) : (stbuf_specvld_any[3:0] >= (DEPTH-1));
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assign lsu_stbuf_empty_any = (stbuf_numvld_any[3:0] == 4'b0);
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// Load forwarding logic from the store queue
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assign cmpaddr_hi_m[pt.LSU_SB_BITS-1:$clog2(
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BYTE_WIDTH
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)] = end_addr_m[pt.LSU_SB_BITS-1:$clog2(
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BYTE_WIDTH
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)];
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assign cmpaddr_lo_m[pt.LSU_SB_BITS-1:$clog2(
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BYTE_WIDTH
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)] = lsu_addr_m[pt.LSU_SB_BITS-1:$clog2(
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BYTE_WIDTH
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)];
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always_comb begin : GenLdFwd
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stbuf_fwdbyteen_hi_pre_m[BYTE_WIDTH-1:0] = '0;
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stbuf_fwdbyteen_lo_pre_m[BYTE_WIDTH-1:0] = '0;
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for (int i = 0; i < DEPTH; i++) begin
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stbuf_match_hi[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] ==
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cmpaddr_hi_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)]) &
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stbuf_vld[i] & ~stbuf_dma_kill[i] & addr_in_dccm_m;
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stbuf_match_lo[i] = (stbuf_addr[i][pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)] ==
|
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cmpaddr_lo_m[pt.LSU_SB_BITS-1:$clog2(BYTE_WIDTH)]) &
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stbuf_vld[i] & ~stbuf_dma_kill[i] & addr_in_dccm_m;
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// Kill the store buffer entry if there is a dma store since it already updated the dccm
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stbuf_dma_kill_en[i] = (stbuf_match_hi[i] | stbuf_match_lo[i]) & lsu_pkt_m.valid & lsu_pkt_m.dma & lsu_pkt_m.store;
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for (int j = 0; j < BYTE_WIDTH; j++) begin
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stbuf_fwdbyteenvec_hi[i][j] = stbuf_match_hi[i] & stbuf_byteen[i][j] & stbuf_vld[i];
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stbuf_fwdbyteen_hi_pre_m[j] |= stbuf_fwdbyteenvec_hi[i][j];
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stbuf_fwdbyteenvec_lo[i][j] = stbuf_match_lo[i] & stbuf_byteen[i][j] & stbuf_vld[i];
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stbuf_fwdbyteen_lo_pre_m[j] |= stbuf_fwdbyteenvec_lo[i][j];
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end
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end
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end // block: GenLdFwd
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|
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always_comb begin : GenLdData
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stbuf_fwddata_hi_pre_m[31:0] = '0;
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stbuf_fwddata_lo_pre_m[31:0] = '0;
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|
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for (int i = 0; i < DEPTH; i++) begin
|
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stbuf_fwddata_hi_pre_m[31:0] |= {32{stbuf_match_hi[i]}} & stbuf_data[i][31:0];
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stbuf_fwddata_lo_pre_m[31:0] |= {32{stbuf_match_lo[i]}} & stbuf_data[i][31:0];
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|
|
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end
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end // block: GenLdData
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// Create Hi/Lo signals - needed for the pipe forwarding
|
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assign ldst_byteen_r[7:0] = ({8{lsu_pkt_r.by}} & 8'b0000_0001) |
|
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({8{lsu_pkt_r.half}} & 8'b0000_0011) |
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|
({8{lsu_pkt_r.word}} & 8'b0000_1111) |
|
|
({8{lsu_pkt_r.dword}} & 8'b1111_1111);
|
|
|
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assign ldst_byteen_ext_r[7:0] = ldst_byteen_r[7:0] << lsu_addr_r[1:0];
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|
|
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assign ldst_byteen_hi_r[3:0] = ldst_byteen_ext_r[7:4];
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assign ldst_byteen_lo_r[3:0] = ldst_byteen_ext_r[3:0];
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|
|
|
assign ld_addr_rhit_lo_lo = (lsu_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & ~lsu_pkt_r.dma;
|
|
assign ld_addr_rhit_lo_hi = (end_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & ~lsu_pkt_r.dma;
|
|
assign ld_addr_rhit_hi_lo = (lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & ~lsu_pkt_r.dma & dual_stbuf_write_r;
|
|
assign ld_addr_rhit_hi_hi = (end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & ~lsu_pkt_r.dma & dual_stbuf_write_r;
|
|
|
|
for (genvar i = 0; i < BYTE_WIDTH; i++) begin
|
|
assign ld_byte_rhit_lo_lo[i] = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i];
|
|
assign ld_byte_rhit_lo_hi[i] = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[i];
|
|
assign ld_byte_rhit_hi_lo[i] = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[i];
|
|
assign ld_byte_rhit_hi_hi[i] = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[i];
|
|
|
|
assign ld_byte_rhit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i];
|
|
assign ld_byte_rhit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i];
|
|
|
|
assign ld_fwddata_rpipe_lo[(8*i)+7:(8*i)] = ({8{ld_byte_rhit_lo_lo[i]}} & store_data_lo_r[(8*i)+7:(8*i)]) |
|
|
({8{ld_byte_rhit_hi_lo[i]}} & store_data_hi_r[(8*i)+7:(8*i)]);
|
|
|
|
assign ld_fwddata_rpipe_hi[(8*i)+7:(8*i)] = ({8{ld_byte_rhit_lo_hi[i]}} & store_data_lo_r[(8*i)+7:(8*i)]) |
|
|
({8{ld_byte_rhit_hi_hi[i]}} & store_data_hi_r[(8*i)+7:(8*i)]);
|
|
|
|
assign ld_byte_hit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i];
|
|
assign ld_byte_hit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i];
|
|
|
|
assign stbuf_fwdbyteen_hi_m[i] = ld_byte_hit_hi[i] | stbuf_fwdbyteen_hi_pre_m[i];
|
|
assign stbuf_fwdbyteen_lo_m[i] = ld_byte_hit_lo[i] | stbuf_fwdbyteen_lo_pre_m[i];
|
|
// // Pipe vs Store Queue priority
|
|
assign stbuf_fwddata_lo_m[(8*i)+7:(8*i)] = ld_byte_rhit_lo[i] ? ld_fwddata_rpipe_lo[(8*i)+7:(8*i)] : stbuf_fwddata_lo_pre_m[(8*i)+7:(8*i)];
|
|
// // Pipe vs Store Queue priority
|
|
assign stbuf_fwddata_hi_m[(8*i)+7:(8*i)] = ld_byte_rhit_hi[i] ? ld_fwddata_rpipe_hi[(8*i)+7:(8*i)] : stbuf_fwddata_hi_pre_m[(8*i)+7:(8*i)];
|
|
end
|
|
|
|
// Flops
|
|
rvdffs #(
|
|
.WIDTH(DEPTH_LOG2)
|
|
) WrPtrff (
|
|
.din (NxtWrPtr[DEPTH_LOG2-1:0]),
|
|
.dout(WrPtr[DEPTH_LOG2-1:0]),
|
|
.en (WrPtrEn),
|
|
.clk (lsu_stbuf_c1_clk),
|
|
.*
|
|
);
|
|
rvdffs #(
|
|
.WIDTH(DEPTH_LOG2)
|
|
) RdPtrff (
|
|
.din (NxtRdPtr[DEPTH_LOG2-1:0]),
|
|
.dout(RdPtr[DEPTH_LOG2-1:0]),
|
|
.en (RdPtrEn),
|
|
.clk (lsu_stbuf_c1_clk),
|
|
.*
|
|
);
|
|
|
|
endmodule
|
|
|