603 lines
17 KiB
C
603 lines
17 KiB
C
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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//signal remaning
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`ifdef JTAG_5
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`define jtag_tdo tb.jtg_tdo
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`define jtag_tdi tb.jtg_tdi
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`endif
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`define jtag_tclk tb.jclk
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`define jtag_tms tb.jtg_tms
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`define jtag_trst_b tb.jrst_b
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//-----------------------------------------------
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//define the instructions opcodes
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`define BKPT32 32'h80000000
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`define BKPT16 16'h0
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`define MOV_R0_R0 32'hc4004820
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`define MOV_R1_R1 32'hc4014821
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`define MOV_R2_R2 32'hc4024822
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`define MOV_R3_R3 32'hc4034823
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`define MOV_R4_R4 32'hc4044824
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`define MOV_R5_R5 32'hc4054825
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`define MOV_R6_R6 32'hc4064826
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`define MOV_R7_R7 32'hc4074827
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`define MOV_R8_R8 32'hc4084828
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`define MOV_R9_R9 32'hc4094829
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`define MOV_R10_R10 32'hc40a482a
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`define MOV_R11_R11 32'hc40b482b
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`define MOV_R12_R12 32'hc40c482c
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`define MOV_R13_R13 32'hc40d482d
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`define MOV_R14_R14 32'hc40e482e
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`define MOV_R15_R15 32'hc40f482f
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`define MOV_R16_R16 32'hc4104830
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`define MOV_R17_R17 32'hc4114831
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`define MOV_R18_R18 32'hc4124832
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`define MOV_R19_R19 32'hc4134833
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`define MOV_R20_R20 32'hc4144834
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`define MOV_R21_R21 32'hc4154835
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`define MOV_R22_R22 32'hc4164836
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`define MOV_R23_R23 32'hc4174837
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`define MOV_R24_R24 32'hc4184838
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`define MOV_R25_R25 32'hc4194839
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`define MOV_R26_R26 32'hc41a483a
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`define MOV_R27_R27 32'hc41b483b
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`define MOV_R28_R28 32'hc41c483c
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`define MOV_R29_R29 32'hc41d483d
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`define MOV_R30_R30 32'hc41e483e
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`define MOV_R31_R31 32'hc41f483f
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`define MFCR_R1_CR0 32'hc0006021
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`define MFCR_R1_CR1 32'hc0016021
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`define MFCR_R1_CR2 32'hc0026021
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`define MFCR_R1_CR3 32'hc0036021
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`define MFCR_R1_CR4 32'hc0046021
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`define MFCR_R1_CR5 32'hc0056021
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`define MFCR_R1_CR6 32'hc0066021
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`define MFCR_R1_CR7 32'hc0076021
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`define MFCR_R1_CR8 32'hc0086021
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`define MFCR_R1_CR9 32'hc0096021
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`define MFCR_R1_CR10 32'hc00a6021
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`define MFCR_R1_CR11 32'hc00b6021
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`define MFCR_R1_CR12 32'hc00c6021
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`define MFCR_R1_CR13 32'hc00d6021
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`define MFCR_R1_CR14 32'hc00e6021
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`define MFCR_R1_CR15 32'hc00f6021
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`define MFCR_R1_CR16 32'hc0106021
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`define MFCR_R1_CR17 32'hc0116021
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`define MFCR_R1_CR18 32'hc0126021
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`define MFCR_R1_CR19 32'hc0136021
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`define MFCR_R1_CR20 32'hc0146021
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`define MFCR_R1_CR21 32'hc0156021
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`define MTCR_R1_CR0 32'hc0016420
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`define MTCR_R1_CR1 32'hc0016421
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`define MTCR_R1_CR2 32'hc0016422
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`define MTCR_R1_CR3 32'hc0016423
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`define MTCR_R1_CR4 32'hc0016424
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`define MTCR_R1_CR5 32'hc0016425
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`define MTCR_R1_CR6 32'hc0016426
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`define MTCR_R1_CR7 32'hc0016427
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`define MTCR_R1_CR8 32'hc0016428
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`define MTCR_R1_CR9 32'hc0016429
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`define MTCR_R1_CR10 32'hc001642a
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`define MTCR_R1_CR11 32'hc001642b
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`define MTCR_R1_CR12 32'hc001642c
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`define MTCR_R1_CR13 32'hc001642d
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`define LDW_R1_R2_0x0 32'hd8222000
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`define LDW_R1_R2_0x4 32'hd8222001
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`define LDW_R1_R2_0x8 32'hd8222002
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`define LDW_R1_R2_0xc 32'hd8222003
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`define LDW_R1_R2_0x10 32'hd8222004
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`define LDW_R1_R2_0x14 32'hd8222005
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`define LDW_R1_R2_0x18 32'hd8222006
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`define LDW_R1_R2_0x1c 32'hd8222007
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`define LDW_R1_R2_0x20 32'hd8222008
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`define LDW_R1_R2_0x24 32'hd8222009
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`define LDW_R1_R2_0x28 32'hd822200a
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`define LDW_R1_R2_0x2c 32'hd822200b
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`define LDW_R1_R2_0x30 32'hd822200c
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`define LDW_R1_R2_0x34 32'hd822200d
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`define LDW_R1_R2_0x38 32'hd822200e
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`define LDW_R1_R2_0x3c 32'hd822200f
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`define LDW_R1_R2_0x40 32'hd8222010
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`define LDW_R1_R2_0x44 32'hd8222011
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`define LDW_R1_R2_0x48 32'hd8222012
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`define LDW_R1_R2_0x4c 32'hd8222013
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`define LDW_R1_R2_0x50 32'hd8222014
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`define LDW_R1_R2_0x54 32'hd8222015
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`define LDW_R1_R6_0x0 32'hd8262000
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`define LDW_R1_R6_0x4 32'hd8262001
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`define STW_R1_R2_0x0 32'hdc222000
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`define STW_R1_R5_0x0 32'hdc252000
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`define STW_R1_R5_0x4 32'hdc252001
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`define STW_R1_R5_0x8 32'hdc252002
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`define STW_R1_R5_0xc 32'hdc252003
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`define STW_R1_R5_0x10 32'hdc252004
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//-----------------------------------------------
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//define the HAD registers
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`define id 7'b0000010
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`define tracer 7'b0000011
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`define mbca 7'b0000100
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`define mbcb 7'b0000101
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`define pcfifo 7'b0000110
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`define baba 7'b0000111
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`define babb 7'b0001000
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`define bama 7'b0001001
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`define bamb 7'b0001010
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`define cpuscr 7'b0001011
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`define bypass 7'b0001100
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`define hcr 7'b0001101
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`define hsr 7'b0001110
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`define daddr 7'b0011000
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`define ddata 7'b0011001
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`define wbbr 7'b0010001
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`define psr 7'b0010010
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`define pc 7'b0010011
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`define ir 7'b0010100
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`define csr 7'b0010101
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`define wbbr_go_ex 7'b1110001
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`define wbbr_go_nex 7'b1010001
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`define wbbr_ngo_ex 7'b0110001
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`define wbbr_ngo_nex 7'b0010001
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`define psr_go_ex 7'b1110010
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`define psr_go_nex 7'b1010010
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`define psr_ngo_ex 7'b0110010
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`define psr_ngo_nex 7'b0010010
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`define pc_go_ex 7'b1110011
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`define pc_go_nex 7'b1010011
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`define pc_ngo_ex 7'b0110011
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`define pc_ngo_nex 7'b0010011
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`define ir_go_ex 7'b1110100
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`define ir_go_nex 7'b1010100
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`define ir_ngo_ex 7'b0110100
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`define ir_ngo_nex 7'b0010100
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`define csr_go_ex 7'b1110101
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`define csr_go_nex 7'b1010101
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`define csr_ngo_ex 7'b0110101
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`define csr_ngo_nex 7'b0010101
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`define cpuscr_go_ex 7'b1101011
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`define cpuscr_go_nex 7'b1001011
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`define bypass_go_ex 7'b1101100
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`define bypass_go_nex 7'b1001100
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`define bypass_ngo_ex 7'b0101100
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`define bypass_ngo_nex 7'b0001100
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`ifdef JTAG_5
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// Task for JTAG 5
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//jtag reset, for example: jtag_rst(100)
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task jtag_rst;
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input[31:0] rst_cycle;
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integer i;
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begin
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force `jtag_trst_b = 1'b1;
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force `jtag_tms = 1'b0;
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//wait until posedge tclk
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@(negedge `jtag_tclk);
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force `jtag_trst_b = 1'b0;
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//wait for user specified cycles
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for(i=0; i<rst_cycle; i=i+1)
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@(negedge `jtag_tclk);
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force `jtag_trst_b = 1'b1;
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//drive TAP state machine into IDLE state
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@(negedge `jtag_tclk);
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@(negedge `jtag_tclk);
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force `jtag_tms = 1'b0;
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end
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endtask
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//write IR
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task write_ir;
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input [7:0] ir_value;
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integer i;
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reg parity;
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begin
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@(negedge `jtag_tclk); //drive to Select DR Scan
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); //drive to Select IR Scan
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); //drive to Capture IR
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force `jtag_tms = 1'b0;
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@(negedge `jtag_tclk); //drive to Shift IR
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force `jtag_tms = 1'b0;
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@(negedge `jtag_tclk);
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for(i=0;i<7;i=i+1)begin
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force `jtag_tms = 1'b0;
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force `jtag_tdi = ir_value[i];
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@(negedge `jtag_tclk); //stay at Shift IR cycle
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end
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force `jtag_tms = 1'b1; //stay at Shift IR cycle 8,drive to EXIT IR
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force `jtag_tdi = ir_value[7];
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@(negedge `jtag_tclk); //drive to Update IR
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); //drive to IDLE
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force `jtag_tms = 1'b0;
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end
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endtask
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//write DR
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task write_dr;
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input [143:0] jtag_data_in;
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input [8:0] jtag_data_len;
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integer i;
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reg parity;
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begin
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@(negedge `jtag_tclk); //drive to Select DR Scan
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); //drive to Capture DR
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force `jtag_tms = 1'b0;
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@(negedge `jtag_tclk); //drive to Shift DR
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force `jtag_tms = 1'b0;
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@(negedge `jtag_tclk);
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for(i=0;i<jtag_data_len-1;i=i+1)begin
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force `jtag_tms = 1'b0;
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force `jtag_tdi = jtag_data_in[i];
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@(negedge `jtag_tclk); //stay at Shift DR cycle i
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end
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force `jtag_tms = 1'b1; //stay at Shift DR last cycle
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force `jtag_tdi = jtag_data_in[i];
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@(negedge `jtag_tclk); //drive to Update DR
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); //drive to IDLE
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force `jtag_tms = 1'b0;
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end
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endtask
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//Read DR
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task read_dr;
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input [8:0] jtag_data_len;
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output [143:0] jtag_data_out;
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reg [143:0] jtag_data_out;
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integer i;
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reg parity;
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begin
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@(negedge `jtag_tclk); //drive to Select DR Scan
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); //drive to Capture DR
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force `jtag_tms = 1'b0;
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@(negedge `jtag_tclk); //drive to Shift DR
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force `jtag_tms = 1'b0;
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for(i=0;i<jtag_data_len-1;i=i+1)begin
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@(negedge `jtag_tclk); //stay at Shift DR cycle i
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force `jtag_tms = 1'b0;
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@(posedge `jtag_tclk);
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jtag_data_out[i] = `jtag_tdo;
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end
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@(negedge `jtag_tclk); //stay at Shift DR last cycle
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force `jtag_tms = 1'b1;
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@(posedge `jtag_tclk);
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jtag_data_out[i] = `jtag_tdo;
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@(negedge `jtag_tclk); //drive to Update DR
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); //drive to IDLE
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force `jtag_tms = 1'b0;
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end
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endtask
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`else
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// Task for JTAG 2
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//jtag reset, for example: jtag_rst(100)
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task jtag_rst;
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input[31:0] rst_cycle;
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integer i;
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begin
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force `jtag_trst_b = 1'b1;
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force `jtag_tms = 1'b1;
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//wait until posedge tclk
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@(negedge `jtag_tclk);
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force `jtag_trst_b = 1'b0;
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//wait for user specified cycles
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for(i=0; i<rst_cycle; i=i+1)
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@(negedge `jtag_tclk);
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force `jtag_trst_b = 1'b1;
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//drive TAP state machine into IDLE state
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@(negedge `jtag_tclk);
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@(negedge `jtag_tclk);
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force `jtag_tms = 1'b1;
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end
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endtask
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//write IR
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task write_ir;
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input [7:0] ir_value;
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integer i;
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reg parity;
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begin
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parity = 1'b1;
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@(negedge `jtag_tclk); // start
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force `jtag_tms = 1'b0;
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@(negedge `jtag_tclk); // read/write
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force `jtag_tms = 1'b0;
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@(negedge `jtag_tclk); // RS[0]
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force `jtag_tms = 1'b0;
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@(negedge `jtag_tclk); // RS[1]
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); // Trn
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk);
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for(i=0; i<8; i=i+1)begin
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force `jtag_tms = ir_value[i];
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parity = parity ^ ir_value[i];
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@(negedge `jtag_tclk); // Shift IR
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end
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force `jtag_tms = parity;
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@(negedge `jtag_tclk); // Parity
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); // Trn
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); // IDLE
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end
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endtask
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//write DR
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task write_dr;
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input [143:0] jtag_data_in;
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input [8:0] jtag_data_len;
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integer i;
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reg parity;
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begin
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parity = 1'b1;
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@(negedge `jtag_tclk); // start
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force `jtag_tms = 1'b0;
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@(negedge `jtag_tclk); // read/write
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force `jtag_tms = 1'b0;
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@(negedge `jtag_tclk); // RS[0]
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); // RS[1]
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); // Trn
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk);
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for(i=0; i<32; i=i+1)begin
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force `jtag_tms = jtag_data_in[i];
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parity = parity ^ jtag_data_in[i];
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@(negedge `jtag_tclk); // Shift DR
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end
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force `jtag_tms = parity; // Parity
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@(negedge `jtag_tclk); // Trn
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); // Drive to IDLE
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force `jtag_tms = 1'b1;
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end
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endtask
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//Read DR
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task read_dr;
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input [8:0] jtag_data_len;
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output [143:0] jtag_data_out;
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reg [143:0] jtag_data_out;
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integer i;
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reg parity;
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begin
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parity = 1'b1;
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@(negedge `jtag_tclk); // start
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force `jtag_tms = 1'b0;
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@(negedge `jtag_tclk); // read/write
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); // RS[0]
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); // RS[1]
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force `jtag_tms = 1'b1;
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@(negedge `jtag_tclk); // Trn
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force `jtag_tms = 1'b1;
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@(posedge `jtag_tclk);
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release `jtag_tms;
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@(posedge `jtag_tclk); // Sync cycle
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for(i=0; i<32; i=i+1)begin
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@(posedge `jtag_tclk); // Shift DR
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jtag_data_out[i] = `jtag_tms;
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end
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@(posedge `jtag_tclk); // Parity
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parity = `jtag_tms;
|
|
@(negedge `jtag_tclk); // Trn
|
|
force `jtag_tms = 1'b1;
|
|
@(negedge `jtag_tclk); // to IDLE
|
|
force `jtag_tms = 1'b1;
|
|
end
|
|
endtask
|
|
`endif
|
|
|
|
/*****************************************************
|
|
The following task has defined the task write_hadreg.
|
|
User can invoke this task to write the target register.
|
|
If user want to write register and set go,ex simultan
|
|
-eously,just add some identifiers in agreement such as
|
|
_go_ex,_go_nex,_ngo_ex,_ngo_nex.
|
|
Special condition:the registor Bypass was cut,just reserve
|
|
the interface to keep the compatibility with CK6xx and CK5xx
|
|
usage: write_hadreg(`target_reg_name,value)
|
|
write_hadreg(`wbbr_go_ex,value)
|
|
*******************************************************/
|
|
task write_hadreg;
|
|
input[6:0] reg_select;
|
|
input[143:0] reg_value;
|
|
// input[143:0] cpuscr_value;
|
|
begin
|
|
case(reg_select & 7'b0011111)
|
|
`id,
|
|
`pcfifo,
|
|
`baba,
|
|
`babb,
|
|
`wbbr,
|
|
`psr,
|
|
`pc,
|
|
`ir,
|
|
`hcr,
|
|
`daddr,
|
|
`ddata : begin
|
|
write_ir({1'b0,reg_select[6:0]});//select id
|
|
write_dr(reg_value,32);
|
|
end
|
|
|
|
`tracer,
|
|
`mbca,
|
|
`mbcb,
|
|
`bama,
|
|
`bamb,
|
|
`bypass: begin
|
|
write_ir({1'b0,reg_select[6:0]});//select mbcb
|
|
write_dr(reg_value,8);
|
|
end
|
|
|
|
`hsr,
|
|
`csr : begin
|
|
write_ir({1'b0,reg_select[6:0]});//select hsr
|
|
write_dr(reg_value,16);
|
|
end
|
|
|
|
`cpuscr : begin
|
|
write_ir({1'b0,reg_select[6:0]});
|
|
write_dr(reg_value,128);
|
|
end
|
|
|
|
default:$display("There is no target!");
|
|
endcase
|
|
end
|
|
endtask
|
|
|
|
/*****************************************************
|
|
The following task has defined the task read_hadreg.
|
|
User can invoke this task to read the target
|
|
register.
|
|
Special condition:the same to write_hadreg.
|
|
usage:read_hadreg(`target_reg_name,value)
|
|
*******************************************************/
|
|
task read_hadreg;
|
|
input[6:0] reg_select;
|
|
// output[143:0] jtag_cpuscr_out;
|
|
output[143:0] jtag_data_out;
|
|
reg[143:0] jtag_data_out;
|
|
// reg[143:0] jtag_cpuscr_out;
|
|
begin
|
|
case(reg_select & 7'b0011111)
|
|
`id,
|
|
`pcfifo,
|
|
`baba,
|
|
`babb,
|
|
`wbbr,
|
|
`psr,
|
|
`pc,
|
|
`ir,
|
|
`hcr,
|
|
`daddr,
|
|
`ddata : begin
|
|
write_ir({1'b1,reg_select[6:0]});//select id
|
|
read_dr(32, jtag_data_out);
|
|
end
|
|
|
|
`tracer,
|
|
`mbca,
|
|
`mbcb,
|
|
`bama,
|
|
`bamb,
|
|
`bypass:begin
|
|
write_ir({1'b1,reg_select[6:0]});//select mbcb
|
|
read_dr(8, jtag_data_out);
|
|
end
|
|
|
|
`hsr,
|
|
`csr : begin
|
|
write_ir({1'b1,reg_select[6:0]});//select hsr
|
|
read_dr(16, jtag_data_out);
|
|
end
|
|
|
|
`cpuscr : begin
|
|
write_ir({1'b1,reg_select[6:0]});
|
|
read_dr(128, jtag_data_out);
|
|
end
|
|
|
|
default:$display("There is no target!");
|
|
endcase
|
|
end
|
|
endtask
|
|
|
|
/***********************************************************
|
|
The following task was defined to wait CPU enter into debug
|
|
mode.
|
|
************************************************************/
|
|
task wait_debug_mode;
|
|
reg[15:0] hsr_data_out;
|
|
begin
|
|
read_hadreg(`hsr,hsr_data_out);
|
|
$display("---------------------------------------");
|
|
$display("wait into debug mode...... |");
|
|
$display("<wait_begin> The hsr is: 0x%h |",
|
|
hsr_data_out[15:0]);
|
|
while(hsr_data_out[1:0]!=2'b10)
|
|
read_hadreg(`hsr,hsr_data_out);
|
|
$display("<wait_end> The hsr is: 0x%h |",
|
|
hsr_data_out[15:0]);
|
|
$display("Now, CPU is in Debug Mode! |");
|
|
$display("---------------------------------------");
|
|
end
|
|
endtask
|
|
|
|
/***********************************************************
|
|
The following task was defined to check the cpu mode.
|
|
If the cpu has into debug mode,
|
|
************************************************************/
|
|
task check_cpu_mode;
|
|
reg[15:0] hsr_data_out;
|
|
begin
|
|
read_hadreg(`hsr,hsr_data_out);
|
|
if(hsr_data_out[1:0]==2'b00)
|
|
begin
|
|
$display("----------------------------------------");
|
|
$display("*** <CHECK> hsr value is:0x%h *** |",
|
|
hsr_data_out[15:0]);
|
|
$display("*** CPU is in Normal Mode! *** |");
|
|
$display("----------------------------------------");
|
|
end
|
|
else if(hsr_data_out[1:0]==2'b01)
|
|
begin
|
|
$display("----------------------------------------");
|
|
$display("*** <CHECK> hsr value is:0x%h *** |",
|
|
hsr_data_out[15:0]);
|
|
$display("*** CPU is in LowPower Mode! *** |");
|
|
$display("----------------------------------------");
|
|
end
|
|
else if(hsr_data_out[1:0]==2'b10)
|
|
begin
|
|
$display("----------------------------------------");
|
|
$display("*** <CHECK> hsr value is:0x%h *** |",
|
|
hsr_data_out[15:0]);
|
|
$display("*** CPU is in Debug Mode! *** |");
|
|
$display("----------------------------------------");
|
|
end
|
|
else
|
|
begin
|
|
$display("----------------------------------------");
|
|
$display("*** <CHECK> hsr value is:0x%h *** |",
|
|
hsr_data_out[15:0]);
|
|
$display("*** CPU is in Reserve Mode! *** |");
|
|
$display("----------------------------------------");
|
|
end
|
|
end
|
|
endtask
|
|
|