443 lines
16 KiB
Systemverilog
443 lines
16 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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`ifndef VERILATOR
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module tb_top;
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`else
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module tb_top ( input logic core_clk, input logic reset_l, output finished);
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`endif
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`ifndef VERILATOR
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logic reset_l;
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logic core_clk;
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`endif
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logic nmi_int;
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logic [31:0] reset_vector;
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logic [31:0] nmi_vector;
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logic [31:1] jtag_id;
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logic [31:0] ic_haddr ;
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logic [2:0] ic_hburst ;
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logic ic_hmastlock ;
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logic [3:0] ic_hprot ;
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logic [2:0] ic_hsize ;
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logic [1:0] ic_htrans ;
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logic ic_hwrite ;
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logic [63:0] ic_hrdata ;
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logic ic_hready ;
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logic ic_hresp ;
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logic [31:0] lsu_haddr ;
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logic [2:0] lsu_hburst ;
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logic lsu_hmastlock ;
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logic [3:0] lsu_hprot ;
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logic [2:0] lsu_hsize ;
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logic [1:0] lsu_htrans ;
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logic lsu_hwrite ;
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logic [63:0] lsu_hrdata ;
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logic [63:0] lsu_hwdata ;
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logic lsu_hready ;
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logic lsu_hresp ;
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logic [31:0] sb_haddr ;
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logic [2:0] sb_hburst ;
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logic sb_hmastlock ;
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logic [3:0] sb_hprot ;
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logic [2:0] sb_hsize ;
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logic [1:0] sb_htrans ;
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logic sb_hwrite ;
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logic [63:0] sb_hrdata ;
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logic [63:0] sb_hwdata ;
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logic sb_hready ;
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logic sb_hresp ;
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logic [63:0] trace_rv_i_insn_ip;
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logic [63:0] trace_rv_i_address_ip;
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logic [2:0] trace_rv_i_valid_ip;
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logic [2:0] trace_rv_i_exception_ip;
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logic [4:0] trace_rv_i_ecause_ip;
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logic [2:0] trace_rv_i_interrupt_ip;
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logic [31:0] trace_rv_i_tval_ip;
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logic o_debug_mode_status;
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logic [1:0] dec_tlu_perfcnt0;
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logic [1:0] dec_tlu_perfcnt1;
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logic [1:0] dec_tlu_perfcnt2;
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logic [1:0] dec_tlu_perfcnt3;
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logic jtag_tdo;
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logic o_cpu_halt_ack;
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logic o_cpu_halt_status;
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logic o_cpu_run_ack;
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logic mailbox_write;
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logic [63:0] dma_hrdata ;
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logic [63:0] dma_hwdata ;
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logic dma_hready ;
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logic dma_hresp ;
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logic mpc_debug_halt_req;
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logic mpc_debug_run_req;
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logic mpc_reset_run_req;
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logic mpc_debug_halt_ack;
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logic mpc_debug_run_ack;
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logic debug_brkpt_status;
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logic [31:0] cycleCnt ;
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logic mailbox_data_val;
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`ifndef VERILATOR
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logic finished;
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`endif
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wire dma_hready_out;
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integer commit_count;
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logic wb_valid[1:0];
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logic [4:0] wb_dest[1:0];
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logic [31:0] wb_data[1:0];
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//assign mailbox_write = &{i_ahb_lsu.Write, i_ahb_lsu.Last_HADDR==32'hD0580000, i_ahb_lsu.HRESETn==1};
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assign mailbox_write = i_ahb_lsu.mailbox_write;
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//assign mailbox_write = i_ahb_lsu.mailbox_write & !core_clk;
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assign mailbox_data_val = (i_ahb_lsu.WriteData[7:0] > 8'h5) & (i_ahb_lsu.WriteData[7:0] < 8'h7f);
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assign finished = finished | &{i_ahb_lsu.mailbox_write, (i_ahb_lsu.WriteData[7:0] == 8'hff)};
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assign jtag_id[31:28] = 4'b1;
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assign jtag_id[27:12] = '0;
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assign jtag_id[11:1] = 11'h45;
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`ifndef VERILATOR
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`define FORCE force
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`else
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`define FORCE
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`endif
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integer fd;
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initial begin
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fd = $fopen("console.log","w");
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commit_count = 0;
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end
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integer tp,el;
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always @(posedge core_clk or negedge reset_l) begin
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if( reset_l == 0)
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cycleCnt <= 0;
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else
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cycleCnt <= cycleCnt+1;
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end
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always @(posedge core_clk) begin
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//if(cycleCnt == 32'h800)
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if(cycleCnt == 32'h800) begin
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$display ("Hit max cycle count.. stopping");
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$finish;
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end
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end
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`ifdef VERILATOR
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always @(negedge mailbox_write)
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`else
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always @(posedge mailbox_write)
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`endif
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if( mailbox_data_val ) begin
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$fwrite(fd,"%c", i_ahb_lsu.WriteData[7:0]);
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$write("%c", i_ahb_lsu.WriteData[7:0]);
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end
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always @(posedge finished) begin
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$display("\n\nFinished : minstret = %0d, mcycle = %0d", rvtop.swerv.dec.tlu.minstretl[31:0],rvtop.swerv.dec.tlu.mcyclel[31:0]);
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$display("\n\nSee \"exec.log\" for execution trace with register updates..\n");
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`ifndef VERILATOR
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$finish;
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`endif
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end
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always @(posedge core_clk) begin
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wb_valid[1:0] <= '{rvtop.swerv.dec.dec_i1_wen_wb & ~rvtop.swerv.dec.decode.dec_tlu_i1_kill_writeb_wb,
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rvtop.swerv.dec.decode.wbd.i0v & ~rvtop.swerv.dec.decode.dec_tlu_i0_kill_writeb_wb};
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wb_dest[1:0] <= '{rvtop.swerv.dec.dec_i1_waddr_wb, rvtop.swerv.dec.dec_i0_waddr_wb};
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wb_data[1:0] <= '{rvtop.swerv.dec.dec_i1_wdata_wb, rvtop.swerv.dec.dec_i0_wdata_wb};
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if (rvtop.trace_rv_i_valid_ip !== 0) begin
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$fwrite(tp,"%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", rvtop.trace_rv_i_valid_ip, rvtop.trace_rv_i_address_ip[63:32], rvtop.trace_rv_i_address_ip[31:0], rvtop.trace_rv_i_insn_ip[63:32], rvtop.trace_rv_i_insn_ip[31:0],rvtop.trace_rv_i_exception_ip,rvtop.trace_rv_i_ecause_ip,rvtop.trace_rv_i_tval_ip,rvtop.trace_rv_i_interrupt_ip);
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// Basic trace - no exception register updates
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// #1 0 ee000000 b0201073 c 0b02 00000000
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if (rvtop.trace_rv_i_valid_ip[0]==1) begin
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commit_count ++;
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$fwrite (el, "%0d : #%0d 0 %0h %0h r %0d %0h\n",$time(), commit_count, rvtop.trace_rv_i_address_ip[31:0], rvtop.trace_rv_i_insn_ip[31:0], wb_dest[0], wb_data[0]);
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end
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if (rvtop.trace_rv_i_valid_ip[1]==1) begin
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commit_count ++;
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$fwrite (el, "%0d : #%0d 0 0x%0h 0x%0h r %0d 0x%h\n",$time(), commit_count, rvtop.trace_rv_i_address_ip[63:32], rvtop.trace_rv_i_insn_ip[63:32], wb_dest[1], wb_data[1]);
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end
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end
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end
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initial begin
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`ifndef VERILATOR
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core_clk = 0;
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reset_l = 0;
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`endif
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reset_vector = 32'h80000000;
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nmi_vector = 32'hee000000;
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nmi_int = 0;
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`ifndef VERILATOR
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@(posedge core_clk);
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reset_l = 0;
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`endif
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$readmemh("data.hex", i_ahb_lsu.mem);
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$readmemh("program.hex", i_ahb_ic.mem);
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tp = $fopen("trace_port.csv","w");
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el = $fopen("exec.log","w");
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$fwrite (el, "//Time : #inst 0 pc opcode reg regnum value\n");
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`ifndef VERILATOR
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repeat (5) @(posedge core_clk);
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reset_l = 1;
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#100000 $display("");$finish;
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`endif
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end
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`ifndef VERILATOR
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initial begin
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forever begin
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core_clk = #5 ~core_clk;
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end
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end
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`endif
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//=========================================================================-
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// RTL instance
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//=========================================================================-
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swerv_wrapper rvtop (
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.rst_l ( reset_l ),
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.clk ( core_clk ),
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.rst_vec ( 31'h40000000 ),
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.nmi_int ( nmi_int ),
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.nmi_vec ( 31'h77000000 ),
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.jtag_id (jtag_id[31:1]),
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.haddr ( ic_haddr ),
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.hburst ( ic_hburst ),
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.hmastlock ( ic_hmastlock ),
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.hprot ( ic_hprot ),
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.hsize ( ic_hsize ),
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.htrans ( ic_htrans ),
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.hwrite ( ic_hwrite ),
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.hrdata ( ic_hrdata[63:0]),
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.hready ( ic_hready ),
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.hresp ( ic_hresp ),
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//---------------------------------------------------------------
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// Debug AHB Master
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//---------------------------------------------------------------
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.sb_haddr ( sb_haddr ),
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.sb_hburst ( sb_hburst ),
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.sb_hmastlock ( sb_hmastlock ),
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.sb_hprot ( sb_hprot ),
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.sb_hsize ( sb_hsize ),
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.sb_htrans ( sb_htrans ),
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.sb_hwrite ( sb_hwrite ),
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.sb_hwdata ( sb_hwdata ),
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.sb_hrdata ( sb_hrdata ),
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.sb_hready ( sb_hready ),
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.sb_hresp ( sb_hresp ),
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//---------------------------------------------------------------
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// LSU AHB Master
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//---------------------------------------------------------------
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.lsu_haddr ( lsu_haddr ),
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.lsu_hburst ( lsu_hburst ),
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.lsu_hmastlock ( lsu_hmastlock ),
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.lsu_hprot ( lsu_hprot ),
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.lsu_hsize ( lsu_hsize ),
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.lsu_htrans ( lsu_htrans ),
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.lsu_hwrite ( lsu_hwrite ),
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.lsu_hwdata ( lsu_hwdata ),
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.lsu_hrdata ( lsu_hrdata[63:0]),
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.lsu_hready ( lsu_hready ),
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.lsu_hresp ( lsu_hresp ),
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//---------------------------------------------------------------
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// DMA Slave
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//---------------------------------------------------------------
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.dma_haddr ( '0 ),
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.dma_hburst ( '0 ),
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.dma_hmastlock ( '0 ),
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.dma_hprot ( '0 ),
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.dma_hsize ( '0 ),
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.dma_htrans ( '0 ),
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.dma_hwrite ( '0 ),
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.dma_hwdata ( '0 ),
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.dma_hrdata ( dma_hrdata ),
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.dma_hresp ( dma_hresp ),
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.dma_hsel ( 1'b1 ),
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.dma_hreadyin ( dma_hready_out ),
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.dma_hreadyout ( dma_hready_out ),
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.timer_int ( 1'b0 ),
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`ifdef TB_RESTRUCT
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.extintsrc_req ( '0 ),
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`else
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.extintsrc_req ( '0 ),
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`endif
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`ifdef RV_BUILD_AHB_LITE
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.lsu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface
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.ifu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface
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.dbg_bus_clk_en ( 1'b0 ),// Clock ratio b/w cpu core clk & AHB Debug master interface
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.dma_bus_clk_en ( 1'b0 ),// Clock ratio b/w cpu core clk & AHB slave interface
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`endif
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.trace_rv_i_insn_ip(trace_rv_i_insn_ip),
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.trace_rv_i_address_ip(trace_rv_i_address_ip),
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.trace_rv_i_valid_ip(trace_rv_i_valid_ip),
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.trace_rv_i_exception_ip(trace_rv_i_exception_ip),
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.trace_rv_i_ecause_ip(trace_rv_i_ecause_ip),
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.trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip),
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.trace_rv_i_tval_ip(trace_rv_i_tval_ip),
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.jtag_tck ( 1'b0 ), // JTAG clk
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.jtag_tms ( 1'b0 ), // JTAG TMS
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.jtag_tdi ( 1'b0 ), // JTAG tdi
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.jtag_trst_n ( 1'b0 ), // JTAG Reset
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.jtag_tdo ( jtag_tdo ), // JTAG TDO
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.mpc_debug_halt_ack ( mpc_debug_halt_ack),
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.mpc_debug_halt_req ( 1'b0),
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.mpc_debug_run_ack ( mpc_debug_run_ack),
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.mpc_debug_run_req ( 1'b1),
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.mpc_reset_run_req ( 1'b1), // Start running after reset
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.debug_brkpt_status (debug_brkpt_status),
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.i_cpu_halt_req ( 1'b0 ), // Async halt req to CPU
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.o_cpu_halt_ack ( o_cpu_halt_ack ), // core response to halt
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.o_cpu_halt_status ( o_cpu_halt_status ), // 1'b1 indicates core is halted
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.i_cpu_run_req ( 1'b0 ), // Async restart req to CPU
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.o_debug_mode_status (o_debug_mode_status),
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.o_cpu_run_ack ( o_cpu_run_ack ), // Core response to run req
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.dec_tlu_perfcnt0(dec_tlu_perfcnt0),
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.dec_tlu_perfcnt1(dec_tlu_perfcnt1),
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.dec_tlu_perfcnt2(dec_tlu_perfcnt2),
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.dec_tlu_perfcnt3(dec_tlu_perfcnt3),
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.scan_mode ( 1'b0 ), // To enable scan mode
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.mbist_mode ( 1'b0 ) // to enable mbist
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);
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initial begin
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`FORCE rvtop.dccm_rd_data_hi = '0;
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`FORCE rvtop.dccm_rd_data_lo = '0;
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end
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//=========================================================================-
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// AHB I$ instance
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//=========================================================================-
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ahb_sif i_ahb_ic (
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// Inputs
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.HWDATA(64'h0),
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.HCLK(core_clk),
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.HSEL(1'b1),
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.HPROT(ic_hprot),
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.HWRITE(ic_hwrite),
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.HTRANS(ic_htrans),
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.HSIZE(ic_hsize),
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.HREADY(ic_hready),
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.HRESETn(reset_l),
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.HADDR(ic_haddr),
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.HBURST(ic_hburst),
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// Outputs
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.HREADYOUT(ic_hready),
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.HRESP(ic_hresp),
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.HRDATA(ic_hrdata[63:0])
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);
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ahb_sif i_ahb_lsu (
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// Inputs
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.HWDATA(lsu_hwdata),
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.HCLK(core_clk),
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.HSEL(1'b1),
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.HPROT(lsu_hprot),
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.HWRITE(lsu_hwrite),
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.HTRANS(lsu_htrans),
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.HSIZE(lsu_hsize),
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.HREADY(lsu_hready),
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.HRESETn(reset_l),
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.HADDR(lsu_haddr),
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.HBURST(lsu_hburst),
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// Outputs
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.HREADYOUT(lsu_hready),
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.HRESP(lsu_hresp),
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.HRDATA(lsu_hrdata[63:0])
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);
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ahb_sif i_ahb_sb (
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// Inputs
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.HWDATA(sb_hwdata),
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.HCLK(core_clk),
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.HSEL(1'b1),
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.HPROT(sb_hprot),
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.HWRITE(sb_hwrite),
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.HTRANS(sb_htrans),
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.HSIZE(sb_hsize),
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.HREADY(1'b0),
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.HRESETn(reset_l),
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.HADDR(sb_haddr),
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.HBURST(sb_hburst),
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// Outputs
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.HREADYOUT(sb_hready),
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.HRESP(sb_hresp),
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.HRDATA(sb_hrdata[63:0])
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);
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endmodule
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