50 lines
1.2 KiB
Bash
Executable File
50 lines
1.2 KiB
Bash
Executable File
#!/bin/bash
|
|
set -ex
|
|
|
|
SOC=../Murax.v
|
|
|
|
YOSYS_COARSE=true
|
|
YOSYS_GLOBRST=false
|
|
YOSYS_SPLITNETS=false
|
|
TOP="Murax"
|
|
|
|
mkdir -p gen
|
|
rm -rf gen/*
|
|
|
|
{
|
|
echo "read_verilog ${SOC}"
|
|
|
|
if test -n "$TOP"; then
|
|
echo "hierarchy -check -top $TOP"
|
|
else
|
|
echo "hierarchy -check"
|
|
fi
|
|
if $YOSYS_GLOBRST; then
|
|
# insertation of global reset (e.g. for FPGA cores)
|
|
echo "add -global_input globrst 1"
|
|
echo "proc -global_arst globrst"
|
|
fi
|
|
echo "synth -run coarse; opt -fine"
|
|
# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
|
|
if ! $YOSYS_COARSE; then
|
|
echo "memory_map; techmap; opt; abc -dff; clean"
|
|
fi
|
|
if $YOSYS_SPLITNETS; then
|
|
# icarus verilog has a performance problems when there are
|
|
# dependencies between the bits of a long vector
|
|
echo "splitnets; clean"
|
|
fi
|
|
if $YOSYS_COARSE; then
|
|
echo "write_verilog -noexpr -noattr gen/synth.v"
|
|
else
|
|
echo "select -assert-none t:\$[!_]"
|
|
echo "write_verilog -noattr gen/synth.v"
|
|
fi
|
|
echo "synth_ecp5 -top $TOP -json gen/soc.json"
|
|
# echo "synth_xilinx -top $TOP"
|
|
} > gen/synth.ys
|
|
|
|
yosys -v2 -l gen/synth.log gen/synth.ys
|
|
|
|
nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg gen/soc.cfg --lpf Colorlight_i5_v6.0-extboard.lpf --freq 100 --json gen/soc.json
|