83 lines
2.7 KiB
Verilog
83 lines
2.7 KiB
Verilog
//`include "global_define.v"
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module TOP(
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inout wire [14:0] DDR_addr,
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inout wire [2:0] DDR_ba,
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inout wire DDR_cas_n,
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inout wire DDR_ck_n,
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inout wire DDR_ck_p,
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inout wire DDR_cke,
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inout wire DDR_cs_n,
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inout wire [3:0] DDR_dm,
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inout wire [31:0] DDR_dq,
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inout wire [3:0] DDR_dqs_n,
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inout wire [3:0] DDR_dqs_p,
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inout wire DDR_odt,
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inout wire DDR_ras_n,
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inout wire DDR_reset_n,
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inout wire DDR_we_n,
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inout wire FIXED_IO_ddr_vrn,
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inout wire FIXED_IO_ddr_vrp,
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inout wire [53:0] FIXED_IO_mio,
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inout wire FIXED_IO_ps_clk,
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inout wire FIXED_IO_ps_porb,
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inout wire FIXED_IO_ps_srstb,
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//misc
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//input wire key,
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output wire led1,
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output wire led2,
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output wire led3,
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input wire uart_rx,
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output wire uart_tx
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);
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// assign led1 = ~vout_lvds_mmcm_locked;
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// assign led2 = ~led_b;
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wire led_b;
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wire clk_axi;
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design_1 u_bd(
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.DDR_addr (DDR_addr ),
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.DDR_ba (DDR_ba ),
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.DDR_cas_n (DDR_cas_n ),
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.DDR_ck_n (DDR_ck_n ),
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.DDR_ck_p (DDR_ck_p ),
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.DDR_cke (DDR_cke ),
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.DDR_cs_n (DDR_cs_n ),
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.DDR_dm (DDR_dm ),
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.DDR_dq (DDR_dq ),
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.DDR_dqs_n (DDR_dqs_n ),
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.DDR_dqs_p (DDR_dqs_p ),
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.DDR_odt (DDR_odt ),
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.DDR_ras_n (DDR_ras_n ),
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.DDR_reset_n (DDR_reset_n ),
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.DDR_we_n (DDR_we_n ),
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.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn ),
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.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp ),
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.FIXED_IO_mio (FIXED_IO_mio ),
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.FIXED_IO_ps_clk (FIXED_IO_ps_clk ),
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.FIXED_IO_ps_porb (FIXED_IO_ps_porb ),
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.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb ),
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.UART_rxd (uart_rx ),
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.UART_txd (uart_tx ),
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.clk_axi (clk_axi ),
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.rstn_axi ( )
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);
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//--------------------------------led----------------------------------
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led led_breath(
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.clk (clk_axi ),
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.led (led_b )
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);
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assign led1 = led_b;
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assign led2 = led_b;
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assign led3 = led_b;
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endmodule
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