119 lines
2.8 KiB
Verilog
119 lines
2.8 KiB
Verilog
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// &ModuleBeg; @28
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module wic(
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awake_data,
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awake_disable,
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awake_enable,
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int_cfg,
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int_exit,
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int_pending,
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int_vld,
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pad_cpu_rst_b,
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pending_clr,
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wic_awake_en,
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wic_clk
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);
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// &Ports; @29
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input awake_data;
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input awake_disable;
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input awake_enable;
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input int_cfg;
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input int_exit;
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input int_vld;
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input pad_cpu_rst_b;
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input pending_clr;
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input wic_clk;
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output int_pending;
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output wic_awake_en;
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// &Regs; @30
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reg int_pending;
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reg int_vld_ff;
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reg wic_awake_en;
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// &Wires; @31
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wire awake_data;
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wire awake_disable;
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wire awake_enable;
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wire int_cfg;
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wire int_exit;
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wire int_level;
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wire int_pulse;
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wire int_vld;
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wire pad_cpu_rst_b;
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wire pending_clr;
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wire wic_clk;
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//always@(posedge wic_clk or negedge pad_cpu_rst_b)
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//begin
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// if (!pad_cpu_rst_b)
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// pending_ctrl_ff <= 1'b0;
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// else
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// pending_ctrl_ff <= pending_ctrl;
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//end
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always@(posedge wic_clk or negedge pad_cpu_rst_b)
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begin
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if (!pad_cpu_rst_b)
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wic_awake_en <= 1'b0;
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else if (awake_enable && awake_data)
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wic_awake_en <= 1'b1;
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else if (awake_disable && awake_data)
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wic_awake_en <= 1'b0;
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end
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//------------------------------------------------
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// sample level-sensitive interrupt
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//------------------------------------------------
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assign int_level = int_vld && !int_cfg && int_exit;
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//------------------------------------------------
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// sample pulse-sensitive interrupt
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//------------------------------------------------
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always@(posedge wic_clk or negedge pad_cpu_rst_b)
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begin
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if (!pad_cpu_rst_b)
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int_vld_ff <= 1'b0;
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else
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int_vld_ff <= int_vld;
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end
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assign int_pulse = int_vld && !int_vld_ff;
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//------------------------------------------------
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// int pending
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//------------------------------------------------
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always@(posedge wic_clk or negedge pad_cpu_rst_b)
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begin
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if(!pad_cpu_rst_b)
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int_pending <= 1'b0;
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else if (!int_cfg)
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int_pending <= int_level;
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else if (pending_clr)
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int_pending <= 1'b0;
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else if(int_cfg)
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int_pending <= int_pulse;
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end
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// &ModuleEnd; @98
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endmodule
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