283 lines
12 KiB
Verilog
283 lines
12 KiB
Verilog
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// &Depend("cpu_cfig.h"); @23
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// &ModuleBeg; @24
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module wic_top(
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ctl_xx_awake_enable,
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gpio_vic_int,
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intraw_vld,
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nmi_wake_int_higher,
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pad_cpu_rst_b,
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pad_vic_int_vld,
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pulse_int,
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stim_vic_int,
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tim1_vic_int,
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tim_vic_int,
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uart0_vic_int,
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wic_clk
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);
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// &Ports; @25
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input [31:0] ctl_xx_awake_enable;
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input [7 :0] gpio_vic_int;
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input [1 :0] nmi_wake_int_higher;
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input pad_cpu_rst_b;
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input pulse_int;
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input [3 :0] stim_vic_int;
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input [3 :0] tim1_vic_int;
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input [3 :0] tim_vic_int;
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input uart0_vic_int;
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input wic_clk;
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output intraw_vld;
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output [31:0] pad_vic_int_vld;
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// &Regs; @26
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reg [31:0] arb_int_ack;
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reg [31:0] arb_int_ack_ff;
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// &Wires; @27
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wire [31:0] arb_int_ack_clr;
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wire ctim_int_vld;
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wire [31:0] ctl_xx_awake_enable;
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wire [7 :0] gpio_vic_int;
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wire [4 :0] int_ack_vec;
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wire [31:0] int_pending;
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wire intraw_vld;
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wire [1 :0] nmi_wake_int_higher;
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wire pad_cpu_rst_b;
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wire [31:0] pad_vic_int_cfg;
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wire [31:0] pad_vic_int_vld;
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wire [31:0] pad_wic_int_cfg;
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wire [31:0] pad_wic_int_vld;
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wire [31:0] pending_clr;
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wire pulse_int;
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wire [3 :0] stim_vic_int;
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wire [3 :0] tim1_vic_int;
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wire [3 :0] tim_vic_int;
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wire uart0_vic_int;
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wire vec_int;
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wire [31:0] wic_awake_en;
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wire wic_clk;
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// &Force("nonport","ctim_int_vld"); @30
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// &Force("nonport","pad_vic_int_cfg"); @31
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assign ctim_int_vld = 0;
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// //&Force("bus", "biu_pad_psr", 31, 0); @34
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// &Force("nonport","pad_wic_int_cfg"); @35
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assign vec_int = 1'b0;
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assign int_ack_vec[4:0] = 5'b0;
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always @( int_ack_vec[4:0])
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begin
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case(int_ack_vec[4:0])
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5'd0 : arb_int_ack[31:0] = 32'b00000000000000000000000000000001;
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5'd1 : arb_int_ack[31:0] = 32'b00000000000000000000000000000010;
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5'd2 : arb_int_ack[31:0] = 32'b00000000000000000000000000000100;
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5'd3 : arb_int_ack[31:0] = 32'b00000000000000000000000000001000;
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5'd4 : arb_int_ack[31:0] = 32'b00000000000000000000000000010000;
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5'd5 : arb_int_ack[31:0] = 32'b00000000000000000000000000100000;
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5'd6 : arb_int_ack[31:0] = 32'b00000000000000000000000001000000;
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5'd7 : arb_int_ack[31:0] = 32'b00000000000000000000000010000000;
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5'd8 : arb_int_ack[31:0] = 32'b00000000000000000000000100000000;
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5'd9 : arb_int_ack[31:0] = 32'b00000000000000000000001000000000;
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5'd10 : arb_int_ack[31:0] = 32'b00000000000000000000010000000000;
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5'd11 : arb_int_ack[31:0] = 32'b00000000000000000000100000000000;
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5'd12 : arb_int_ack[31:0] = 32'b00000000000000000001000000000000;
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5'd13 : arb_int_ack[31:0] = 32'b00000000000000000010000000000000;
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5'd14 : arb_int_ack[31:0] = 32'b00000000000000000100000000000000;
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5'd15 : arb_int_ack[31:0] = 32'b00000000000000001000000000000000;
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5'd16 : arb_int_ack[31:0] = 32'b00000000000000010000000000000000;
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5'd17 : arb_int_ack[31:0] = 32'b00000000000000100000000000000000;
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5'd18 : arb_int_ack[31:0] = 32'b00000000000001000000000000000000;
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5'd19 : arb_int_ack[31:0] = 32'b00000000000010000000000000000000;
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5'd20 : arb_int_ack[31:0] = 32'b00000000000100000000000000000000;
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5'd21 : arb_int_ack[31:0] = 32'b00000000001000000000000000000000;
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5'd22 : arb_int_ack[31:0] = 32'b00000000010000000000000000000000;
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5'd23 : arb_int_ack[31:0] = 32'b00000000100000000000000000000000;
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5'd24 : arb_int_ack[31:0] = 32'b00000001000000000000000000000000;
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5'd25 : arb_int_ack[31:0] = 32'b00000010000000000000000000000000;
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5'd26 : arb_int_ack[31:0] = 32'b00000100000000000000000000000000;
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5'd27 : arb_int_ack[31:0] = 32'b00001000000000000000000000000000;
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5'd28 : arb_int_ack[31:0] = 32'b00010000000000000000000000000000;
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5'd29 : arb_int_ack[31:0] = 32'b00100000000000000000000000000000;
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5'd30 : arb_int_ack[31:0] = 32'b01000000000000000000000000000000;
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5'd31 : arb_int_ack[31:0] = 32'b10000000000000000000000000000000;
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default: arb_int_ack[31:0] = 32'bx;
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endcase
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end
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assign arb_int_ack_clr[31:0] = vec_int ? arb_int_ack[31:0] : 32'b0;
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always@(posedge wic_clk or negedge pad_cpu_rst_b)
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begin
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if(!pad_cpu_rst_b)
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arb_int_ack_ff[31:0] <= 32'b0;
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else
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arb_int_ack_ff[31:0] <= arb_int_ack_clr[31:0];
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end
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// &Force("nonport", "arb_int_ack"); @92
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// &Force("nonport", "arb_int_ack_ff"); @93
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assign pending_clr[31:0] = arb_int_ack_clr[31:0] & ~arb_int_ack_ff[31:0];
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//----------------------------------------------------------
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// instantiate wic
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//-------------------------------------------------------------------------
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// &Force("nonport", "wic_awake_en"); @120
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// &Force("nonport", "wic_awake_en"); @125
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// &Instance("wic_awake_en_64", "x_wic_awake_en"); @130
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// &Connect(.awake_enable (vic_wic_awake_enable ), @132
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// .awake_disable (vic_wic_awake_disable ), @133
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// .awake_data (vic_wic_awake_data[63:0] ), @134
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// .int_exit (vic_wic_int_exit[63:0] ), @135
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// .pending_set (vic_wic_pending_set[63:0]), @136
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// .pending_clr (vic_wic_pending_clr[63:0]), @137
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// .int_vld (pad_wic_int_vld[63:0] ), @138
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// .int_cfg (pad_wic_int_cfg[63:0] ), @139
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// .wic_awake_en (wic_awake_en[63:0] ), @140
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// .int_pending (int_pending[63:0] ) @141
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// ); @142
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// &Connect(.awake_enable (1'b0 ), @144
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// .awake_disable (1'b0 ), @145
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// .awake_data (64'b0 ), @146
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// .int_exit (64'hffffffff_ffffffff ), @147
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// .pending_set (64'b0 ), @148
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// // .pending_clr (32'b0 ), @149
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// .int_vld (pad_wic_int_vld[63:0] ), @150
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// .int_cfg (pad_wic_int_cfg[63:0] ), @151
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// .wic_awake_en (wic_awake_en[63:0] ), @152
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// .int_pending (int_pending[63:0] ) @153
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// ); @154
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assign pad_wic_int_vld[31:0] = {6'b0,tim1_vic_int[3:0],nmi_wake_int_higher[1:0],pulse_int,stim_vic_int[3:0],gpio_vic_int[7:0],1'b0,
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tim_vic_int[3:0],ctim_int_vld,uart0_vic_int};
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assign pad_wic_int_cfg[31:0] = {12'b0,1'b1,19'b0};
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assign intraw_vld =|(int_pending[31:0] & ctl_xx_awake_enable[31:0]);
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assign pad_vic_int_vld[31:0] = int_pending[31:0];
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assign pad_vic_int_cfg[31:0] = 32'b0;
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// &Force("nonport", "wic_awake_en"); @172
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// &Instance("wic_awake_en_32", "x_wic_awake_en"); @176
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wic_awake_en_32 x_wic_awake_en (
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.awake_data (32'b0 ),
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.awake_disable (1'b0 ),
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.awake_enable (1'b0 ),
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.int_cfg (pad_wic_int_cfg[31:0]),
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.int_exit (32'hffffffff ),
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.int_pending (int_pending[31:0] ),
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.int_vld (pad_wic_int_vld[31:0]),
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.pad_cpu_rst_b (pad_cpu_rst_b ),
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.pending_clr (pending_clr ),
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.wic_awake_en (wic_awake_en[31:0] ),
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.wic_clk (wic_clk )
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);
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// &Connect(.awake_enable (vic_wic_awake_enable ), @178
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// .awake_disable (vic_wic_awake_disable ), @179
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// .awake_data (vic_wic_awake_data[31:0] ), @180
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// .int_exit (vic_wic_int_exit[31:0] ), @181
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// .pending_set (vic_wic_pending_set[31:0]), @182
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// .pending_clr (vic_wic_pending_clr[31:0]), @183
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// .int_vld (pad_wic_int_vld[31:0] ), @184
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// .int_cfg (pad_wic_int_cfg[31:0] ), @185
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// .wic_awake_en (wic_awake_en[31:0] ), @186
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// .int_pending (int_pending[31:0] ) @187
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// ); @188
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// &Connect(.awake_enable (1'b0 ), @190
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// .awake_disable (1'b0 ), @191
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// .awake_data (32'b0 ), @192
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// .int_exit (32'hffffffff ), @193
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// .pending_set (32'b0 ), @194
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// // .pending_clr (32'b0 ), @195
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// .int_vld (pad_wic_int_vld[31:0] ), @196
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// .int_cfg (pad_wic_int_cfg[31:0] ), @197
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// .wic_awake_en (wic_awake_en[31:0] ), @198
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// .int_pending (int_pending[31:0] ) @199
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// ); @200
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// &Force("nonport", "wic_awake_en"); @217
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// &Instance("wic_awake_en_16", "x_wic_awake_en"); @221
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// &Connect(.awake_enable (vic_wic_awake_enable ), @223
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// .awake_disable (vic_wic_awake_disable ), @224
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// .awake_data (vic_wic_awake_data[15:0] ), @225
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// .int_exit (vic_wic_int_exit[15:0] ), @226
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// .pending_set (vic_wic_pending_set[15:0]), @227
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// .pending_clr (vic_wic_pending_clr[15:0]), @228
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// .int_vld (pad_wic_int_vld[15:0] ), @229
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// .int_cfg (pad_wic_int_cfg[15:0] ), @230
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// .wic_awake_en (wic_awake_en[15:0] ), @231
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// .int_pending (int_pending[15:0] ) @232
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// ); @233
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// &Connect(.awake_enable (1'b0 ), @235
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// .awake_disable (1'b0 ), @236
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// .awake_data (16'b0 ), @237
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// .int_exit (16'hffff ), @238
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// .pending_set (16'b0 ), @239
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// // .pending_clr (32'b0 ), @240
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// .int_vld (pad_wic_int_vld[15:0] ), @241
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// .int_cfg (pad_wic_int_cfg[15:0] ), @242
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// .wic_awake_en (wic_awake_en[15:0] ), @243
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// .int_pending (int_pending[15:0] ) @244
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// ); @245
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// &Force("nonport", "wic_awake_en"); @263
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// &Instance("wic_awake_en_8", "x_wic_awake_en"); @267
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// &Connect(.awake_enable (vic_wic_awake_enable ), @269
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// .awake_disable (vic_wic_awake_disable ), @270
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// .awake_data (vic_wic_awake_data[7:0] ), @271
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// .int_exit (vic_wic_int_exit[7:0] ), @272
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// .pending_set (vic_wic_pending_set[7:0]), @273
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// .pending_clr (vic_wic_pending_clr[7:0]), @274
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// .int_vld (pad_wic_int_vld[7:0] ), @275
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// .int_cfg (pad_wic_int_cfg[7:0] ), @276
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// .wic_awake_en (wic_awake_en[7:0] ), @277
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// .int_pending (int_pending[7:0] ) @278
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// ); @279
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// &Connect(.awake_enable (1'b0 ), @281
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// .awake_disable (1'b0 ), @282
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// .awake_data (8'b0 ), @283
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// .int_exit (8'hff ), @284
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// .pending_set (8'b0 ), @285
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// // .pending_clr (32'b0 ), @286
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// .int_vld (pad_wic_int_vld[7:0] ), @287
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// .int_cfg (pad_wic_int_cfg[7:0] ), @288
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// .wic_awake_en (wic_awake_en[7:0] ), @289
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// .int_pending (int_pending[7:0] ) @290
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// ); @291
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// &ModuleEnd; @295
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endmodule
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