171 lines
5.4 KiB
Systemverilog
171 lines
5.4 KiB
Systemverilog
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// This is an automatically generated file by joseph.rahmeh on Tue Oct 15 13:13:16 PDT 2019
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//
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// cmd: swerv -snapshot=default -ahb_lite
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//
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`define RV_INST_ACCESS_MASK5 'hffffffff
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`define RV_DATA_ACCESS_ENABLE4 1'h0
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`define RV_INST_ACCESS_ENABLE3 1'h0
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`define RV_INST_ACCESS_ENABLE0 1'h0
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`define RV_INST_ACCESS_MASK3 'hffffffff
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`define RV_DATA_ACCESS_ENABLE5 1'h0
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`define RV_DATA_ACCESS_MASK5 'hffffffff
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`define RV_DATA_ACCESS_ADDR3 'h00000000
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`define RV_INST_ACCESS_ENABLE7 1'h0
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`define RV_DATA_ACCESS_ADDR6 'h00000000
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`define RV_INST_ACCESS_MASK7 'hffffffff
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`define RV_INST_ACCESS_ENABLE6 1'h0
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`define RV_INST_ACCESS_ENABLE5 1'h0
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`define RV_DATA_ACCESS_ADDR4 'h00000000
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`define RV_DATA_ACCESS_ADDR7 'h00000000
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`define RV_DATA_ACCESS_MASK3 'hffffffff
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`define RV_INST_ACCESS_MASK4 'hffffffff
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`define RV_DATA_ACCESS_ADDR1 'h00000000
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`define RV_INST_ACCESS_ADDR4 'h00000000
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`define RV_INST_ACCESS_ADDR3 'h00000000
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`define RV_DATA_ACCESS_ENABLE1 1'h0
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`define RV_DATA_ACCESS_ADDR0 'h00000000
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`define RV_DATA_ACCESS_MASK0 'hffffffff
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`define RV_DATA_ACCESS_MASK6 'hffffffff
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`define RV_INST_ACCESS_ADDR7 'h00000000
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`define RV_INST_ACCESS_MASK0 'hffffffff
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`define RV_DATA_ACCESS_ADDR5 'h00000000
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`define RV_DATA_ACCESS_ADDR2 'h00000000
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`define RV_DATA_ACCESS_MASK4 'hffffffff
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`define RV_DATA_ACCESS_MASK1 'hffffffff
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`define RV_INST_ACCESS_ADDR0 'h00000000
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`define RV_INST_ACCESS_ADDR2 'h00000000
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`define RV_DATA_ACCESS_ENABLE0 1'h0
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`define RV_DATA_ACCESS_ENABLE2 1'h0
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`define RV_DATA_ACCESS_ENABLE7 1'h0
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`define RV_INST_ACCESS_ENABLE4 1'h0
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`define RV_DATA_ACCESS_MASK7 'hffffffff
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`define RV_INST_ACCESS_ADDR5 'h00000000
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`define RV_INST_ACCESS_ENABLE1 1'h0
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`define RV_DATA_ACCESS_MASK2 'hffffffff
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`define RV_INST_ACCESS_MASK6 'hffffffff
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`define RV_DATA_ACCESS_ENABLE3 1'h0
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`define RV_INST_ACCESS_ADDR6 'h00000000
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`define RV_INST_ACCESS_MASK2 'hffffffff
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`define RV_INST_ACCESS_ENABLE2 1'h0
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`define RV_DATA_ACCESS_ENABLE6 1'h0
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`define RV_INST_ACCESS_ADDR1 'h00000000
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`define RV_INST_ACCESS_MASK1 'hffffffff
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`define RV_DEC_INSTBUF_DEPTH 4
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`define RV_DMA_BUF_DEPTH 4
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`define RV_LSU_NUM_NBLOAD 8
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`define RV_LSU_STBUF_DEPTH 8
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`define RV_LSU_NUM_NBLOAD_WIDTH 3
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`define RV_IFU_BUS_TAG 3
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`define RV_LSU_BUS_TAG 4
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`define RV_SB_BUS_TAG 1
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`define RV_DMA_BUS_TAG 1
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`define RV_DCCM_WIDTH_BITS 2
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`define RV_DCCM_REGION 4'hf
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`define RV_DCCM_RESERVED 'h1000
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`define RV_DCCM_SIZE 64
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`define RV_DCCM_DATA_WIDTH 32
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`define RV_DCCM_NUM_BANKS_8
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`define RV_DCCM_FDATA_WIDTH 39
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`define RV_DCCM_BYTE_WIDTH 4
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`define RV_DCCM_DATA_CELL ram_2048x39
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`define RV_DCCM_ENABLE 1
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`define RV_DCCM_BITS 16
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`define RV_DCCM_OFFSET 28'h40000
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`define RV_DCCM_ECC_WIDTH 7
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`define RV_DCCM_SIZE_64
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`define RV_DCCM_ROWS 2048
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`define RV_DCCM_BANK_BITS 3
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`define RV_DCCM_NUM_BANKS 8
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`define RV_DCCM_INDEX_BITS 11
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`define RV_LSU_SB_BITS 16
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`define RV_DCCM_EADR 32'hf004ffff
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`define RV_DCCM_SADR 32'hf0040000
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`define RV_RESET_VEC 'h80000000
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`define RV_RET_STACK_SIZE 4
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`define RV_XLEN 32
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`define RV_TARGET default
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`define RV_BTB_BTAG_FOLD 1
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`define RV_BTB_INDEX3_HI 9
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`define RV_BTB_INDEX1_LO 4
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`define RV_BTB_ADDR_HI 5
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`define RV_BTB_ADDR_LO 4
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`define RV_BTB_INDEX1_HI 5
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`define RV_BTB_INDEX2_HI 7
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`define RV_BTB_INDEX2_LO 6
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`define RV_BTB_ARRAY_DEPTH 4
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`define RV_BTB_BTAG_SIZE 9
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`define RV_BTB_SIZE 32
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`define RV_BTB_INDEX3_LO 8
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`define RV_ICCM_NUM_BANKS 8
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`define RV_ICCM_BITS 19
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`define RV_ICCM_BANK_BITS 3
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`define RV_ICCM_ROWS 16384
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`define RV_ICCM_OFFSET 10'he000000
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`define RV_ICCM_REGION 4'he
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`define RV_ICCM_SADR 32'hee000000
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`define RV_ICCM_RESERVED 'h1000
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`define RV_ICCM_DATA_CELL ram_16384x39
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`define RV_ICCM_INDEX_BITS 14
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`define RV_ICCM_NUM_BANKS_8
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`define RV_ICCM_SIZE 512
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`define RV_ICCM_EADR 32'hee07ffff
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`define RV_ICCM_SIZE_512
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`define RV_ICACHE_SIZE 16
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`define RV_ICACHE_TAG_HIGH 12
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`define RV_ICACHE_IC_ROWS 256
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`define RV_ICACHE_TADDR_HIGH 5
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`define RV_ICACHE_TAG_LOW 6
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`define RV_ICACHE_TAG_CELL ram_64x21
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`define RV_ICACHE_IC_DEPTH 8
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`define RV_ICACHE_IC_INDEX 8
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`define RV_ICACHE_ENABLE 1
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`define RV_ICACHE_DATA_CELL ram_256x34
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`define RV_ICACHE_TAG_DEPTH 64
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`define RV_EXTERNAL_PROG 'hb0000000
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`define RV_EXTERNAL_DATA_1 'h00000000
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`define RV_DEBUG_SB_MEM 'hb0580000
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`define RV_EXTERNAL_DATA 'hc0580000
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`define RV_SERIALIO 'hd0580000
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`define RV_NMI_VEC 'h11110000
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`define RV_BHT_HASH_STRING {ghr[3:2] ^ {ghr[3+1], {4-1-2{1'b0} } },hashin[5:4]^ghr[2-1:0]}
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`define RV_BHT_ADDR_HI 7
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`define RV_BHT_GHR_RANGE 4:0
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`define RV_BHT_GHR_SIZE 5
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`define RV_BHT_GHR_PAD2 fghr[4:3],2'b0
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`define RV_BHT_SIZE 128
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`define RV_BHT_ADDR_LO 4
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`define RV_BHT_ARRAY_DEPTH 16
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`define RV_BHT_GHR_PAD fghr[4],3'b0
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`define RV_NUMIREGS 32
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`define RV_PIC_BITS 15
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`define RV_PIC_REGION 4'hf
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`define RV_PIC_INT_WORDS 1
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`define RV_PIC_TOTAL_INT_PLUS1 9
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`define RV_PIC_MEIP_OFFSET 'h1000
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`define RV_PIC_BASE_ADDR 32'hf00c0000
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`define RV_PIC_MEIGWCTRL_OFFSET 'h4000
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`define RV_PIC_MEIPL_OFFSET 'h0000
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`define RV_PIC_TOTAL_INT 8
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`define RV_PIC_SIZE 32
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`define RV_PIC_MEIE_OFFSET 'h2000
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`define RV_PIC_OFFSET 10'hc0000
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`define RV_PIC_MEIPT_OFFSET 'h3004
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`define RV_PIC_MPICCFG_OFFSET 'h3000
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`define RV_PIC_MEIGWCLR_OFFSET 'h5000
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`define CLOCK_PERIOD 100
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`define CPU_TOP `RV_TOP.swerv
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`define TOP tb_top
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`define RV_BUILD_AHB_LITE 1
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`define RV_TOP `TOP.rvtop
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`define DATAWIDTH 64
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`define RV_STERR_ROLLBACK 0
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`define RV_EXT_ADDRWIDTH 32
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`define RV_EXT_DATAWIDTH 64
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`define SDVT_AHB 1
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`define RV_LDERR_ROLLBACK 1
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`define ASSERT_ON
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`define TEC_RV_ICG clockhdr
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`define REGWIDTH 32
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`undef ASSERT_ON
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