391 lines
22 KiB
Systemverilog
391 lines
22 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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//
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// Function: Top level file for load store unit
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// Comments:
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//
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//
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// DC1 -> DC2 -> DC3 -> DC4 (Commit)
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//
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//********************************************************************************
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module lsu
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import swerv_types::*;
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(
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input logic [31:0] i0_result_e4_eff, // I0 e4 result for e4 -> dc3 store forwarding
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input logic [31:0] i1_result_e4_eff, // I1 e4 result for e4 -> dc3 store forwarding
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input logic [31:0] i0_result_e2, // I0 e2 result for e2 -> dc2 store forwarding
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input logic flush_final_e3, // I0/I1 flush in e3
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input logic i0_flush_final_e3, // I0 flush in e3
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input logic dec_tlu_flush_lower_wb, // I0/I1 writeback flush. This is used to flush the old packets only
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input logic dec_tlu_i0_kill_writeb_wb, // I0 is flushed, don't writeback any results to arch state
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input logic dec_tlu_i1_kill_writeb_wb, // I1 is flushed, don't writeback any results to arch state
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input logic dec_tlu_cancel_e4, // cancel the bus load in dc4 and reset the freeze
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// chicken signals
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input logic dec_tlu_non_blocking_disable, // disable the non block
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input logic dec_tlu_wb_coalescing_disable, // disable the write buffer coalesce
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input logic dec_tlu_ld_miss_byp_wb_disable, // disable the miss bypass in the write buffer
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input logic dec_tlu_sideeffect_posted_disable, // disable posted writes to sideeffect addr to the bus
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input logic dec_tlu_core_ecc_disable, // disable the generation of the ecc
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input logic [31:0] exu_lsu_rs1_d, // address rs operand
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input logic [31:0] exu_lsu_rs2_d, // store data
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input logic [11:0] dec_lsu_offset_d, // address offset operand
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input lsu_pkt_t lsu_p, // lsu control packet
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input logic dec_i0_lsu_decode_d, // lsu is in i0
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input logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control
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output logic [31:0] lsu_result_dc3, // lsu load data
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output logic [31:0] lsu_result_corr_dc4, // This is the ECC corrected data going to RF
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output logic lsu_freeze_dc3, // lsu freeze due to load to external
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output logic lsu_load_stall_any, // This is for blocking loads in the decode
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output logic lsu_store_stall_any, // This is for blocking stores in the decode
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output logic lsu_idle_any, // lsu buffers are empty and no instruction in the pipeline
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output logic lsu_halt_idle_any, // This is used to enter halt mode. Exclude DMA
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output lsu_error_pkt_t lsu_error_pkt_dc3, // lsu exception packet
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output logic lsu_freeze_external_ints_dc3, // freeze due to sideeffects loads need to suppress external interrupt
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output logic lsu_imprecise_error_load_any, // bus load imprecise error
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output logic lsu_imprecise_error_store_any, // bus store imprecise error
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output logic [31:0] lsu_imprecise_error_addr_any, // bus store imprecise error address
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// Non-blocking loads
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input logic dec_nonblock_load_freeze_dc2, //
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output logic lsu_nonblock_load_valid_dc3, // there is an external load -> put in the cam
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output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc3, // the tag of the external non block load
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output logic lsu_nonblock_load_inv_dc5, // invalidate signal for the cam entry for non block loads
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output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_dc5, // tag of the enrty which needs to be invalidated
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output logic lsu_nonblock_load_data_valid, // the non block is valid - sending information back to the cam
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output logic lsu_nonblock_load_data_error, // non block load has an error
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output logic [`RV_LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error
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output logic [31:0] lsu_nonblock_load_data, // Data of the non block load
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output logic lsu_pmu_misaligned_dc3, // PMU : misaligned
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output logic lsu_pmu_bus_trxn, // PMU : bus transaction
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output logic lsu_pmu_bus_misaligned, // PMU : misaligned access going to the bus
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output logic lsu_pmu_bus_error, // PMU : bus sending error back
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output logic lsu_pmu_bus_busy, // PMU : bus is not ready
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// Trigger signals
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input trigger_pkt_t [3:0] trigger_pkt_any, // Trigger info from the decode
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output logic [3:0] lsu_trigger_match_dc3, // lsu trigger hit (one bit per trigger)
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// DCCM ports
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output logic dccm_wren, // DCCM write enable
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output logic dccm_rden, // DCCM read enable
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output logic [`RV_DCCM_BITS-1:0] dccm_wr_addr, // DCCM write address (write can happen to one bank only)
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output logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_lo, // DCCM read address low bank
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output logic [`RV_DCCM_BITS-1:0] dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
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output logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_wr_data, // DCCM write data (this is always aligned)
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input logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // DCCM read data low bank
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input logic [`RV_DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // DCCM read data hi bank
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// PIC ports
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output logic picm_wren, // PIC memory write enable
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output logic picm_rden, // PIC memory read enable
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output logic picm_mken, // Need to read the mask for stores to determine which bits to write/forward
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output logic [31:0] picm_addr, // PIC memory address
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output logic [31:0] picm_wr_data, // PIC memory write data
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input logic [31:0] picm_rd_data, // PIC memory read/mask data
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// AXI Write Channels
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output logic lsu_axi_awvalid,
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input logic lsu_axi_awready,
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output logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid,
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output logic [31:0] lsu_axi_awaddr,
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output logic [3:0] lsu_axi_awregion,
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output logic [7:0] lsu_axi_awlen,
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output logic [2:0] lsu_axi_awsize,
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output logic [1:0] lsu_axi_awburst,
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output logic lsu_axi_awlock,
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output logic [3:0] lsu_axi_awcache,
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output logic [2:0] lsu_axi_awprot,
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output logic [3:0] lsu_axi_awqos,
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output logic lsu_axi_wvalid,
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input logic lsu_axi_wready,
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output logic [63:0] lsu_axi_wdata,
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output logic [7:0] lsu_axi_wstrb,
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output logic lsu_axi_wlast,
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input logic lsu_axi_bvalid,
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output logic lsu_axi_bready,
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input logic [1:0] lsu_axi_bresp,
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input logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_bid,
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// AXI Read Channels
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output logic lsu_axi_arvalid,
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input logic lsu_axi_arready,
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output logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_arid,
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output logic [31:0] lsu_axi_araddr,
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output logic [3:0] lsu_axi_arregion,
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output logic [7:0] lsu_axi_arlen,
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output logic [2:0] lsu_axi_arsize,
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output logic [1:0] lsu_axi_arburst,
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output logic lsu_axi_arlock,
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output logic [3:0] lsu_axi_arcache,
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output logic [2:0] lsu_axi_arprot,
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output logic [3:0] lsu_axi_arqos,
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input logic lsu_axi_rvalid,
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output logic lsu_axi_rready,
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input logic [`RV_LSU_BUS_TAG-1:0] lsu_axi_rid,
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input logic [63:0] lsu_axi_rdata,
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input logic [1:0] lsu_axi_rresp,
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input logic lsu_axi_rlast,
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input logic lsu_bus_clk_en, // external drives a clock_en to control bus ratio
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// DMA slave
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input logic dma_dccm_req, // DMA read/write to dccm
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input logic [31:0] dma_mem_addr, // DMA address
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input logic [2:0] dma_mem_sz, // DMA access size
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input logic dma_mem_write, // DMA access is a write
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input logic [63:0] dma_mem_wdata, // DMA write data
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output logic dccm_dma_rvalid, // lsu data valid for DMA dccm read
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output logic dccm_dma_ecc_error, // DMA load had ecc error
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output logic [63:0] dccm_dma_rdata, // lsu data for DMA dccm read
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output logic dccm_ready, // lsu ready for DMA access
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input logic clk_override, // Disable clock gating
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input logic scan_mode, // scan
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input logic clk,
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input logic free_clk,
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input logic rst_l
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);
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`include "global.h"
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logic lsu_dccm_rden_dc3;
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logic [63:0] store_data_dc2;
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logic [63:0] store_data_dc3;
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logic [31:0] store_data_dc4;
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logic [31:0] store_data_dc5;
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logic [31:0] store_ecc_datafn_hi_dc3;
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logic [31:0] store_ecc_datafn_lo_dc3;
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logic single_ecc_error_hi_dc3, single_ecc_error_lo_dc3;
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logic lsu_single_ecc_error_dc3, lsu_single_ecc_error_dc4, lsu_single_ecc_error_dc5;
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logic lsu_double_ecc_error_dc3;
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logic [31:0] dccm_data_hi_dc3;
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logic [31:0] dccm_data_lo_dc3;
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logic [6:0] dccm_data_ecc_hi_dc3;
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logic [6:0] dccm_data_ecc_lo_dc3;
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logic [31:0] lsu_ld_data_dc3;
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logic [31:0] lsu_ld_data_corr_dc3;
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logic [31:0] picm_mask_data_dc3;
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logic [31:0] lsu_addr_dc1, lsu_addr_dc2, lsu_addr_dc3, lsu_addr_dc4, lsu_addr_dc5;
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logic [31:0] end_addr_dc1, end_addr_dc2, end_addr_dc3, end_addr_dc4, end_addr_dc5;
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lsu_pkt_t lsu_pkt_dc1, lsu_pkt_dc2, lsu_pkt_dc3, lsu_pkt_dc4, lsu_pkt_dc5;
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logic lsu_i0_valid_dc1, lsu_i0_valid_dc2, lsu_i0_valid_dc3, lsu_i0_valid_dc4, lsu_i0_valid_dc5;
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// Store Buffer signals
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logic isldst_dc1, dccm_ldst_dc2, dccm_ldst_dc3;
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logic store_stbuf_reqvld_dc3;
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logic load_stbuf_reqvld_dc3;
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logic ldst_stbuf_reqvld_dc3;
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logic lsu_commit_dc5;
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logic lsu_exc_dc2;
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logic addr_in_dccm_dc1, addr_in_dccm_dc2, addr_in_dccm_dc3;
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logic addr_in_pic_dc1, addr_in_pic_dc2, addr_in_pic_dc3;
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logic addr_external_dc2, addr_external_dc3, addr_external_dc4, addr_external_dc5;
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logic stbuf_reqvld_any;
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logic stbuf_reqvld_flushed_any;
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logic stbuf_addr_in_pic_any;
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logic [DCCM_BYTE_WIDTH-1:0] stbuf_byteen_any;
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logic [LSU_SB_BITS-1:0] stbuf_addr_any;
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logic [DCCM_DATA_WIDTH-1:0] stbuf_data_any;
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logic [(DCCM_FDATA_WIDTH-DCCM_DATA_WIDTH-1):0] stbuf_ecc_any;
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logic lsu_cmpen_dc2;
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logic [DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_dc3;
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logic [DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_dc3;
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logic [DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_dc3;
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logic [DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_dc3;
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logic lsu_stbuf_commit_any;
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logic lsu_stbuf_empty_any;
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logic lsu_stbuf_nodma_empty_any; // Store Buffer is empty except dma writes
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logic lsu_stbuf_full_any;
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// Bus signals
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logic lsu_busreq_dc5;
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logic lsu_bus_buffer_pend_any;
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logic lsu_bus_buffer_empty_any;
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logic lsu_bus_buffer_full_any;
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logic lsu_busreq_dc2;
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logic [31:0] bus_read_data_dc3;
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logic ld_bus_error_dc3;
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logic [31:0] ld_bus_error_addr_dc3;
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logic flush_dc2_up, flush_dc3, flush_dc4, flush_dc5, flush_prior_dc5;
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logic is_sideeffects_dc2, is_sideeffects_dc3;
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logic ldst_nodma_dc1todc3;
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// Clocks
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logic lsu_c1_dc3_clk, lsu_c1_dc4_clk, lsu_c1_dc5_clk;
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logic lsu_c2_dc3_clk, lsu_c2_dc4_clk, lsu_c2_dc5_clk;
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logic lsu_freeze_c1_dc2_clk, lsu_freeze_c1_dc3_clk;
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logic lsu_freeze_c1_dc1_clken, lsu_freeze_c1_dc2_clken, lsu_freeze_c1_dc3_clken;
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logic lsu_store_c1_dc1_clken, lsu_store_c1_dc2_clken, lsu_store_c1_dc3_clken, lsu_store_c1_dc4_clk, lsu_store_c1_dc5_clk;
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logic lsu_freeze_c2_dc1_clk, lsu_freeze_c2_dc2_clk, lsu_freeze_c2_dc3_clk, lsu_freeze_c2_dc4_clk;
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logic lsu_stbuf_c1_clk;
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logic lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
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logic lsu_dccm_c1_dc3_clk, lsu_pic_c1_dc3_clken;
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logic lsu_busm_clk;
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logic lsu_free_c2_clk;
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lsu_lsc_ctl lsu_lsc_ctl(.*);
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// block stores in decode - for either bus or stbuf reasons
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assign lsu_store_stall_any = lsu_stbuf_full_any | lsu_bus_buffer_full_any;
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assign lsu_load_stall_any = lsu_bus_buffer_full_any;
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// Ready to accept dma trxns
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// There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have ld/st in dc3-dc5 when dma is in dc2
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assign ldst_nodma_dc1todc3 = (lsu_pkt_dc1.valid & ~lsu_pkt_dc1.dma) | (lsu_pkt_dc2.valid & ~lsu_pkt_dc2.dma) | (lsu_pkt_dc3.valid & ~lsu_pkt_dc3.dma);
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assign dccm_ready = ~(lsu_p.valid | lsu_stbuf_full_any | lsu_freeze_dc3 | ldst_nodma_dc1todc3);
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// Generate per cycle flush signals
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assign flush_dc2_up = flush_final_e3 | i0_flush_final_e3 | dec_tlu_flush_lower_wb;
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assign flush_dc3 = (flush_final_e3 & i0_flush_final_e3) | dec_tlu_flush_lower_wb;
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assign flush_dc4 = dec_tlu_flush_lower_wb;
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assign flush_dc5 = (dec_tlu_i0_kill_writeb_wb | (dec_tlu_i1_kill_writeb_wb & ~lsu_i0_valid_dc5));
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assign flush_prior_dc5 = dec_tlu_i0_kill_writeb_wb & ~lsu_i0_valid_dc5; // Flush is due to i0 instruction and ld/st is in i1
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// lsu idle
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assign lsu_idle_any = ~(lsu_pkt_dc1.valid | lsu_pkt_dc2.valid | lsu_pkt_dc3.valid | lsu_pkt_dc4.valid | lsu_pkt_dc5.valid) &
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lsu_bus_buffer_empty_any & lsu_stbuf_empty_any;
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// lsu halt idle. This is used for entering the halt mode
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// Indicates non-idle if there is a instruction valid in dc1-dc5 or read/write buffers are non-empty since they can come with error
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// Need to make sure bus trxns are done and there are no non-dma writes in store buffer
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assign lsu_halt_idle_any = ~((lsu_pkt_dc1.valid & ~lsu_pkt_dc1.dma) |
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(lsu_pkt_dc2.valid & ~lsu_pkt_dc2.dma) |
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(lsu_pkt_dc3.valid & ~lsu_pkt_dc3.dma) |
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(lsu_pkt_dc4.valid & ~lsu_pkt_dc4.dma) |
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(lsu_pkt_dc5.valid & ~lsu_pkt_dc5.dma)) &
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lsu_bus_buffer_empty_any & lsu_stbuf_nodma_empty_any;
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// Instantiate the store buffer
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//assign ldst_stbuf_reqvld_dc3 = store_stbuf_reqvld_dc3 | load_stbuf_reqvld_dc3;
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assign store_stbuf_reqvld_dc3 = lsu_pkt_dc3.valid & lsu_pkt_dc3.store & (addr_in_dccm_dc3 | addr_in_pic_dc3) & (~flush_dc3 | lsu_pkt_dc3.dma) & ~lsu_freeze_dc3;
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assign load_stbuf_reqvld_dc3 = lsu_pkt_dc3.valid & lsu_pkt_dc3.load & (addr_in_dccm_dc3 | addr_in_pic_dc3) & lsu_single_ecc_error_dc3 & (~flush_dc3 | lsu_pkt_dc3.dma) & ~lsu_freeze_dc3;
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// These go to store buffer to detect full
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assign isldst_dc1 = lsu_pkt_dc1.valid & (lsu_pkt_dc1.load | lsu_pkt_dc1.store);
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assign dccm_ldst_dc2 = lsu_pkt_dc2.valid & (lsu_pkt_dc2.load | lsu_pkt_dc2.store) & (addr_in_dccm_dc2 | addr_in_pic_dc2);
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assign dccm_ldst_dc3 = lsu_pkt_dc3.valid & (lsu_pkt_dc3.load | lsu_pkt_dc3.store) & (addr_in_dccm_dc3 | addr_in_pic_dc3);
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// Disable Forwarding for now
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assign lsu_cmpen_dc2 = lsu_pkt_dc2.valid & (lsu_pkt_dc2.load | lsu_pkt_dc2.store) & (addr_in_dccm_dc2 | addr_in_pic_dc2);
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// Bus signals
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assign lsu_busreq_dc2 = lsu_pkt_dc2.valid & (lsu_pkt_dc2.load | lsu_pkt_dc2.store) & addr_external_dc2 & ~flush_dc2_up & ~lsu_exc_dc2;
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// PMU signals
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assign lsu_pmu_misaligned_dc3 = lsu_pkt_dc3.valid & ((lsu_pkt_dc3.half & lsu_addr_dc3[0]) | (lsu_pkt_dc3.word & (|lsu_addr_dc3[1:0])));
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lsu_dccm_ctl dccm_ctl (
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.lsu_addr_dc1(lsu_addr_dc1[31:0]),
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.end_addr_dc1(end_addr_dc1[DCCM_BITS-1:0]),
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.lsu_addr_dc3(lsu_addr_dc3[DCCM_BITS-1:0]),
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.*
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);
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lsu_stbuf stbuf(
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.lsu_addr_dc1(lsu_addr_dc1[LSU_SB_BITS-1:0]),
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.end_addr_dc1(end_addr_dc1[LSU_SB_BITS-1:0]),
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.lsu_addr_dc2(lsu_addr_dc2[LSU_SB_BITS-1:0]),
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.end_addr_dc2(end_addr_dc2[LSU_SB_BITS-1:0]),
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.lsu_addr_dc3(lsu_addr_dc3[LSU_SB_BITS-1:0]),
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.end_addr_dc3(end_addr_dc3[LSU_SB_BITS-1:0]),
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.*
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);
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lsu_ecc ecc (
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.lsu_addr_dc3(lsu_addr_dc3[DCCM_BITS-1:0]),
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.end_addr_dc3(end_addr_dc3[DCCM_BITS-1:0]),
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.*
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);
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lsu_trigger trigger (
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.store_data_dc3(store_data_dc3[31:0]),
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.*
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);
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// Clk domain
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lsu_clkdomain clkdomain (.*);
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// Bus interface
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lsu_bus_intf bus_intf (.*);
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//Flops
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//rvdffs #(1) lsu_i0_valid_dc1ff (.*, .din(dec_i0_lsu_decode_d), .dout(lsu_i0_valid_dc1), .en(~lsu_freeze_dc3));
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rvdff #(1) lsu_i0_valid_dc1ff (.*, .din(dec_i0_lsu_decode_d), .dout(lsu_i0_valid_dc1), .clk(lsu_freeze_c2_dc1_clk));
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rvdff #(1) lsu_i0_valid_dc2ff (.*, .din(lsu_i0_valid_dc1), .dout(lsu_i0_valid_dc2), .clk(lsu_freeze_c2_dc2_clk));
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rvdff #(1) lsu_i0_valid_dc3ff (.*, .din(lsu_i0_valid_dc2), .dout(lsu_i0_valid_dc3), .clk(lsu_freeze_c2_dc3_clk));
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rvdff #(1) lsu_i0_valid_dc4ff (.*, .din(lsu_i0_valid_dc3), .dout(lsu_i0_valid_dc4), .clk(lsu_freeze_c2_dc4_clk));
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rvdff #(1) lsu_i0_valid_dc5ff (.*, .din(lsu_i0_valid_dc4), .dout(lsu_i0_valid_dc5), .clk(lsu_c2_dc5_clk));
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rvdff #(1) lsu_single_ecc_err_dc4(.*, .din(lsu_single_ecc_error_dc3), .dout(lsu_single_ecc_error_dc4), .clk(lsu_c2_dc4_clk));
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rvdff #(1) lsu_single_ecc_err_dc5(.*, .din(lsu_single_ecc_error_dc4), .dout(lsu_single_ecc_error_dc5), .clk(lsu_c2_dc5_clk));
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`ifdef ASSERT_ON
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logic [8:0] store_data_bypass_sel;
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assign store_data_bypass_sel[8:0] = {lsu_p.store_data_bypass_c1,
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lsu_p.store_data_bypass_c2,
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lsu_p.store_data_bypass_i0_e2_c2,
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lsu_p.store_data_bypass_e4_c1[1:0],
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lsu_p.store_data_bypass_e4_c2[1:0],
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lsu_p.store_data_bypass_e4_c3[1:0]};
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assert_store_data_bypass_onehot: assert #0 ($onehot0(store_data_bypass_sel[8:0]));
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assert_picm_rden_and_wren: assert #0 ($onehot0({(picm_rden | picm_mken),picm_wren}));
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assert_picm_rden_and_dccmen: assert #0 ($onehot0({(picm_rden | picm_mken),dccm_rden}));
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assert_picm_wren_and_dccmen: assert #0 ($onehot0({picm_wren, dccm_wren}));
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//assert_no_exceptions: assert #0 (lsu_exc_pkt_dc3.exc_valid == 1'b0);
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property exception_no_lsu_flush;
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@(posedge clk) disable iff(~rst_l) lsu_error_pkt_dc3.exc_valid |-> ##[1:2] (flush_dc4 | flush_dc5);
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endproperty
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assert_exception_no_lsu_flush: assert property (exception_no_lsu_flush) else
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$display("No flush within 2 cycles of exception");
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`endif
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|
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endmodule // lsu
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