186 lines
8.2 KiB
Systemverilog
186 lines
8.2 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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//
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// Owner:
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// Function: Top level file for load store unit
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// Comments:
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//
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//
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// DC1 -> DC2 -> DC3 -> DC4 (Commit)
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//
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//********************************************************************************
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module lsu_ecc
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import swerv_types::*;
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(
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input logic lsu_c2_dc4_clk, // clocks
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input logic lsu_c1_dc4_clk,
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input logic lsu_c1_dc5_clk,
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input logic clk,
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input logic rst_l,
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input lsu_pkt_t lsu_pkt_dc3, // packet in dc3
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input logic lsu_dccm_rden_dc3, // dccm rden
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input logic addr_in_dccm_dc3, // address in dccm
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input logic [`RV_DCCM_BITS-1:0] lsu_addr_dc3, // start address
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input logic [`RV_DCCM_BITS-1:0] end_addr_dc3, // end address
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input logic [63:0] store_data_dc3, // store data
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input logic [`RV_DCCM_DATA_WIDTH-1:0] stbuf_data_any,
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input logic [`RV_DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_dc3, // data forward from the store buffer
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input logic [`RV_DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_dc3, // data forward from the store buffer
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input logic [`RV_DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_dc3,// which bytes from the store buffer are on
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input logic [`RV_DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_dc3,// which bytes from the store buffer are on
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input logic [`RV_DCCM_DATA_WIDTH-1:0] dccm_data_hi_dc3, // raw data from mem
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input logic [`RV_DCCM_DATA_WIDTH-1:0] dccm_data_lo_dc3, // raw data from mem
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input logic [`RV_DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_dc3, // ecc read out from mem
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input logic [`RV_DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_dc3, // ecc read out from mem
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input logic dec_tlu_core_ecc_disable, // disables the ecc computation and error flagging
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output logic [`RV_DCCM_DATA_WIDTH-1:0] store_ecc_datafn_hi_dc3, // final store data either from stbuf or SEC DCCM readout
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output logic [`RV_DCCM_DATA_WIDTH-1:0] store_ecc_datafn_lo_dc3,
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output logic [`RV_DCCM_ECC_WIDTH-1:0] stbuf_ecc_any,
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output logic single_ecc_error_hi_dc3, // sec detected
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output logic single_ecc_error_lo_dc3, // sec detected on lower dccm bank
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output logic lsu_single_ecc_error_dc3, // or of the 2
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output logic lsu_double_ecc_error_dc3, // double error detected
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input logic scan_mode
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);
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`include "global.h"
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`ifdef RV_DCCM_ENABLE
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localparam DCCM_ENABLE = 1'b1;
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`else
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localparam DCCM_ENABLE = 1'b0;
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`endif
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logic [DCCM_DATA_WIDTH-1:0] sec_data_hi_dc3;
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logic [DCCM_DATA_WIDTH-1:0] sec_data_lo_dc3;
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logic double_ecc_error_hi_dc3, double_ecc_error_lo_dc3;
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logic ldst_dual_dc3;
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logic is_ldst_dc3;
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logic is_ldst_hi_dc3, is_ldst_lo_dc3;
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logic [7:0] ldst_byteen_dc3;
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logic [7:0] store_byteen_dc3;
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logic [7:0] store_byteen_ext_dc3;
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logic [DCCM_BYTE_WIDTH-1:0] store_byteen_hi_dc3, store_byteen_lo_dc3;
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logic [163:0] store_data_ext_dc3;
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logic [DCCM_DATA_WIDTH-1:0] store_data_hi_dc3, store_data_lo_dc3;
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logic [6:0] ecc_out_hi_nc, ecc_out_lo_nc;
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assign ldst_dual_dc3 = (lsu_addr_dc3[2] != end_addr_dc3[2]);
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assign is_ldst_dc3 = lsu_pkt_dc3.valid & (lsu_pkt_dc3.load | lsu_pkt_dc3.store) & addr_in_dccm_dc3 & lsu_dccm_rden_dc3;
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assign is_ldst_lo_dc3 = is_ldst_dc3 & ~dec_tlu_core_ecc_disable;
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assign is_ldst_hi_dc3 = is_ldst_dc3 & ldst_dual_dc3 & ~dec_tlu_core_ecc_disable;
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assign ldst_byteen_dc3[7:0] = ({8{lsu_pkt_dc3.by}} & 8'b0000_0001) |
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({8{lsu_pkt_dc3.half}} & 8'b0000_0011) |
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({8{lsu_pkt_dc3.word}} & 8'b0000_1111) |
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({8{lsu_pkt_dc3.dword}} & 8'b1111_1111);
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assign store_byteen_dc3[7:0] = ldst_byteen_dc3[7:0] & {8{lsu_pkt_dc3.store}};
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assign store_byteen_ext_dc3[7:0] = store_byteen_dc3[7:0] << lsu_addr_dc3[1:0];
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assign store_byteen_hi_dc3[DCCM_BYTE_WIDTH-1:0] = store_byteen_ext_dc3[7:4];
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assign store_byteen_lo_dc3[DCCM_BYTE_WIDTH-1:0] = store_byteen_ext_dc3[3:0];
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assign store_data_ext_dc3[63:0] = store_data_dc3[63:0] << {lsu_addr_dc3[1:0], 3'b000};
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assign store_data_hi_dc3[DCCM_DATA_WIDTH-1:0] = store_data_ext_dc3[63:32];
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assign store_data_lo_dc3[DCCM_DATA_WIDTH-1:0] = store_data_ext_dc3[31:0];
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// Merge store data and sec data
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// This is used for loads as well for ecc error case. store_byteen will be 0 for loads
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for (genvar i=0; i<DCCM_BYTE_WIDTH; i++) begin
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assign store_ecc_datafn_hi_dc3[(8*i)+7:(8*i)] = store_byteen_hi_dc3[i] ? store_data_hi_dc3[(8*i)+7:(8*i)] :
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(stbuf_fwdbyteen_hi_dc3[i] ? stbuf_fwddata_hi_dc3[(8*i)+7:(8*i)] : sec_data_hi_dc3[(8*i)+7:(8*i)]);
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assign store_ecc_datafn_lo_dc3[(8*i)+7:(8*i)] = store_byteen_lo_dc3[i] ? store_data_lo_dc3[(8*i)+7:(8*i)] :
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(stbuf_fwdbyteen_lo_dc3[i] ? stbuf_fwddata_lo_dc3[(8*i)+7:(8*i)] : sec_data_lo_dc3[(8*i)+7:(8*i)]);
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end
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if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
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//Detect/Repair for Hi/Lo
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rvecc_decode lsu_ecc_decode_hi (
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// Inputs
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.en(is_ldst_hi_dc3),
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.sed_ded (1'b0), // 1 : means only detection
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.din(dccm_data_hi_dc3[DCCM_DATA_WIDTH-1:0]),
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.ecc_in(dccm_data_ecc_hi_dc3[DCCM_ECC_WIDTH-1:0]),
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// Outputs
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.dout(sec_data_hi_dc3[DCCM_DATA_WIDTH-1:0]),
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.ecc_out (ecc_out_hi_nc[6:0]),
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.single_ecc_error(single_ecc_error_hi_dc3),
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.double_ecc_error(double_ecc_error_hi_dc3),
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.*
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);
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rvecc_decode lsu_ecc_decode_lo (
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// Inputs
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.en(is_ldst_lo_dc3),
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.sed_ded (1'b0), // 1 : means only detection
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.din(dccm_data_lo_dc3[DCCM_DATA_WIDTH-1:0] ),
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.ecc_in(dccm_data_ecc_lo_dc3[DCCM_ECC_WIDTH-1:0]),
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// Outputs
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.dout(sec_data_lo_dc3[DCCM_DATA_WIDTH-1:0]),
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.ecc_out (ecc_out_lo_nc[6:0]),
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.single_ecc_error(single_ecc_error_lo_dc3),
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.double_ecc_error(double_ecc_error_lo_dc3),
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.*
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);
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// Generate the ECC bits for store buffer drain
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rvecc_encode lsu_ecc_encode (
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//Inputs
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.din(stbuf_data_any[DCCM_DATA_WIDTH-1:0]),
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//Outputs
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.ecc_out(stbuf_ecc_any[DCCM_ECC_WIDTH-1:0]),
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.*
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);
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end else begin: Gen_dccm_disable // block: Gen_dccm_enable
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assign sec_data_hi_dc3[DCCM_DATA_WIDTH-1:0] = '0;
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assign sec_data_lo_dc3[DCCM_DATA_WIDTH-1:0] = '0;
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assign single_ecc_error_hi_dc3 = '0;
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assign double_ecc_error_hi_dc3 = '0;
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assign single_ecc_error_lo_dc3 = '0;
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assign double_ecc_error_lo_dc3 = '0;
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assign stbuf_ecc_any[DCCM_ECC_WIDTH-1:0] = '0;
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end
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assign lsu_single_ecc_error_dc3 = single_ecc_error_hi_dc3 | single_ecc_error_lo_dc3;
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assign lsu_double_ecc_error_dc3 = double_ecc_error_hi_dc3 | double_ecc_error_lo_dc3;
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`ifdef ASSERT_ON
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// ecc_check: assert property (@(posedge clk) ~(single_ecc_error_lo_dc3 | single_ecc_error_hi_dc3));
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`endif
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endmodule // lsu_ecc
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