167 lines
4.9 KiB
Systemverilog
167 lines
4.9 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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module ahb_sif (
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input logic [63:0] HWDATA,
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input logic HCLK,
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input logic HSEL,
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input logic [3:0] HPROT,
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input logic HWRITE,
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input logic [1:0] HTRANS,
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input logic [2:0] HSIZE,
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input logic HREADY,
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input logic HRESETn,
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input logic [31:0] HADDR,
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input logic [2:0] HBURST,
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output logic HREADYOUT,
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output logic HRESP,
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output logic [63:0] HRDATA
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);
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localparam MEM_SIZE_DW = 8192;
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localparam MAILBOX_ADDR = 32'hD0580000;
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logic Last_HSEL;
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logic NextLast_HSEL;
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logic Last_HWRITE;
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logic [1:0] Last_HTRANS;
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logic [1:0] NextLast_HTRANS;
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logic [31:0] Last_HADDR;
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logic [63:0] Next_HRDATA;
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logic [63:0] WriteReadData;
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logic [63:0] WriteMask;
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bit [7:0] mem [0:MEM_SIZE_DW-1];
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// Wires
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wire [63:0] Next_WriteMask = HSIZE == 3'b000 ? (64'hff << {HADDR[2:0], 3'b000}) : (HSIZE == 3'b001 ? (64'hffff << {HADDR[2], 4'h0}) : (HSIZE == 3'b010 ? (64'hffff_ffff << {HADDR[3],5'h0}) : 64'hffff_ffff_ffff_ffff));
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wire [63:0] MaskedWriteData = HWDATA & WriteMask;
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wire [63:0] MaskedWriteReadData = WriteReadData & ~WriteMask;
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wire [63:0] WriteData = (MaskedWriteData | MaskedWriteReadData );
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wire Write = &{Last_HSEL, Last_HWRITE, Last_HTRANS[1]};
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wire Read = &{ HSEL, ~HWRITE, HTRANS[1]};
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wire mailbox_write = &{Write, Last_HADDR==MAILBOX_ADDR, HRESETn==1};
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wire Next_HWRITE = |{HTRANS} ? HWRITE : Last_HWRITE;
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wire [63:0] mem_dout = {mem[{Last_HADDR[12:3],3'b0}+7],mem[{Last_HADDR[12:3],3'b0}+6],mem[{Last_HADDR[12:3],3'b0}+5],mem[{Last_HADDR[12:3],3'b0}+4],mem[{Last_HADDR[12:3],3'b0}+3],mem[{Last_HADDR[12:3],3'b0}+2],mem[{Last_HADDR[12:3],3'b0}+1],mem[{Last_HADDR[12:3],3'b0}]};
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always @ (posedge HCLK or negedge HRESETn) begin
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if (Write && Last_HADDR == 32'h0) begin
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mem[{Last_HADDR[12:3],3'b0}+7] <= #1 { WriteData[63:56] };
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mem[{Last_HADDR[12:3],3'b0}+6] <= #1 { WriteData[55:48] };
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mem[{Last_HADDR[12:3],3'b0}+5] <= #1 { WriteData[47:40] };
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mem[{Last_HADDR[12:3],3'b0}+4] <= #1 { WriteData[39:32] };
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mem[{Last_HADDR[12:3],3'b0}+3] <= #1 { WriteData[31:24] };
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mem[{Last_HADDR[12:3],3'b0}+2] <= #1 { WriteData[23:16] };
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mem[{Last_HADDR[12:3],3'b0}+1] <= #1 { WriteData[15:08] };
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mem[{Last_HADDR[12:3],3'b0}+0] <= #1 { WriteData[07:00] };
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end
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end
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always @(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) begin
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HREADYOUT <= #1 1'b0 ;
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HRESP <= #1 1'b0;
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end else begin
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HREADYOUT <= #1 |HTRANS;
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HRESP <= #1 1'b0;
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WriteMask <= #1 Next_WriteMask;
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end
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end
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`ifdef VERILATOR
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always @(posedge HCLK or negedge HRESETn) begin
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`else
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always @(negedge HCLK or negedge HRESETn) begin
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`endif
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if(~HRESETn) begin
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Last_HADDR <= #1 32'b0;
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end else begin
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Last_HADDR <= #1 |{HTRANS} ? {HADDR[31:2], 2'b00} : Last_HADDR;
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end
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end
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always @(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) begin
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Last_HWRITE <= #1 1'b0;
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end else begin
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Last_HWRITE <= #1 Next_HWRITE;
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end
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end
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always @(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) begin
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Last_HTRANS <= #1 2'b0;
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end else begin
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Last_HTRANS <= #1 HTRANS;
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end
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end
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always @(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) begin
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Last_HSEL <= #1 1'b0;
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end else begin
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Last_HSEL <= #1 HSEL;
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end
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end
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`ifndef VERILATOR
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always @(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) begin
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HRDATA <= #1 Next_HRDATA ;
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end else begin
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HRDATA <= #1 Next_HRDATA ;
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end
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end
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always @* begin
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Next_HRDATA = mem_dout;
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end
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`else
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always @(posedge HCLK) begin
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Next_HRDATA <= mem_dout;
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end
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assign HRDATA = mem_dout;
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`endif
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always @* begin
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if(Last_HSEL) begin
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WriteReadData[07:00] = mem[{Last_HADDR[12:3],3'b0}];
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WriteReadData[15:08] = mem[{Last_HADDR[12:3],3'b0}+1];
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WriteReadData[23:16] = mem[{Last_HADDR[12:3],3'b0}+2];
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WriteReadData[31:24] = mem[{Last_HADDR[12:3],3'b0}+3];
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WriteReadData[39:32] = mem[{Last_HADDR[12:3],3'b0}+4];
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WriteReadData[47:40] = mem[{Last_HADDR[12:3],3'b0}+5];
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WriteReadData[55:48] = mem[{Last_HADDR[12:3],3'b0}+6];
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WriteReadData[63:56] = mem[{Last_HADDR[12:3],3'b0}+7];
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end
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end
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endmodule
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