407 lines
21 KiB
Systemverilog
407 lines
21 KiB
Systemverilog
//********************************************************************************
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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//********************************************************************************
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// Function: Top level file for Icache, Fetch, Branch prediction & Aligner
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// BFF -> F1 -> F2 -> A
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//********************************************************************************
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module ifu
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import swerv_types::*;
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(
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input logic free_clk,
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input logic active_clk,
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input logic clk,
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input logic clk_override,
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input logic rst_l,
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input logic dec_ib3_valid_d, dec_ib2_valid_d, // mass balance for decode buffer
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input logic dec_ib0_valid_eff_d, // effective valid taking decode into account
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input logic dec_ib1_valid_eff_d, // effective valid taking decode into account
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input logic exu_i0_br_ret_e4, // i0 branch commit is a ret
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input logic exu_i1_br_ret_e4, // i1 branch commit is a ret
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input logic exu_i0_br_call_e4, // i0 branch commit is a call
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input logic exu_i1_br_call_e4, // i1 branch commit is a call
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input logic exu_flush_final, // flush, includes upper and lower
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input logic dec_tlu_flush_err_wb , // flush due to parity error.
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input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final
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input logic dec_tlu_dbg_halted, // halted, used for leaving IDLE state
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input logic dec_tlu_pmu_fw_halted, // Core is halted
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input logic [31:1] exu_flush_path_final, // flush fetch address
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input logic exu_flush_upper_e2, // flush upper, either i0 or i1
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input logic [31:0] dec_tlu_mrac_ff ,// Side_effect , cacheable for each region
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input logic dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final
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input logic dec_tlu_flush_leak_one_wb, // ignore bp for leak one fetches
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input logic dec_tlu_bpred_disable, // disable all branch prediction
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input logic dec_tlu_core_ecc_disable, // disable ecc checking and flagging
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// AXI Write Channels - IFU never writes. So, 0 out mostly
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output logic ifu_axi_awvalid,
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input logic ifu_axi_awready,
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output logic [`RV_IFU_BUS_TAG-1:0] ifu_axi_awid,
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output logic [31:0] ifu_axi_awaddr,
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output logic [3:0] ifu_axi_awregion,
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output logic [7:0] ifu_axi_awlen,
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output logic [2:0] ifu_axi_awsize,
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output logic [1:0] ifu_axi_awburst,
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output logic ifu_axi_awlock,
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output logic [3:0] ifu_axi_awcache,
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output logic [2:0] ifu_axi_awprot,
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output logic [3:0] ifu_axi_awqos,
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output logic ifu_axi_wvalid,
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input logic ifu_axi_wready,
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output logic [63:0] ifu_axi_wdata,
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output logic [7:0] ifu_axi_wstrb,
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output logic ifu_axi_wlast,
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input logic ifu_axi_bvalid,
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output logic ifu_axi_bready,
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input logic [1:0] ifu_axi_bresp,
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input logic [`RV_IFU_BUS_TAG-1:0] ifu_axi_bid,
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// AXI Read Channels
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output logic ifu_axi_arvalid,
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input logic ifu_axi_arready,
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output logic [`RV_IFU_BUS_TAG-1:0] ifu_axi_arid,
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output logic [31:0] ifu_axi_araddr,
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output logic [3:0] ifu_axi_arregion,
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output logic [7:0] ifu_axi_arlen,
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output logic [2:0] ifu_axi_arsize,
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output logic [1:0] ifu_axi_arburst,
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output logic ifu_axi_arlock,
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output logic [3:0] ifu_axi_arcache,
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output logic [2:0] ifu_axi_arprot,
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output logic [3:0] ifu_axi_arqos,
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input logic ifu_axi_rvalid,
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output logic ifu_axi_rready,
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input logic [`RV_IFU_BUS_TAG-1:0] ifu_axi_rid,
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input logic [63:0] ifu_axi_rdata,
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input logic [1:0] ifu_axi_rresp,
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input logic ifu_axi_rlast,
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//// AHB LITE BUS
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//`ifdef RV_BUILD_AHB_LITE
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input logic ifu_bus_clk_en,
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input logic dma_iccm_req,
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input logic dma_iccm_stall_any,
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input logic [31:0] dma_mem_addr,
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input logic [2:0] dma_mem_sz,
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input logic dma_mem_write,
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input logic [63:0] dma_mem_wdata,
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output logic iccm_dma_ecc_error,
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output logic iccm_dma_rvalid,
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output logic [63:0] iccm_dma_rdata,
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output logic iccm_ready,
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//`endif
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output logic [1:0] ifu_pmu_instr_aligned,
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output logic ifu_pmu_align_stall,
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output logic ifu_pmu_fetch_stall,
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// I$ & ITAG Ports
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output logic [31:3] ic_rw_addr, // Read/Write addresss to the Icache.
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output logic [3:0] ic_wr_en, // Icache write enable, when filling the Icache.
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output logic ic_rd_en, // Icache read enable.
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`ifdef RV_ICACHE_ECC
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output logic [83:0] ic_wr_data, // Data to fill to the Icache. With ECC
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input logic [167:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
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input logic [24:0] ictag_debug_rd_data,// Debug icache tag.
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output logic [41:0] ic_debug_wr_data, // Debug wr cache.
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output logic [41:0] ifu_ic_debug_rd_data,
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`else
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output logic [67:0] ic_wr_data, // Data to fill to the Icache. With Parity
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input logic [135:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With Parity
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input logic [20:0] ictag_debug_rd_data,// Debug icache tag.
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output logic [33:0] ic_debug_wr_data, // Debug wr cache.
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output logic [33:0] ifu_ic_debug_rd_data,
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`endif
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output logic [127:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
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output logic ic_sel_premux_data, // Select the premux data.
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output logic [15:2] ic_debug_addr, // Read/Write addresss to the Icache.
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output logic ic_debug_rd_en, // Icache debug rd
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output logic ic_debug_wr_en, // Icache debug wr
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output logic ic_debug_tag_array, // Debug tag array
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output logic [3:0] ic_debug_way, // Debug way. Rd or Wr.
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output logic [3:0] ic_tag_valid, // Valid bits when accessing the Icache. One valid bit per way. F2 stage
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input logic [3:0] ic_rd_hit, // Compare hits from Icache tags. Per way. F2 stage
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input logic ic_tag_perr, // Icache Tag parity error
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`ifdef RV_ICCM_ENABLE
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// ICCM ports
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output logic [`RV_ICCM_BITS-1:2] iccm_rw_addr, // ICCM read/write address.
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output logic iccm_wren, // ICCM write enable (through the DMA)
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output logic iccm_rden, // ICCM read enable.
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output logic [77:0] iccm_wr_data, // ICCM write data.
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output logic [2:0] iccm_wr_size, // ICCM write location within DW.
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input logic [155:0] iccm_rd_data, // Data read from ICCM.
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`endif
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// Perf counter sigs
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output logic ifu_pmu_ic_miss, // ic miss
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output logic ifu_pmu_ic_hit, // ic hit
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output logic ifu_pmu_bus_error, // iside bus error
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output logic ifu_pmu_bus_busy, // iside bus busy
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output logic ifu_pmu_bus_trxn, // iside bus transactions
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output logic ifu_i0_valid, // Instruction 0 valid. From Aligner to Decode
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output logic ifu_i1_valid, // Instruction 1 valid. From Aligner to Decode
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output logic ifu_i0_icaf, // Instruction 0 access fault. From Aligner to Decode
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output logic ifu_i1_icaf, // Instruction 1 access fault. From Aligner to Decode
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output logic ifu_i0_icaf_f1, // Instruction 0 has access fault on second fetch group
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output logic ifu_i1_icaf_f1, // Instruction 1 has access fault on second fetch group
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output logic ifu_i0_perr, // Instruction 0 parity error. From Aligner to Decode
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output logic ifu_i1_perr, // Instruction 1 parity error. From Aligner to Decode
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output logic ifu_i0_sbecc, // Instruction 0 has single bit ecc error
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output logic ifu_i1_sbecc, // Instruction 1 has single bit ecc error
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output logic ifu_i0_dbecc, // Instruction 0 has double bit ecc error
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output logic ifu_i1_dbecc, // Instruction 1 has double bit ecc error
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output logic iccm_dma_sb_error, // Single Bit ECC error from a DMA access
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output logic[31:0] ifu_i0_instr, // Instruction 0 . From Aligner to Decode
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output logic[31:0] ifu_i1_instr, // Instruction 1 . From Aligner to Decode
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output logic[31:1] ifu_i0_pc, // Instruction 0 pc. From Aligner to Decode
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output logic[31:1] ifu_i1_pc, // Instruction 1 pc. From Aligner to Decode
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output logic ifu_i0_pc4, // Instruction 0 is 4 byte. From Aligner to Decode
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output logic ifu_i1_pc4, // Instruction 1 is 4 byte. From Aligner to Decode
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output logic [15:0] ifu_illegal_inst, // Illegal instruction.
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output logic ifu_miss_state_idle, // There is no outstanding miss. Cache miss state is idle.
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output br_pkt_t i0_brp, // Instruction 0 branch packet. From Aligner to Decode
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output br_pkt_t i1_brp, // Instruction 1 branch packet. From Aligner to Decode
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input predict_pkt_t exu_mp_pkt, // mispredict packet
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input logic [`RV_BHT_GHR_RANGE] exu_mp_eghr, // execute ghr
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input br_tlu_pkt_t dec_tlu_br0_wb_pkt, // slot0 update/error pkt
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input br_tlu_pkt_t dec_tlu_br1_wb_pkt, // slot1 update/error pkt
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input dec_tlu_flush_lower_wb,
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input rets_pkt_t exu_rets_e1_pkt, // E1 return stack packet
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input rets_pkt_t exu_rets_e4_pkt, // E4 return stack packet
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// pc's used to maintain and update the BP RET stacks
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`ifdef REAL_COMM_RS
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input logic [31:1] exu_i0_pc_e1,
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input logic [31:1] exu_i1_pc_e1,
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input logic [31:1] dec_tlu_i0_pc_e4,
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input logic [31:1] dec_tlu_i1_pc_e4,
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`endif
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output logic [15:0] ifu_i0_cinst,
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output logic [15:0] ifu_i1_cinst,
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/// Icache debug
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input cache_debug_pkt_t dec_tlu_ic_diag_pkt ,
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output logic ifu_ic_debug_rd_data_valid,
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input logic scan_mode
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);
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localparam TAGWIDTH = 2 ;
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localparam IDWIDTH = 2 ;
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logic ifu_fb_consume1, ifu_fb_consume2;
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logic [31:1] ifc_fetch_addr_f2;
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logic ifc_fetch_uncacheable_f1;
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logic [7:0] ifu_fetch_val; // valids on a 2B boundary, left justified [7] implies valid fetch
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logic [31:1] ifu_fetch_pc; // starting pc of fetch
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logic [31:1] ifc_fetch_addr_f1;
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logic ic_crit_wd_rdy;
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logic ic_write_stall;
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logic ic_dma_active;
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logic ifc_dma_access_ok;
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logic ifc_iccm_access_f1;
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logic ifc_region_acc_fault_f1;
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logic ic_access_fault_f2;
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logic ifu_ic_mb_empty;
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logic ic_hit_f2;
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// fetch control
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ifu_ifc_ctl ifc (.*
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);
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`ifdef RV_BTB_48
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logic [7:0][1:0] ifu_bp_way_f2; // way indication; right justified
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`else
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logic [7:0] ifu_bp_way_f2; // way indication; right justified
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`endif
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logic ifu_bp_kill_next_f2; // kill next fetch; taken target found
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logic [31:1] ifu_bp_btb_target_f2; // predicted target PC
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logic [7:1] ifu_bp_inst_mask_f2; // tell ic which valids to kill because of a taken branch; right justified
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logic [7:0] ifu_bp_hist1_f2; // history counters for all 4 potential branches; right justified
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logic [7:0] ifu_bp_hist0_f2; // history counters for all 4 potential branches; right justified
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logic [11:0] ifu_bp_poffset_f2; // predicted target
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logic [7:0] ifu_bp_ret_f2; // predicted ret ; right justified
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logic [7:0] ifu_bp_pc4_f2; // pc4 indication; right justified
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logic [7:0] ifu_bp_valid_f2; // branch valid, right justified
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logic [`RV_BHT_GHR_RANGE] ifu_bp_fghr_f2;
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// branch predictor
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ifu_bp_ctl bp (.*);
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logic [7:0] ic_fetch_val_f2;
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logic [127:0] ic_data_f2;
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logic [127:0] ifu_fetch_data;
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logic ifc_fetch_req_f1_raw, ifc_fetch_req_f1, ifc_fetch_req_f2;
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logic ic_rd_parity_final_err; // This fetch has a data_cache or tag parity error.
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logic iccm_rd_ecc_single_err; // This fetch has an iccm single error.
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logic iccm_rd_ecc_double_err; // This fetch has an iccm double error.
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icache_err_pkt_t ic_error_f2;
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logic ifu_icache_fetch_f2 ;
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logic [16:2] ifu_icache_error_index; // Index with parity error
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logic ifu_icache_error_val; // Parity error
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logic ifu_icache_sb_error_val;
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assign ifu_fetch_data[127:0] = ic_data_f2[127:0];
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assign ifu_fetch_val[7:0] = ic_fetch_val_f2[7:0];
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assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f2[31:1];
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// aligner
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ifu_aln_ctl aln (.*);
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// icache
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ifu_mem_ctl mem_ctl
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(.*,
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.fetch_addr_f1(ifc_fetch_addr_f1),
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.ifu_icache_error_index(ifu_icache_error_index[16:6]),
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.ic_hit_f2(ic_hit_f2),
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.ic_data_f2(ic_data_f2[127:0])
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);
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// Performance debug info
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//
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//
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`ifdef DUMP_BTB_ON
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logic exu_mp_valid; // conditional branch mispredict
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logic exu_mp_way; // conditional branch mispredict
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logic exu_mp_ataken; // direction is actual taken
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logic exu_mp_boffset; // branch offsett
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logic exu_mp_pc4; // branch is a 4B inst
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logic exu_mp_call; // branch is a call inst
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logic exu_mp_ret; // branch is a ret inst
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logic exu_mp_ja; // branch is a jump always
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logic [1:0] exu_mp_hist; // new history
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logic [11:0] exu_mp_tgt; // target offset
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logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
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logic [1:0] exu_mp_bank; // write bank; based on branch PC[3:2]
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logic [`RV_BTB_BTAG_SIZE-1:0] exu_mp_btag; // branch tag
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logic [`RV_BHT_GHR_RANGE] exu_mp_fghr; // original fetch ghr (for correcting dir)
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assign exu_mp_valid = exu_mp_pkt.misp; // conditional branch mispredict
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assign exu_mp_ataken = exu_mp_pkt.ataken; // direction is actual taken
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assign exu_mp_boffset = exu_mp_pkt.boffset; // branch offset
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assign exu_mp_pc4 = exu_mp_pkt.pc4; // branch is a 4B inst
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assign exu_mp_call = exu_mp_pkt.pcall; // branch is a call inst
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assign exu_mp_ret = exu_mp_pkt.pret; // branch is a ret inst
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assign exu_mp_ja = exu_mp_pkt.pja; // branch is a jump always
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assign exu_mp_way = exu_mp_pkt.way; // branch is a jump always
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assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0]; // new history
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assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0] ; // target offset
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assign exu_mp_addr[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] = exu_mp_pkt.index[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] ; // BTB/BHT address
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assign exu_mp_bank[1:0] = exu_mp_pkt.bank[1:0] ; // write bank = exu_mp_pkt.; based on branch PC[3:2]
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assign exu_mp_btag = exu_mp_pkt.btag[`RV_BTB_BTAG_SIZE-1:0] ; // branch tag
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assign exu_mp_fghr[`RV_BHT_GHR_RANGE] = exu_mp_pkt.fghr[`RV_BHT_GHR_RANGE] ; // original fetch ghr (for correcting dir)
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logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] btb_rd_addr_f2;
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`define DEC `CPU_TOP.dec
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`define EXU `CPU_TOP.exu
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rvbtb_addr_hash f2hash(.pc(ifc_fetch_addr_f2[31:1]), .hash(btb_rd_addr_f2[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO]));
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logic [31:0] mppc_ns, mppc;
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assign mppc_ns[31:1] = `EXU.exu_i0_flush_upper_e1 ? `DEC.decode.i0_pc_e1[31:1] : (`EXU.exu_i1_flush_upper_e1 ? `DEC.decode.i1_pc_e1[31:1] : (`EXU.exu_i0_flush_lower_e4 ? `DEC.decode.i0_pc_e4[31:1] : `DEC.decode.i1_pc_e4[31:1]));
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assign mppc_ns[0] = 1'b0;
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logic [3:0] ic_rd_hit_f2;
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rvdff #(36) mdseal_ff (.*, .din({mppc_ns[31:0], mem_ctl.ic_rd_hit[3:0]}), .dout({mppc[31:0],ic_rd_hit_f2[3:0]}));
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logic [2:0] tmp_bnk;
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assign tmp_bnk[2:0] = encode8_3(bp.btb_sel_f2[7:0]);
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always @(negedge clk) begin
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if(`DEC.tlu.mcyclel[31:0] == 32'h0000_0010) begin
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$display("BTB_CONFIG: %d",`RV_BTB_ARRAY_DEPTH*4);
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`ifndef BP_NOGSHARE
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$display("BHT_CONFIG: %d gshare: 1",`RV_BHT_ARRAY_DEPTH*4);
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`else
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$display("BHT_CONFIG: %d gshare: 0",`RV_BHT_ARRAY_DEPTH*4);
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`endif
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$display("RS_CONFIG: %d", `RV_RET_STACK_SIZE);
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end
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if(exu_flush_final & ~(dec_tlu_br0_wb_pkt.br_error | dec_tlu_br0_wb_pkt.br_start_error | dec_tlu_br1_wb_pkt.br_error | dec_tlu_br1_wb_pkt.br_start_error) & (exu_mp_pkt.misp | exu_mp_pkt.ataken))
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$display("%7d BTB_MP : index: %0h bank: %0h call: %b ret: %b ataken: %b hist: %h valid: %b tag: %h targ: %h eghr: %b pred: %b ghr_index: %h brpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha, exu_mp_addr[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO], exu_mp_bank[1:0], exu_mp_call, exu_mp_ret, exu_mp_ataken, exu_mp_hist[1:0], exu_mp_valid, exu_mp_pkt.btag[`RV_BTB_BTAG_SIZE-1:0], {exu_flush_path_final[31:1], 1'b0}, exu_mp_eghr[`RV_BHT_GHR_RANGE], exu_mp_valid, bp.bht_wr_addr0, mppc[31:0], exu_mp_pkt.way);
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for(int i = 0; i < 8; i++) begin
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if(ifu_bp_valid_f2[i] & ifc_fetch_req_f2)
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$display("%7d BTB_HIT : index: %0h bank: %0h call: %b ret: %b taken: %b strength: %b tag: %h targ: %h ghr: %4b ghr_index: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,btb_rd_addr_f2[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO],encode8_3(bp.btb_sel_f2[7:0]), bp.btb_rd_call_f2, bp.btb_rd_ret_f2, ifu_bp_hist1_f2[tmp_bnk], ifu_bp_hist0_f2[tmp_bnk], bp.fetch_rd_tag_f2[`RV_BTB_BTAG_SIZE-1:0], {ifu_bp_btb_target_f2[31:1], 1'b0}, bp.fghr[`RV_BHT_GHR_RANGE], bp.bht_rd_addr_f1, ifu_bp_way_f2[tmp_bnk]);
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end
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`ifdef RV_BTB_48
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for(int y = 0; y < 4; y++) begin
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for(int z = 0; z < 4; z++) begin
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if(bp.lru_bank_sel[y][z])
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$display("%7d BTB_LRU: index: %0h bank: %0h newlru %h", `DEC.tlu.mcyclel[31:0]+32'ha, z,y,bp.lru_bank_wr_data[y][z]);
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end
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end
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`endif
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if(dec_tlu_br0_wb_pkt.valid & ~(dec_tlu_br0_wb_pkt.br_error | dec_tlu_br0_wb_pkt.br_start_error))
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$display("%7d BTB_UPD0: ghr_index: %0h bank: %0h hist: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,bp.br0_hashed_wb[`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO],{dec_tlu_br0_wb_pkt.bank[1:0],dec_tlu_br0_wb_pkt.middle}, dec_tlu_br0_wb_pkt.hist, dec_tlu_br0_wb_pkt.way);
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if(dec_tlu_br1_wb_pkt.valid & ~(dec_tlu_br1_wb_pkt.br_error | dec_tlu_br1_wb_pkt.br_start_error))
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$display("%7d BTB_UPD1: ghr_index: %0h bank: %0h hist: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,bp.br1_hashed_wb[`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO],{dec_tlu_br1_wb_pkt.bank[1:0],dec_tlu_br1_wb_pkt.middle}, dec_tlu_br1_wb_pkt.hist, dec_tlu_br1_wb_pkt.way);
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if(dec_tlu_br0_wb_pkt.br_error | dec_tlu_br0_wb_pkt.br_start_error)
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$display("%7d BTB_ERR0: index: %0h bank: %0h start: %b rfpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,dec_tlu_br0_wb_pkt.index[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO],dec_tlu_br0_wb_pkt.bank[1:0], dec_tlu_br0_wb_pkt.br_start_error, {exu_flush_path_final[31:1], 1'b0}, dec_tlu_br0_wb_pkt.way);
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if(dec_tlu_br1_wb_pkt.br_error | dec_tlu_br1_wb_pkt.br_start_error)
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$display("%7d BTB_ERR1: index: %0h bank: %0h start: %b rfpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,dec_tlu_br1_wb_pkt.index[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO],dec_tlu_br1_wb_pkt.bank[1:0], dec_tlu_br1_wb_pkt.br_start_error, {exu_flush_path_final[31:1], 1'b0}, dec_tlu_br1_wb_pkt.way);
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end // always @ (negedge clk)
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function [2:0] encode8_3;
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input [7:0] in;
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|
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encode8_3[2] = |in[7:4];
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encode8_3[1] = in[7] | in[6] | in[3] | in[2];
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encode8_3[0] = in[7] | in[5] | in[3] | in[1];
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endfunction
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`endif
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endmodule // ifu
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