1089 lines
59 KiB
Plaintext
1089 lines
59 KiB
Plaintext
yosys -p "read_verilog -sv top.sv bram.sv; synth_ecp5 -top top -json top.json"
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/----------------------------------------------------------------------------\
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| yosys -- Yosys Open SYnthesis Suite |
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| Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
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| Permission to use, copy, modify, and/or distribute this software for any |
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| purpose with or without fee is hereby granted, provided that the above |
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| copyright notice and this permission notice appear in all copies. |
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| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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\----------------------------------------------------------------------------/
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Yosys 0.13+28 (git sha1 fc40df091, gcc 11.2.0-7ubuntu2 -fPIC -Os)
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-- Running command `read_verilog -sv top.sv bram.sv; synth_ecp5 -top top -json top.json' --
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1. Executing Verilog-2005 frontend: top.sv
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Parsing SystemVerilog input from `top.sv' to AST representation.
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Generating RTLIL representation for module `\top'.
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Model running...
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Successfully finished Verilog frontend.
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2. Executing Verilog-2005 frontend: bram.sv
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Parsing SystemVerilog input from `bram.sv' to AST representation.
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Generating RTLIL representation for module `\bram'.
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Successfully finished Verilog frontend.
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3. Executing SYNTH_ECP5 pass.
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3.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_sim.v
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Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation.
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Generating RTLIL representation for module `\LUT4'.
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Generating RTLIL representation for module `\$__ABC9_LUT5'.
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Generating RTLIL representation for module `\$__ABC9_LUT6'.
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Generating RTLIL representation for module `\$__ABC9_LUT7'.
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Generating RTLIL representation for module `\L6MUX21'.
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Generating RTLIL representation for module `\CCU2C'.
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Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
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Generating RTLIL representation for module `\PFUMX'.
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Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
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Generating RTLIL representation for module `\DPR16X4C'.
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Generating RTLIL representation for module `\LUT2'.
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Generating RTLIL representation for module `\TRELLIS_FF'.
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Generating RTLIL representation for module `\TRELLIS_IO'.
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Generating RTLIL representation for module `\INV'.
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Generating RTLIL representation for module `\TRELLIS_SLICE'.
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Generating RTLIL representation for module `\DP16KD'.
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Generating RTLIL representation for module `\FD1P3AX'.
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Generating RTLIL representation for module `\FD1P3AY'.
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Generating RTLIL representation for module `\FD1P3BX'.
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Generating RTLIL representation for module `\FD1P3DX'.
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Generating RTLIL representation for module `\FD1P3IX'.
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Generating RTLIL representation for module `\FD1P3JX'.
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Generating RTLIL representation for module `\FD1S3AX'.
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Generating RTLIL representation for module `\FD1S3AY'.
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Generating RTLIL representation for module `\FD1S3BX'.
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Generating RTLIL representation for module `\FD1S3DX'.
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Generating RTLIL representation for module `\FD1S3IX'.
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Generating RTLIL representation for module `\FD1S3JX'.
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Generating RTLIL representation for module `\IFS1P3BX'.
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Generating RTLIL representation for module `\IFS1P3DX'.
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Generating RTLIL representation for module `\IFS1P3IX'.
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Generating RTLIL representation for module `\IFS1P3JX'.
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Generating RTLIL representation for module `\OFS1P3BX'.
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Generating RTLIL representation for module `\OFS1P3DX'.
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Generating RTLIL representation for module `\OFS1P3IX'.
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Generating RTLIL representation for module `\OFS1P3JX'.
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Generating RTLIL representation for module `\IB'.
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Generating RTLIL representation for module `\IBPU'.
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Generating RTLIL representation for module `\IBPD'.
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Generating RTLIL representation for module `\OB'.
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Generating RTLIL representation for module `\OBZ'.
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Generating RTLIL representation for module `\OBZPU'.
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Generating RTLIL representation for module `\OBZPD'.
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Generating RTLIL representation for module `\OBCO'.
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Generating RTLIL representation for module `\BB'.
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Generating RTLIL representation for module `\BBPU'.
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Generating RTLIL representation for module `\BBPD'.
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Generating RTLIL representation for module `\ILVDS'.
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Generating RTLIL representation for module `\OLVDS'.
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Successfully finished Verilog frontend.
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3.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_bb.v
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Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation.
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Generating RTLIL representation for module `\MULT18X18D'.
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Generating RTLIL representation for module `\ALU54B'.
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Generating RTLIL representation for module `\EHXPLLL'.
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Generating RTLIL representation for module `\DTR'.
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Generating RTLIL representation for module `\OSCG'.
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Generating RTLIL representation for module `\USRMCLK'.
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Generating RTLIL representation for module `\JTAGG'.
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Generating RTLIL representation for module `\DELAYF'.
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Generating RTLIL representation for module `\DELAYG'.
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Generating RTLIL representation for module `\IDDRX1F'.
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Generating RTLIL representation for module `\IDDRX2F'.
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Generating RTLIL representation for module `\IDDR71B'.
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Generating RTLIL representation for module `\IDDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX1F'.
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Generating RTLIL representation for module `\ODDRX2F'.
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Generating RTLIL representation for module `\ODDR71B'.
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Generating RTLIL representation for module `\OSHX2A'.
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Generating RTLIL representation for module `\ODDRX2DQA'.
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Generating RTLIL representation for module `\ODDRX2DQSB'.
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Generating RTLIL representation for module `\TSHX2DQA'.
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Generating RTLIL representation for module `\TSHX2DQSA'.
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Generating RTLIL representation for module `\DQSBUFM'.
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Generating RTLIL representation for module `\DDRDLLA'.
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Generating RTLIL representation for module `\DLLDELD'.
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Generating RTLIL representation for module `\CLKDIVF'.
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Generating RTLIL representation for module `\ECLKSYNCB'.
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Generating RTLIL representation for module `\ECLKBRIDGECS'.
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Generating RTLIL representation for module `\DCCA'.
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Generating RTLIL representation for module `\DCSC'.
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Generating RTLIL representation for module `\DCUA'.
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Generating RTLIL representation for module `\EXTREFB'.
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Generating RTLIL representation for module `\PCSCLKDIV'.
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Generating RTLIL representation for module `\PUR'.
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Generating RTLIL representation for module `\GSR'.
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Generating RTLIL representation for module `\SGSR'.
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Generating RTLIL representation for module `\PDPW16KD'.
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Successfully finished Verilog frontend.
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3.3. Executing HIERARCHY pass (managing design hierarchy).
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3.3.1. Analyzing design hierarchy..
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Top module: \top
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Used module: \bram
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Parameter \WIDTH = 8
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Parameter \DEPTH = 10
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Parameter \SIZE = 4096
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3.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\bram'.
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Parameter \WIDTH = 8
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Parameter \DEPTH = 10
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Parameter \SIZE = 4096
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Generating RTLIL representation for module `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram'.
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3.3.3. Analyzing design hierarchy..
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Top module: \top
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Used module: $paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram
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3.3.4. Analyzing design hierarchy..
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Top module: \top
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Used module: $paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram
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Removing unused module `\bram'.
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Removed 1 unused modules.
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3.4. Executing PROC pass (convert processes to netlists).
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3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
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Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$135'.
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Removing empty process `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$proc$bram.sv:0$251'.
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Cleaned up 1 empty switch.
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3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$235 in module TRELLIS_FF.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$194 in module DPR16X4C.
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Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$136 in module TRELLIS_DPR16X4.
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Marked 1 switch rules as full_case in process $proc$bram.sv:20$241 in module $paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.
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Removed a total of 0 dead cases.
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3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
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Removed 0 redundant assignments.
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Promoted 52 assignments to connections.
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3.4.4. Executing PROC_INIT pass (extract init attributes).
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Found init rule in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$239'.
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Set init value: \Q = 1'0
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Found init rule in `\top.$proc$top.sv:0$4'.
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Set init value: \read_addr = 10'0000000000
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Set init value: \write_addr = 10'0000000000
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Set init value: \write_data = 8'00000000
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3.4.5. Executing PROC_ARST pass (detect async resets in processes).
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3.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
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Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$239'.
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Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$235'.
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1/1: $0\Q[0:0]
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Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$194'.
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1/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$193_EN[3:0]$200
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2/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$193_DATA[3:0]$199
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3/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$193_ADDR[3:0]$198
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Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
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Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$136'.
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1/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$134_EN[3:0]$142
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2/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$134_DATA[3:0]$141
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3/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$134_ADDR[3:0]$140
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Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$135'.
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Creating decoders for process `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$proc$bram.sv:26$248'.
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1/1: $0\data_rd[7:0]
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Creating decoders for process `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$proc$bram.sv:20$241'.
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1/3: $1$memwr$\ram$bram.sv:22$240_EN[7:0]$247
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2/3: $1$memwr$\ram$bram.sv:22$240_DATA[7:0]$246
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3/3: $1$memwr$\ram$bram.sv:22$240_ADDR[11:0]$245
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Creating decoders for process `\top.$proc$top.sv:0$4'.
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Creating decoders for process `\top.$proc$top.sv:29$3'.
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3.4.7. Executing PROC_DLATCH pass (convert process syncs to latches).
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3.4.8. Executing PROC_DFF pass (convert process syncs to FFs).
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Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$235'.
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created $dff cell `$procdff$286' with positive edge clock.
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Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$178_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$179_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$180_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$181_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$182_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$183_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$184_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$185_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$186_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$187_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$188_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$189_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$190_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$191_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$192_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
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created direct connection (no actual register cell created).
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$193_ADDR' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$194'.
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created $dff cell `$procdff$287' with positive edge clock.
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$193_DATA' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$194'.
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created $dff cell `$procdff$288' with positive edge clock.
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Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$193_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$194'.
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created $dff cell `$procdff$289' with positive edge clock.
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Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
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created direct connection (no actual register cell created).
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Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$118_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
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created direct connection (no actual register cell created).
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Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$119_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
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created direct connection (no actual register cell created).
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Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$120_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
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created direct connection (no actual register cell created).
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Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$121_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
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created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$122_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$123_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$124_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$125_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$126_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$127_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$128_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$129_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$130_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$131_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$132_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$133_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$134_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$136'.
|
|
created $dff cell `$procdff$290' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$134_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$136'.
|
|
created $dff cell `$procdff$291' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$134_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$136'.
|
|
created $dff cell `$procdff$292' with positive edge clock.
|
|
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$135'.
|
|
created direct connection (no actual register cell created).
|
|
Creating register for signal `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.\data_rd' using process `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$proc$bram.sv:26$248'.
|
|
created $dff cell `$procdff$293' with positive edge clock.
|
|
Creating register for signal `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$memwr$\ram$bram.sv:22$240_ADDR' using process `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$proc$bram.sv:20$241'.
|
|
created $dff cell `$procdff$294' with positive edge clock.
|
|
Creating register for signal `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$memwr$\ram$bram.sv:22$240_DATA' using process `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$proc$bram.sv:20$241'.
|
|
created $dff cell `$procdff$295' with positive edge clock.
|
|
Creating register for signal `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$memwr$\ram$bram.sv:22$240_EN' using process `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$proc$bram.sv:20$241'.
|
|
created $dff cell `$procdff$296' with positive edge clock.
|
|
Creating register for signal `\top.\led_o' using process `\top.$proc$top.sv:29$3'.
|
|
created $dff cell `$procdff$297' with positive edge clock.
|
|
Creating register for signal `\top.\read_addr' using process `\top.$proc$top.sv:29$3'.
|
|
created $dff cell `$procdff$298' with positive edge clock.
|
|
Creating register for signal `\top.\write_addr' using process `\top.$proc$top.sv:29$3'.
|
|
created $dff cell `$procdff$299' with positive edge clock.
|
|
Creating register for signal `\top.\write_data' using process `\top.$proc$top.sv:29$3'.
|
|
created $dff cell `$procdff$300' with positive edge clock.
|
|
|
|
3.4.9. Executing PROC_MEMWR pass (convert process memory writes to cells).
|
|
|
|
3.4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).
|
|
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$239'.
|
|
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$235'.
|
|
Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$235'.
|
|
Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$217'.
|
|
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$194'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$160'.
|
|
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$136'.
|
|
Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$135'.
|
|
Found and cleaned up 1 empty switch in `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$proc$bram.sv:26$248'.
|
|
Removing empty process `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$proc$bram.sv:26$248'.
|
|
Found and cleaned up 1 empty switch in `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$proc$bram.sv:20$241'.
|
|
Removing empty process `$paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.$proc$bram.sv:20$241'.
|
|
Removing empty process `top.$proc$top.sv:0$4'.
|
|
Removing empty process `top.$proc$top.sv:29$3'.
|
|
Cleaned up 6 empty switches.
|
|
|
|
3.4.11. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module $paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.
|
|
Optimizing module top.
|
|
|
|
3.5. Executing FLATTEN pass (flatten design).
|
|
Deleting now unused module $paramod$27c53d37c91ca9b8b077500dcff58f781e672cc9\bram.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.6. Executing TRIBUF pass.
|
|
|
|
3.7. Executing DEMINOUT pass (demote inout ports to input or output).
|
|
|
|
3.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~4 debug messages>
|
|
|
|
3.9. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 6 unused cells and 32 unused wires.
|
|
<suppressed ~12 debug messages>
|
|
|
|
3.10. Executing CHECK pass (checking for obvious problems).
|
|
Checking module top...
|
|
Found and reported 0 problems.
|
|
|
|
3.11. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.11.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.11.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
3.11.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.11.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.11.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.11.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
3.12. Executing FSM pass (extract and optimize FSM).
|
|
|
|
3.12.1. Executing FSM_DETECT pass (finding FSMs in design).
|
|
|
|
3.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
|
|
|
|
3.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
3.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
|
|
|
|
3.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
|
|
|
|
3.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
|
|
|
|
3.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
|
|
|
|
3.13. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.13.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.13.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
3.13.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.13.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.13.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.13.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
3.14. Executing WREDUCE pass (reducing word size of cells).
|
|
Removed top 20 address bits (of 32) from memory init port top.$flatten\bram_i.$meminit$\ram$bram.sv:0$250 (bram_i.ram).
|
|
Removed top 7 bits (of 8) from FF cell top.$flatten\bram_i.$procdff$293 ($dff).
|
|
Removed top 7 bits (of 8) from wire top.read_data.
|
|
|
|
3.15. Executing PEEPOPT pass (run peephole optimizers).
|
|
|
|
3.16. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 0 unused cells and 1 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.17. Executing SHARE pass (SAT-based resource sharing).
|
|
|
|
3.18. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_lut_cmp_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.18.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~6 debug messages>
|
|
|
|
3.19. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.20. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.21. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.21.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/mul2dsp.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/mul2dsp.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_mul'.
|
|
Generating RTLIL representation for module `\_90_soft_mul'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.21.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/dsp_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/dsp_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__MUL18X18'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.21.3. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~5 debug messages>
|
|
|
|
3.22. Executing ALUMACC pass (create $alu and $macc cells).
|
|
Extracting $alu and $macc cells in module top:
|
|
creating $macc model for $add$top.sv:10$1 ($add).
|
|
creating $alu model for $macc $add$top.sv:10$1.
|
|
creating $alu cell for $add$top.sv:10$1: $auto$alumacc.cc:485:replace_alu$304
|
|
created 1 $alu and 0 $macc cells.
|
|
|
|
3.23. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.23.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.23.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
3.23.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.23.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.23.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.23.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
3.24. Executing MEMORY pass.
|
|
|
|
3.24.1. Executing OPT_MEM pass (optimize memories).
|
|
Performed a total of 1 transformations.
|
|
|
|
3.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
|
|
Performed a total of 0 transformations.
|
|
|
|
3.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
|
|
|
|
3.24.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
|
|
Checking read port `\bram_i.ram'[0] in module `\top': merging output FF to cell.
|
|
|
|
3.24.5. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 1 unused cells and 1 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.24.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
|
|
|
|
3.24.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
|
|
Performed a total of 0 transformations.
|
|
|
|
3.24.8. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.24.9. Executing MEMORY_COLLECT pass (generating $mem cells).
|
|
|
|
3.25. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.26. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
Processing top.bram_i.ram:
|
|
Properties: ports=1 bits=32768 rports=1 wports=0 dbits=8 abits=12 words=4096
|
|
Checking rule #1 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #1 for bram type $__ECP5_PDPW16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_PDPW16KD (variant 1):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=14336 efficiency=22
|
|
Storing for later selection.
|
|
Checking rule #2 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule #2 for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #3 for bram type $__ECP5_PDPW16KD (variant 1):
|
|
Bram geometry: abits=9 dbits=36 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_PDPW16KD: awaste=0 dwaste=28 bwaste=14336 waste=14336 efficiency=22
|
|
Rule for bram type $__ECP5_PDPW16KD (variant 1) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 1) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 1):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=10240 efficiency=44
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 2) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 2):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=2048 efficiency=88
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 3) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=0 efficiency=100
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4096 dwaste=0 bwaste=8192 waste=8192 efficiency=50
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 4) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 4):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=8192 efficiency=50
|
|
Storing for later selection.
|
|
Checking rule #4 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=12288 dwaste=0 bwaste=12288 waste=12288 efficiency=25
|
|
Rule #4 for bram type $__ECP5_DP16KD (variant 5) accepted.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 5):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port B1.1.
|
|
Updated properties: dups=1 waste=12288 efficiency=25
|
|
Storing for later selection.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4096 dwaste=0 bwaste=8192 waste=8192 efficiency=50
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #5 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=12288 dwaste=0 bwaste=12288 waste=12288 efficiency=25
|
|
Rule #5 for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'min wports 1' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 1):
|
|
Bram geometry: abits=10 dbits=18 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=10 bwaste=10240 waste=10240 efficiency=44
|
|
Rule for bram type $__ECP5_DP16KD (variant 1) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 2):
|
|
Bram geometry: abits=11 dbits=9 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=1 bwaste=2048 waste=2048 efficiency=88
|
|
Rule for bram type $__ECP5_DP16KD (variant 2) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 3):
|
|
Bram geometry: abits=12 dbits=4 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
|
|
Rule for bram type $__ECP5_DP16KD (variant 3) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 4):
|
|
Bram geometry: abits=13 dbits=2 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=4096 dwaste=0 bwaste=8192 waste=8192 efficiency=50
|
|
Rule for bram type $__ECP5_DP16KD (variant 4) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Checking rule #6 for bram type $__ECP5_DP16KD (variant 5):
|
|
Bram geometry: abits=14 dbits=1 wports=0 rports=0
|
|
Estimated number of duplicates for more read ports: dups=1
|
|
Metrics for $__ECP5_DP16KD: awaste=12288 dwaste=0 bwaste=12288 waste=12288 efficiency=25
|
|
Rule for bram type $__ECP5_DP16KD (variant 5) rejected: requirement 'attribute syn_romstyle="ebr" ...' not met.
|
|
Selecting best of 6 rules:
|
|
Efficiency for rule 4.5: efficiency=25, cells=8, acells=1
|
|
Efficiency for rule 4.4: efficiency=50, cells=4, acells=1
|
|
Efficiency for rule 4.3: efficiency=100, cells=2, acells=1
|
|
Efficiency for rule 4.2: efficiency=88, cells=2, acells=2
|
|
Efficiency for rule 4.1: efficiency=44, cells=4, acells=4
|
|
Efficiency for rule 1.1: efficiency=22, cells=8, acells=8
|
|
Selected rule 4.3 with efficiency 100.
|
|
Mapping to bram type $__ECP5_DP16KD (variant 3):
|
|
Read port #0 is in clock domain \clk.
|
|
Mapped to bram port B1.1.
|
|
Creating $__ECP5_DP16KD cell at grid position <0 0 0>: bram_i.ram.0.0.0
|
|
Creating $__ECP5_DP16KD cell at grid position <1 0 0>: bram_i.ram.1.0.0
|
|
|
|
3.27. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.27.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/brams_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__ECP5_DP16KD'.
|
|
Generating RTLIL representation for module `\$__ECP5_PDPW16KD'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.27.2. Continuing TECHMAP pass.
|
|
Using template $paramod$ba9148b1adcb2e75ad39c74e24db38e574379cd3\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
Using template $paramod$30fb7e36c476b971e3c7167d64eb66b5cf299a0d\$__ECP5_DP16KD for cells of type $__ECP5_DP16KD.
|
|
No more expansions possible.
|
|
<suppressed ~44 debug messages>
|
|
|
|
3.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
|
|
|
|
3.29. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.29.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/lutrams_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.29.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~3 debug messages>
|
|
|
|
3.30. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.30.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~10 debug messages>
|
|
|
|
3.30.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.30.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.30.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 1 unused cells and 21 unused wires.
|
|
<suppressed ~2 debug messages>
|
|
|
|
3.30.5. Finished fast OPT passes.
|
|
|
|
3.31. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
|
|
|
|
3.32. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.32.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.32.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.32.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
|
|
Running muxtree optimizer on module \top..
|
|
Creating internal representation of mux trees.
|
|
No muxes found in this module.
|
|
Removed 0 multiplexer ports.
|
|
|
|
3.32.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
|
|
Optimizing cells in module \top.
|
|
Performed a total of 0 changes.
|
|
|
|
3.32.5. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
Removed a total of 0 cells.
|
|
|
|
3.32.6. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.32.7. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.32.8. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.32.9. Finished OPT passes. (There is nothing left to do.)
|
|
|
|
3.33. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.33.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
|
|
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
|
|
Generating RTLIL representation for module `\_90_simplemap_various'.
|
|
Generating RTLIL representation for module `\_90_simplemap_registers'.
|
|
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
|
|
Generating RTLIL representation for module `\_90_shift_shiftx'.
|
|
Generating RTLIL representation for module `\_90_fa'.
|
|
Generating RTLIL representation for module `\_90_lcu'.
|
|
Generating RTLIL representation for module `\_90_alu'.
|
|
Generating RTLIL representation for module `\_90_macc'.
|
|
Generating RTLIL representation for module `\_90_alumacc'.
|
|
Generating RTLIL representation for module `\$__div_mod_u'.
|
|
Generating RTLIL representation for module `\$__div_mod_trunc'.
|
|
Generating RTLIL representation for module `\_90_div'.
|
|
Generating RTLIL representation for module `\_90_mod'.
|
|
Generating RTLIL representation for module `\$__div_mod_floor'.
|
|
Generating RTLIL representation for module `\_90_divfloor'.
|
|
Generating RTLIL representation for module `\_90_modfloor'.
|
|
Generating RTLIL representation for module `\_90_pow'.
|
|
Generating RTLIL representation for module `\_90_pmux'.
|
|
Generating RTLIL representation for module `\_90_demux'.
|
|
Generating RTLIL representation for module `\_90_lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.33.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/arith_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/arith_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\_80_ecp5_alu'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.33.3. Continuing TECHMAP pass.
|
|
Using extmapper simplemap for cells of type $dff.
|
|
Using template $paramod$754650b284649a026620fc6856e5b6886cbfe794\_80_ecp5_alu for cells of type $alu.
|
|
Using extmapper simplemap for cells of type $logic_or.
|
|
Using extmapper simplemap for cells of type $logic_and.
|
|
Using extmapper simplemap for cells of type $xor.
|
|
Using extmapper simplemap for cells of type $mux.
|
|
Using extmapper simplemap for cells of type $not.
|
|
Using extmapper simplemap for cells of type $pos.
|
|
No more expansions possible.
|
|
<suppressed ~118 debug messages>
|
|
|
|
3.34. Executing OPT pass (performing simple optimizations).
|
|
|
|
3.34.1. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
<suppressed ~36 debug messages>
|
|
|
|
3.34.2. Executing OPT_MERGE pass (detect identical cells).
|
|
Finding identical cells in module `\top'.
|
|
<suppressed ~3 debug messages>
|
|
Removed a total of 1 cells.
|
|
|
|
3.34.3. Executing OPT_DFF pass (perform DFF optimizations).
|
|
|
|
3.34.4. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 14 unused cells and 40 unused wires.
|
|
<suppressed ~15 debug messages>
|
|
|
|
3.34.5. Finished fast OPT passes.
|
|
|
|
3.35. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
|
|
3.36. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
|
|
|
|
3.37. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.37.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `\$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.37.2. Continuing TECHMAP pass.
|
|
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
|
|
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
|
|
No more expansions possible.
|
|
<suppressed ~104 debug messages>
|
|
|
|
3.38. Executing OPT_EXPR pass (perform const folding).
|
|
Optimizing module top.
|
|
|
|
3.39. Executing SIMPLEMAP pass (map simple cells to gate primitives).
|
|
|
|
3.40. Executing ECP5_GSR pass (implement FF init values).
|
|
Handling GSR in top.
|
|
|
|
3.41. Executing ATTRMVCP pass (move or copy attributes).
|
|
|
|
3.42. Executing OPT_CLEAN pass (remove unused cells and wires).
|
|
Finding unused cells or wires in module \top..
|
|
Removed 0 unused cells and 44 unused wires.
|
|
<suppressed ~1 debug messages>
|
|
|
|
3.43. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/latches_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/latches_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DLATCH_N_'.
|
|
Generating RTLIL representation for module `\$_DLATCH_P_'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.43.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~4 debug messages>
|
|
|
|
3.44. Executing ABC pass (technology mapping using ABC).
|
|
|
|
3.44.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
|
|
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
|
|
Don't call ABC as there is nothing to map.
|
|
Removing temp directory.
|
|
|
|
3.45. Executing TECHMAP pass (map to technology primitives).
|
|
|
|
3.45.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
|
|
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
|
|
Generating RTLIL representation for module `\$_DFF_N_'.
|
|
Generating RTLIL representation for module `\$_DFF_P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PN_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_DFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_NP1_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP0_'.
|
|
Generating RTLIL representation for module `\$_SDFF_PP1_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
|
|
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
|
|
Generating RTLIL representation for module `\$_ALDFF_NP_'.
|
|
Generating RTLIL representation for module `\$_ALDFF_PP_'.
|
|
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
|
|
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
|
|
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
|
|
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
|
|
Generating RTLIL representation for module `\FD1P3AX'.
|
|
Generating RTLIL representation for module `\FD1P3AY'.
|
|
Generating RTLIL representation for module `\FD1P3BX'.
|
|
Generating RTLIL representation for module `\FD1P3DX'.
|
|
Generating RTLIL representation for module `\FD1P3IX'.
|
|
Generating RTLIL representation for module `\FD1P3JX'.
|
|
Generating RTLIL representation for module `\FD1S3AX'.
|
|
Generating RTLIL representation for module `\FD1S3AY'.
|
|
Generating RTLIL representation for module `\FD1S3BX'.
|
|
Generating RTLIL representation for module `\FD1S3DX'.
|
|
Generating RTLIL representation for module `\FD1S3IX'.
|
|
Generating RTLIL representation for module `\FD1S3JX'.
|
|
Generating RTLIL representation for module `\IFS1P3BX'.
|
|
Generating RTLIL representation for module `\IFS1P3DX'.
|
|
Generating RTLIL representation for module `\IFS1P3IX'.
|
|
Generating RTLIL representation for module `\IFS1P3JX'.
|
|
Generating RTLIL representation for module `\OFS1P3BX'.
|
|
Generating RTLIL representation for module `\OFS1P3DX'.
|
|
Generating RTLIL representation for module `\OFS1P3IX'.
|
|
Generating RTLIL representation for module `\OFS1P3JX'.
|
|
Generating RTLIL representation for module `\IB'.
|
|
Generating RTLIL representation for module `\IBPU'.
|
|
Generating RTLIL representation for module `\IBPD'.
|
|
Generating RTLIL representation for module `\OB'.
|
|
Generating RTLIL representation for module `\OBZ'.
|
|
Generating RTLIL representation for module `\OBZPU'.
|
|
Generating RTLIL representation for module `\OBZPD'.
|
|
Generating RTLIL representation for module `\OBCO'.
|
|
Generating RTLIL representation for module `\BB'.
|
|
Generating RTLIL representation for module `\BBPU'.
|
|
Generating RTLIL representation for module `\BBPD'.
|
|
Generating RTLIL representation for module `\ILVDS'.
|
|
Generating RTLIL representation for module `\OLVDS'.
|
|
Generating RTLIL representation for module `\$lut'.
|
|
Successfully finished Verilog frontend.
|
|
|
|
3.45.2. Continuing TECHMAP pass.
|
|
No more expansions possible.
|
|
<suppressed ~72 debug messages>
|
|
|
|
3.46. Executing OPT_LUT_INS pass (discard unused LUT inputs).
|
|
Optimizing LUTs in top.
|
|
|
|
3.47. Executing AUTONAME pass.
|
|
Renamed 19 objects in module top (3 iterations).
|
|
<suppressed ~19 debug messages>
|
|
|
|
3.48. Executing HIERARCHY pass (managing design hierarchy).
|
|
|
|
3.48.1. Analyzing design hierarchy..
|
|
Top module: \top
|
|
|
|
3.48.2. Analyzing design hierarchy..
|
|
Top module: \top
|
|
Removed 0 unused modules.
|
|
|
|
3.49. Printing statistics.
|
|
|
|
=== top ===
|
|
|
|
Number of wires: 13
|
|
Number of wire bits: 72
|
|
Number of public wires: 13
|
|
Number of public wire bits: 72
|
|
Number of memories: 0
|
|
Number of memory bits: 0
|
|
Number of processes: 0
|
|
Number of cells: 17
|
|
CCU2C 5
|
|
DP16KD 1
|
|
TRELLIS_FF 11
|
|
|
|
3.50. Executing CHECK pass (checking for obvious problems).
|
|
Checking module top...
|
|
Found and reported 0 problems.
|
|
|
|
3.51. Executing JSON backend.
|
|
|
|
End of script. Logfile hash: 190f20a9ac, CPU: user 0.98s system 0.04s, MEM: 374.53 MB peak
|
|
Yosys 0.13+28 (git sha1 fc40df091, gcc 11.2.0-7ubuntu2 -fPIC -Os)
|
|
Time spent: 42% 8x techmap (0 sec), 40% 16x read_verilog (0 sec), ...
|
|
nextpnr-ecp5 --25k --package CABGA381 --speed 6 --json top.json --textcfg top.config --lpf top.lpf --freq 65
|