52 lines
1.2 KiB
Verilog
52 lines
1.2 KiB
Verilog
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module soc_fpga_ram(
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PortAClk,
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PortAAddr,
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PortADataIn,
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PortAWriteEnable,
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PortADataOut
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);
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parameter DATAWIDTH = 2;
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parameter ADDRWIDTH = 2;
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input PortAClk;
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input [(ADDRWIDTH-1):0] PortAAddr;
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input [(DATAWIDTH-1):0] PortADataIn;
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input PortAWriteEnable;
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output [(DATAWIDTH-1):0] PortADataOut;
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parameter MEMDEPTH = 2**(ADDRWIDTH);
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reg [(DATAWIDTH-1):0] mem [(MEMDEPTH-1):0];
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reg [(DATAWIDTH-1):0] PortADataOut;
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always @(posedge PortAClk)
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begin
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if(PortAWriteEnable)
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begin
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mem[PortAAddr] <= PortADataIn;
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end
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else
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begin
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PortADataOut <= mem[PortAAddr];
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end
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end
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endmodule
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