297 lines
16 KiB
Systemverilog
297 lines
16 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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// Owner:
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// Function: AHB to AXI4 Bridge
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// Comments:
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//
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//********************************************************************************
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module ahb_to_axi4 #(parameter TAG = 1) (
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input clk,
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input rst_l,
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input scan_mode,
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input bus_clk_en,
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input clk_override,
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// AXI signals
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// AXI Write Channels
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output logic axi_awvalid,
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input logic axi_awready,
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output logic [TAG-1:0] axi_awid,
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output logic [31:0] axi_awaddr,
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output logic [2:0] axi_awsize,
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output logic [2:0] axi_awprot,
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output logic [7:0] axi_awlen,
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output logic [1:0] axi_awburst,
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output logic axi_wvalid,
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input logic axi_wready,
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output logic [63:0] axi_wdata,
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output logic [7:0] axi_wstrb,
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output logic axi_wlast,
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input logic axi_bvalid,
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output logic axi_bready,
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input logic [1:0] axi_bresp,
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input logic [TAG-1:0] axi_bid,
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// AXI Read Channels
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output logic axi_arvalid,
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input logic axi_arready,
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output logic [TAG-1:0] axi_arid,
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output logic [31:0] axi_araddr,
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output logic [2:0] axi_arsize,
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output logic [2:0] axi_arprot,
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output logic [7:0] axi_arlen,
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output logic [1:0] axi_arburst,
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input logic axi_rvalid,
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output logic axi_rready,
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input logic [TAG-1:0] axi_rid,
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input logic [63:0] axi_rdata,
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input logic [1:0] axi_rresp,
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// AHB-Lite signals
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input logic [31:0] ahb_haddr, // ahb bus address
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input logic [2:0] ahb_hburst, // tied to 0
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input logic ahb_hmastlock, // tied to 0
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input logic [3:0] ahb_hprot, // tied to 4'b0011
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input logic [2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3)
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input logic [1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now)
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input logic ahb_hwrite, // ahb bus write
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input logic [63:0] ahb_hwdata, // ahb bus write data
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input logic ahb_hsel, // this slave was selected
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input logic ahb_hreadyin, // previous hready was accepted or not
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output logic [63:0] ahb_hrdata, // ahb bus read data
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output logic ahb_hreadyout, // slave ready to accept transaction
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output logic ahb_hresp // slave response (high indicates erro)
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);
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logic [7:0] master_wstrb;
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typedef enum logic [1:0] { IDLE = 2'b00, // Nothing in the buffer. No commands yet recieved
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WR = 2'b01, // Write Command recieved
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RD = 2'b10, // Read Command recieved
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PEND = 2'b11 // Waiting on Read Data from core
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} state_t;
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state_t buf_state, buf_nxtstate;
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logic buf_state_en;
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// Buffer signals (one entry buffer)
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logic buf_read_error_in, buf_read_error;
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logic [63:0] buf_rdata;
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logic ahb_hready;
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logic ahb_hready_q;
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logic [1:0] ahb_htrans_in, ahb_htrans_q;
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logic [2:0] ahb_hsize_q;
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logic ahb_hwrite_q;
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logic [31:0] ahb_haddr_q;
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logic [63:0] ahb_hwdata_q;
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logic ahb_hresp_q;
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//Miscellaneous signals
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logic ahb_addr_in_dccm, ahb_addr_in_iccm, ahb_addr_in_pic;
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logic ahb_addr_in_dccm_region_nc, ahb_addr_in_iccm_region_nc, ahb_addr_in_pic_region_nc;
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// signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus
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logic buf_rdata_en;
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logic ahb_bus_addr_clk_en, buf_rdata_clk_en;
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logic ahb_clk, ahb_addr_clk, buf_rdata_clk;
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// Command buffer is the holding station where we convert to AXI and send to core
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logic cmdbuf_wr_en, cmdbuf_rst;
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logic cmdbuf_full;
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logic cmdbuf_vld, cmdbuf_write;
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logic [1:0] cmdbuf_size;
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logic [7:0] cmdbuf_wstrb;
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logic [31:0] cmdbuf_addr;
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logic [63:0] cmdbuf_wdata;
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logic bus_clk;
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// FSM to control the bus states and when to block the hready and load the command buffer
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always_comb begin
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buf_nxtstate = IDLE;
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buf_state_en = 1'b0;
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buf_rdata_en = 1'b0; // signal to load the buffer when the core sends read data back
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buf_read_error_in = 1'b0; // signal indicating that an error came back with the read from the core
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cmdbuf_wr_en = 1'b0; // all clear from the gasket to load the buffer with the command for reads, command/dat for writes
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case (buf_state)
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IDLE: begin // No commands recieved
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buf_nxtstate = ahb_hwrite ? WR : RD;
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buf_state_en = ahb_hready & ahb_htrans[1] & ahb_hsel; // only transition on a valid hrtans
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end
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WR: begin // Write command recieved last cycle
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buf_nxtstate = (ahb_hresp | (ahb_htrans[1:0] == 2'b0) | ~ahb_hsel) ? IDLE : (ahb_hwrite ? WR : RD);
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buf_state_en = (~cmdbuf_full | ahb_hresp) ;
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cmdbuf_wr_en = ~cmdbuf_full & ~(ahb_hresp | ((ahb_htrans[1:0] == 2'b01) & ahb_hsel)); // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
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end
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RD: begin // Read command recieved last cycle.
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buf_nxtstate = ahb_hresp ? IDLE :PEND; // If error go to idle, else wait for read data
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buf_state_en = (~cmdbuf_full | ahb_hresp); // only when command can go, or if its an error
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cmdbuf_wr_en = ~ahb_hresp & ~cmdbuf_full; // send command only when no error
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end
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PEND: begin // Read Command has been sent. Waiting on Data.
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buf_nxtstate = IDLE; // go back for next command and present data next cycle
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buf_state_en = axi_rvalid & ~cmdbuf_write; // read data is back
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buf_rdata_en = buf_state_en; // buffer the read data coming back from core
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buf_read_error_in = buf_state_en & |axi_rresp[1:0]; // buffer error flag if return has Error ( ECC )
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end
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endcase
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end // always_comb begin
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assign master_wstrb[7:0] = ({8{ahb_hsize_q[2:0] == 3'b0}} & (8'b1 << ahb_haddr_q[2:0])) |
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({8{ahb_hsize_q[2:0] == 3'b1}} & (8'b11 << ahb_haddr_q[2:0])) |
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({8{ahb_hsize_q[2:0] == 3'b10}} & (8'b1111 << ahb_haddr_q[2:0])) |
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({8{ahb_hsize_q[2:0] == 3'b11}} & 8'b1111_1111);
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// AHB signals
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assign ahb_hreadyout = ahb_hresp ? (ahb_hresp_q & ~ahb_hready_q) :
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((~cmdbuf_full | (buf_state == IDLE)) & ~(buf_state == RD | buf_state == PEND) & ~buf_read_error);
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assign ahb_hready = ahb_hreadyout & ahb_hreadyin;
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assign ahb_htrans_in[1:0] = {2{ahb_hsel}} & ahb_htrans[1:0];
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assign ahb_hrdata[63:0] = buf_rdata[63:0];
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assign ahb_hresp = ((ahb_htrans_q[1:0] != 2'b0) & (buf_state != IDLE) &
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((~(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM
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((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & ~((ahb_hsize_q[1:0] == 2'b10) | (ahb_hsize_q[1:0] == 2'b11))) | // ICCM Rd/Wr OR DCCM Wr not the right size
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((ahb_hsize_q[2:0] == 3'h1) & ahb_haddr_q[0]) | // HW size but unaligned
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((ahb_hsize_q[2:0] == 3'h2) & (|ahb_haddr_q[1:0])) | // W size but unaligned
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((ahb_hsize_q[2:0] == 3'h3) & (|ahb_haddr_q[2:0])))) | // DW size but unaligned
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buf_read_error | // Read ECC error
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(ahb_hresp_q & ~ahb_hready_q); // This is for second cycle of hresp protocol
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// Buffer signals - needed for the read data and ECC error response
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// All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
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rvdff_fpga #(.WIDTH(1)) hresp_ff (.din(ahb_hresp), .dout(ahb_hresp_q), .clk(ahb_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(1)) hready_ff (.din(ahb_hready), .dout(ahb_hready_q), .clk(ahb_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(2)) htrans_ff (.din(ahb_htrans_in[1:0]), .dout(ahb_htrans_q[1:0]), .clk(ahb_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(3)) hsize_ff (.din(ahb_hsize[2:0]), .dout(ahb_hsize_q[2:0]), .clk(ahb_addr_clk), .clken(ahb_bus_addr_clk_en), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(1)) hwrite_ff (.din(ahb_hwrite), .dout(ahb_hwrite_q), .clk(ahb_addr_clk), .clken(ahb_bus_addr_clk_en), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(32)) haddr_ff (.din(ahb_haddr[31:0]), .dout(ahb_haddr_q[31:0]), .clk(ahb_addr_clk), .clken(ahb_bus_addr_clk_en), .rawclk(clk), .*);
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rvdffs_fpga #($bits(state_t)) state_reg (.din(buf_nxtstate), .dout({buf_state}), .en(buf_state_en), .clk(ahb_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(64)) buf_rdata_ff (.din(axi_rdata[63:0]), .dout(buf_rdata[63:0]), .clk(buf_rdata_clk), .clken(buf_rdata_clk_en), .rawclk(clk), .*);
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// buf_read_error will be high only one cycle
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rvdff_fpga #(.WIDTH(1)) buf_read_error_ff(.din(buf_read_error_in), .dout(buf_read_error),.clk(ahb_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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// Clock header logic
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assign ahb_bus_addr_clk_en = bus_clk_en & (ahb_hready & ahb_htrans[1]);
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assign buf_rdata_clk_en = bus_clk_en & buf_rdata_en;
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`ifdef RV_FPGA_OPTIMIZE
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assign ahb_clk = 1'b0;
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assign ahb_addr_clk = 1'b0;
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assign buf_rdata_clk = 1'b0;
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assign bus_clk = 1'b0;
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`else
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rvclkhdr ahb_cgc (.en(bus_clk_en), .l1clk(ahb_clk), .*); // ifndef FPGA_OPTIMIZE
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rvclkhdr ahb_addr_cgc (.en(ahb_bus_addr_clk_en), .l1clk(ahb_addr_clk), .*); // ifndef FPGA_OPTIMIZE
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rvclkhdr buf_rdata_cgc (.en(buf_rdata_clk_en), .l1clk(buf_rdata_clk), .*); // ifndef FPGA_OPTIMIZE
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rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*); // ifndef FPGA_OPTIMIZE
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`endif
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// Address check dccm
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rvrangecheck #(.CCM_SADR(`RV_DCCM_SADR),
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.CCM_SIZE(`RV_DCCM_SIZE)) addr_dccm_rangecheck (
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.addr(ahb_haddr_q[31:0]),
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.in_range(ahb_addr_in_dccm),
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.in_region(ahb_addr_in_dccm_region_nc)
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);
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// Address check iccm
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`ifdef RV_ICCM_ENABLE
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rvrangecheck #(.CCM_SADR(`RV_ICCM_SADR),
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.CCM_SIZE(`RV_ICCM_SIZE)) addr_iccm_rangecheck (
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.addr(ahb_haddr_q[31:0]),
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.in_range(ahb_addr_in_iccm),
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.in_region(ahb_addr_in_iccm_region_nc)
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);
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`else
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assign ahb_addr_in_iccm = '0;
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assign ahb_addr_in_iccm_region_nc = '0;
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`endif
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// PIC memory address check
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rvrangecheck #(.CCM_SADR(`RV_PIC_BASE_ADDR),
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.CCM_SIZE(`RV_PIC_SIZE)) addr_pic_rangecheck (
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.addr(ahb_haddr_q[31:0]),
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.in_range(ahb_addr_in_pic),
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.in_region(ahb_addr_in_pic_region_nc)
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);
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// Command Buffer - Holding for the commands to be sent for the AXI. It will be converted to the AXI signals.
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assign cmdbuf_rst = (((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)) & ~cmdbuf_wr_en) | (ahb_hresp & ~cmdbuf_write);
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assign cmdbuf_full = (cmdbuf_vld & ~((axi_awvalid & axi_awready) | (axi_arvalid & axi_arready)));
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rvdffsc_fpga #(.WIDTH(1)) cmdbuf_vldff (.din(1'b1), .clear(cmdbuf_rst), .dout(cmdbuf_vld), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(1)) cmdbuf_writeff (.din(ahb_hwrite_q), .dout(cmdbuf_write), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(2)) cmdbuf_sizeff (.din(ahb_hsize_q[1:0]), .dout(cmdbuf_size[1:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(8)) cmdbuf_wstrbff (.din(master_wstrb[7:0]), .dout(cmdbuf_wstrb[7:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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// REVIEW : was 2 clock headers
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// rvdffe #(.WIDTH(32)) cmdbuf_addrff (.din(ahb_haddr_q[31:0]), .dout(cmdbuf_addr[31:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
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// rvdffe #(.WIDTH(64)) cmdbuf_wdataff (.din(ahb_hwdata[63:0]), .dout(cmdbuf_wdata[63:0]), .en(cmdbuf_wr_en), .clk(bus_clk), .*);
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rvdffe #(.WIDTH(32)) cmdbuf_addrff (.din(ahb_haddr_q[31:0]), .dout(cmdbuf_addr[31:0]), .en(cmdbuf_wr_en & bus_clk_en), .*);
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rvdffe #(.WIDTH(64)) cmdbuf_wdataff (.din(ahb_hwdata[63:0]), .dout(cmdbuf_wdata[63:0]), .en(cmdbuf_wr_en & bus_clk_en), .*);
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// AXI Write Command Channel
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assign axi_awvalid = cmdbuf_vld & cmdbuf_write;
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assign axi_awid[TAG-1:0] = '0;
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assign axi_awaddr[31:0] = cmdbuf_addr[31:0];
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assign axi_awsize[2:0] = {1'b0, cmdbuf_size[1:0]};
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assign axi_awprot[2:0] = 3'b0;
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assign axi_awlen[7:0] = '0;
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assign axi_awburst[1:0] = 2'b01;
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// AXI Write Data Channel - This is tied to the command channel as we only write the command buffer once we have the data.
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assign axi_wvalid = cmdbuf_vld & cmdbuf_write;
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assign axi_wdata[63:0] = cmdbuf_wdata[63:0];
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assign axi_wstrb[7:0] = cmdbuf_wstrb[7:0];
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assign axi_wlast = 1'b1;
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// AXI Write Response - Always ready. AHB does not require a write response.
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assign axi_bready = 1'b1;
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// AXI Read Channels
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assign axi_arvalid = cmdbuf_vld & ~cmdbuf_write;
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assign axi_arid[TAG-1:0] = '0;
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assign axi_araddr[31:0] = cmdbuf_addr[31:0];
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assign axi_arsize[2:0] = {1'b0, cmdbuf_size[1:0]};
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assign axi_arprot = 3'b0;
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assign axi_arlen[7:0] = '0;
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assign axi_arburst[1:0] = 2'b01;
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// AXI Read Response Channel - Always ready as AHB reads are blocking and the the buffer is available for the read coming back always.
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assign axi_rready = 1'b1;
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// Clock header logic
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`ifdef ASSERT_ON
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property ahb_error_protocol;
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@(posedge ahb_clk) (ahb_hready & ahb_hresp) |-> (~$past(ahb_hready) & $past(ahb_hresp));
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endproperty
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assert_ahb_error_protocol: assert property (ahb_error_protocol) else
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$display("Bus Error with hReady isn't preceded with Bus Error without hready");
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`endif
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endmodule // ahb_to_axi4
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