549 lines
17 KiB
Systemverilog
549 lines
17 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// all flops call the rvdff flop
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module rvdff #( parameter WIDTH=1 )
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(
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input logic [WIDTH-1:0] din,
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input logic clk,
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input logic rst_l,
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output logic [WIDTH-1:0] dout
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);
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`ifdef CLOCKGATE
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always @(posedge tb_top.clk) begin
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#0 $strobe("CG: %0t %m din %x dout %x clk %b width %d",$time,din,dout,clk,WIDTH);
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end
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`endif
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always_ff @(posedge clk or negedge rst_l) begin
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if (rst_l == 0)
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dout[WIDTH-1:0] <= 0;
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else
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dout[WIDTH-1:0] <= din[WIDTH-1:0];
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end
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endmodule
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// rvdff with 2:1 input mux to flop din iff sel==1
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module rvdffs #( parameter WIDTH=1 )
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(
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input logic [WIDTH-1:0] din,
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input logic en,
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input logic clk,
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input logic rst_l,
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output logic [WIDTH-1:0] dout
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);
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rvdff #(WIDTH) dffs (.din((en) ? din[WIDTH-1:0] : dout[WIDTH-1:0]), .*);
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endmodule
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// rvdff with en and clear
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module rvdffsc #( parameter WIDTH=1 )
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(
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input logic [WIDTH-1:0] din,
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input logic en,
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input logic clear,
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input logic clk,
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input logic rst_l,
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output logic [WIDTH-1:0] dout
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);
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logic [WIDTH-1:0] din_new;
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assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]);
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rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*);
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endmodule
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// versions with clock enables .clken to assist in RV_FPGA_OPTIMIZE
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module rvdff_fpga #( parameter WIDTH=1 )
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(
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input logic [WIDTH-1:0] din,
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input logic clk,
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input logic clken,
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input logic rawclk,
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input logic rst_l,
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input logic scan_mode,
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output logic [WIDTH-1:0] dout
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);
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken), .*);
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`else
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rvdff #(WIDTH) dff (.*);
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`endif
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endmodule
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// rvdff with 2:1 input mux to flop din iff sel==1
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module rvdffs_fpga #( parameter WIDTH=1 )
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(
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input logic [WIDTH-1:0] din,
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input logic en,
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input logic clk,
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input logic clken,
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input logic rawclk,
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input logic rst_l,
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input logic scan_mode,
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output logic [WIDTH-1:0] dout
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);
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken & en), .*);
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`else
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rvdffs #(WIDTH) dffs (.*);
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`endif
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endmodule
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// rvdff with en and clear
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module rvdffsc_fpga #( parameter WIDTH=1 )
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(
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input logic [WIDTH-1:0] din,
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input logic en,
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input logic clear,
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input logic clk,
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input logic clken,
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input logic rawclk,
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input logic rst_l,
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input logic scan_mode,
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output logic [WIDTH-1:0] dout
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);
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dffs (.clk(rawclk), .din(din[WIDTH-1:0] & {WIDTH{~clear}}),.en((en | clear) & clken), .*);
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`else
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rvdffsc #(WIDTH) dffsc (.*);
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`endif
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endmodule
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module `TEC_RV_ICG
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(
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input logic TE, E, CP,
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output Q
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);
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logic en_ff;
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logic enable;
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assign enable = E | TE;
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`ifdef VERILATOR
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always @(negedge CP) begin
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en_ff <= enable;
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end
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`else
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always @(CP, enable) begin
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if(!CP)
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en_ff = enable;
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end
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`endif
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assign Q = CP & en_ff;
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endmodule
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`ifndef RV_FPGA_OPTIMIZE
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module rvclkhdr
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(
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input logic en,
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input logic clk,
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input logic scan_mode,
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output logic l1clk
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);
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logic TE;
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assign TE = scan_mode;
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`TEC_RV_ICG clkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
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endmodule // rvclkhdr
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`endif
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module rvoclkhdr
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(
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input logic en,
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input logic clk,
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input logic scan_mode,
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output logic l1clk
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);
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logic TE;
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assign TE = scan_mode;
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`ifdef RV_FPGA_OPTIMIZE
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assign l1clk = clk;
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`else
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`TEC_RV_ICG rvclkhdr ( .*, .E(en), .CP(clk), .Q(l1clk));
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`endif
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endmodule
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module rvdffe #( parameter WIDTH=8, parameter OVERRIDE=0 )
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(
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input logic [WIDTH-1:0] din,
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input logic en,
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input logic clk,
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input logic rst_l,
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input logic scan_mode,
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output logic [WIDTH-1:0] dout
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);
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logic l1clk;
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`ifndef PHYSICAL
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if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
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`endif
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dff ( .* );
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`else
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rvclkhdr clkhdr ( .* );
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rvdff #(WIDTH) dff (.*, .clk(l1clk));
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`endif
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`ifndef PHYSICAL
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end
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else
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$error("%m: rvdffe width must be >= 8");
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`endif
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endmodule // rvdffe
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module rvsyncss #(parameter WIDTH = 251)
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(
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input logic clk,
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input logic rst_l,
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input logic [WIDTH-1:0] din,
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output logic [WIDTH-1:0] dout
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);
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logic [WIDTH-1:0] din_ff1;
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rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));
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rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));
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endmodule // rvsyncss
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module rvlsadder
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(
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input logic [31:0] rs1,
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input logic [11:0] offset,
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output logic [31:0] dout
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);
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logic cout;
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logic sign;
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logic [31:12] rs1_inc;
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logic [31:12] rs1_dec;
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assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};
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assign rs1_inc[31:12] = rs1[31:12] + 1;
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assign rs1_dec[31:12] = rs1[31:12] - 1;
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assign sign = offset[11];
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assign dout[31:12] = ({20{ sign ^~ cout}} & rs1[31:12]) |
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({20{ ~sign & cout}} & rs1_inc[31:12]) |
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({20{ sign & ~cout}} & rs1_dec[31:12]);
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endmodule // rvlsadder
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// assume we only maintain pc[31:1] in the pipe
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module rvbradder
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(
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input [31:1] pc,
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input [12:1] offset,
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output [31:1] dout
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);
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logic cout;
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logic sign;
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logic [31:13] pc_inc;
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logic [31:13] pc_dec;
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assign {cout,dout[12:1]} = {1'b0,pc[12:1]} + {1'b0,offset[12:1]};
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assign pc_inc[31:13] = pc[31:13] + 1;
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assign pc_dec[31:13] = pc[31:13] - 1;
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assign sign = offset[12];
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assign dout[31:13] = ({19{ sign ^~ cout}} & pc[31:13]) |
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({19{ ~sign & cout}} & pc_inc[31:13]) |
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({19{ sign & ~cout}} & pc_dec[31:13]);
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endmodule // rvbradder
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// 2s complement circuit
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module rvtwoscomp #( parameter WIDTH=32 )
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(
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input logic [WIDTH-1:0] din,
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output logic [WIDTH-1:0] dout
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);
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logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din
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genvar i;
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for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one
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assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i];
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end : flip_after_first_one
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assign dout[WIDTH-1:0] = { dout_temp[WIDTH-1:1], din[0] };
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endmodule // 2'scomp
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// find first
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module rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) )
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(
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input logic [WIDTH-1:0] din,
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output logic [SHIFT-1:0] dout
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);
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logic done;
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always_comb begin
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dout[SHIFT-1:0] = {SHIFT{1'b0}};
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done = 1'b0;
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for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one
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done |= din[i];
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dout[SHIFT-1:0] += done ? 1'b0 : 1'b1;
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end : find_first_one
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end
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endmodule // rvfindfirst1
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module rvfindfirst1hot #( parameter WIDTH=32 )
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(
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input logic [WIDTH-1:0] din,
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output logic [WIDTH-1:0] dout
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);
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logic done;
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always_comb begin
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dout[WIDTH-1:0] = {WIDTH{1'b0}};
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done = 1'b0;
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for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one
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dout[i] = ~done & din[i];
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done |= din[i];
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end : find_first_one
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end
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endmodule // rvfindfirst1hot
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// mask and match function matches bits after finding the first 0 position
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// find first starting from LSB. Skip that location and match the rest of the bits
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module rvmaskandmatch #( parameter WIDTH=32 )
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(
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input logic [WIDTH-1:0] mask, // this will have the mask in the lower bit positions
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input logic [WIDTH-1:0] data, // this is what needs to be matched on the upper bits with the mask's upper bits
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input logic masken, // when 1 : do mask. 0 : full match
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output logic match
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);
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logic [WIDTH-1:0] matchvec;
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logic masken_or_fullmask;
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assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]);
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assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]);
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genvar i;
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for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero
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assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]);
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end : match_after_first_zero
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assign match = &matchvec[WIDTH-1:0]; // all bits either matched or were masked off
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endmodule // rvmaskandmatch
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module rvbtb_tag_hash (
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input logic [31:1] pc,
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output logic [`RV_BTB_BTAG_SIZE-1:0] hash
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);
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`ifndef RV_BTB_BTAG_FOLD
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assign hash = {(pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE+1] ^
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pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+1] ^
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pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+1])};
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`else
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assign hash = {(
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pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE+1] ^
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pc[`RV_BTB_ADDR_HI+`RV_BTB_BTAG_SIZE:`RV_BTB_ADDR_HI+1])};
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`endif
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// assign hash = {pc[`RV_BTB_ADDR_HI+1],(pc[`RV_BTB_ADDR_HI+13:`RV_BTB_ADDR_HI+10] ^
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// pc[`RV_BTB_ADDR_HI+9:`RV_BTB_ADDR_HI+6] ^
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// pc[`RV_BTB_ADDR_HI+5:`RV_BTB_ADDR_HI+2])};
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endmodule
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module rvbtb_addr_hash (
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input logic [31:1] pc,
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output logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] hash
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);
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assign hash[`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] = pc[`RV_BTB_INDEX1_HI:`RV_BTB_INDEX1_LO] ^
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`ifndef RV_BTB_FOLD2_INDEX_HASH
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pc[`RV_BTB_INDEX2_HI:`RV_BTB_INDEX2_LO] ^
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`endif
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pc[`RV_BTB_INDEX3_HI:`RV_BTB_INDEX3_LO];
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endmodule
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module rvbtb_ghr_hash (
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input logic [`RV_BTB_ADDR_HI:`RV_BTB_ADDR_LO] hashin,
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input logic [`RV_BHT_GHR_RANGE] ghr,
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output logic [`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO] hash
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);
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// The hash function is too complex to write in verilog for all cases.
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// The config script generates the logic string based on the bp config.
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assign hash[`RV_BHT_ADDR_HI:`RV_BHT_ADDR_LO] = `RV_BHT_HASH_STRING;
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endmodule
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// Check if the S_ADDR <= addr < E_ADDR
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module rvrangecheck #(CCM_SADR = 32'h0,
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CCM_SIZE = 128) (
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input logic [31:0] addr, // Address to be checked for range
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output logic in_range, // S_ADDR <= start_addr < E_ADDR
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output logic in_region
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);
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localparam REGION_BITS = 4;
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localparam MASK_BITS = 10 + $clog2(CCM_SIZE);
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logic [31:0] start_addr;
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logic [3:0] region;
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assign start_addr[31:0] = CCM_SADR;
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assign region[REGION_BITS-1:0] = start_addr[31:(32-REGION_BITS)];
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assign in_region = (addr[31:(32-REGION_BITS)] == region[REGION_BITS-1:0]);
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if (CCM_SIZE == 48)
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assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS-1 : MASK_BITS-2]);
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else
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assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]);
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endmodule // rvrangechecker
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// 16 bit even parity generator
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module rveven_paritygen #(WIDTH = 16) (
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input logic [WIDTH-1:0] data_in, // Data
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output logic parity_out // generated even parity
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);
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assign parity_out = ^(data_in[WIDTH-1:0]) ;
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endmodule // rveven_paritygen
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module rveven_paritycheck #(WIDTH = 16) (
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input logic [WIDTH-1:0] data_in, // Data
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input logic parity_in,
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output logic parity_err // Parity error
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);
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assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ;
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endmodule // rveven_paritycheck
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module rvecc_encode (
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input [31:0] din,
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output [6:0] ecc_out
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);
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logic [5:0] ecc_out_temp;
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assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
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assign ecc_out_temp[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];
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assign ecc_out_temp[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
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assign ecc_out_temp[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
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assign ecc_out_temp[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
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assign ecc_out_temp[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
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assign ecc_out[6:0] = {(^din[31:0])^(^ecc_out_temp[5:0]),ecc_out_temp[5:0]};
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endmodule // rvecc_encode
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module rvecc_decode (
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input en,
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input [31:0] din,
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input [6:0] ecc_in,
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input sed_ded, // only do detection and no correction. Used for the I$
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output [31:0] dout,
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output [6:0] ecc_out,
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output single_ecc_error,
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output double_ecc_error
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);
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logic [6:0] ecc_check;
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logic [38:0] error_mask;
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logic [38:0] din_plus_parity, dout_plus_parity;
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// Generate the ecc bits
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assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
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assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];
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assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
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assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
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assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
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assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
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// This is the parity bit
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assign ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0])) & ~sed_ded;
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assign single_ecc_error = en & (ecc_check[6:0] != 0) & ecc_check[6]; // this will never be on for sed_ded
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assign double_ecc_error = en & (ecc_check[6:0] != 0) & ~ecc_check[6]; // all errors in the sed_ded case will be recorded as DE
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// Generate the mask for error correctiong
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for (genvar i=1; i<40; i++) begin
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assign error_mask[i-1] = (ecc_check[5:0] == i);
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end
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// Generate the corrected data
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assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]};
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assign dout_plus_parity[38:0] = single_ecc_error ? (error_mask[38:0] ^ din_plus_parity[38:0]) : din_plus_parity[38:0];
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assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]};
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assign ecc_out[6:0] = {(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]};
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endmodule // rvecc_decode
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