156 lines
4.3 KiB
Verilog
156 lines
4.3 KiB
Verilog
// SPDX-License-Identifier: Apache-2.0
|
|
// Copyright 2020 Western Digital Corporation or its affiliates.
|
|
//
|
|
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
// you may not use this file except in compliance with the License.
|
|
// You may obtain a copy of the License at
|
|
//
|
|
// http://www.apache.org/licenses/LICENSE-2.0
|
|
//
|
|
// Unless required by applicable law or agreed to in writing, software
|
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
// See the License for the specific language governing permissions and
|
|
// limitations under the License.
|
|
//
|
|
|
|
|
|
`define E906
|
|
// `define SOC_TOP tb.x_soc
|
|
// `define RTL_MEM tb.x_soc.x_smem_ctrl
|
|
// `define ISA_MEM tb.x_pa_isa
|
|
`define JTAG_5
|
|
|
|
`define IAHB_LITE
|
|
`define RTL_IAHBL_MEM soc_sim.rvsoc.x_cpu_sub_system_ahb.x_iahb_mem_ctrl
|
|
|
|
`define DAHB_LITE
|
|
`define RTL_DAHBL_MEM soc_sim.rvsoc.x_cpu_sub_system_ahb.x_dahb_mem_ctrl
|
|
|
|
// `define CLK_PERIOD 10
|
|
// `define TCLK_PERIOD 33
|
|
// `define MAX_RUN_TIME 700000000
|
|
// `define clk tb.clk
|
|
// `define rst_b tb.rst_b
|
|
// `include "../cpu/environment.h"
|
|
// `timescale 1ns/100ps
|
|
|
|
|
|
module soc_sim (
|
|
input bit clk,
|
|
output jtag_tdo,
|
|
output jtag_tck,
|
|
output jtag_tms,
|
|
output jtag_tdi
|
|
);
|
|
|
|
wire rst;
|
|
|
|
bit [63:0] cycleCnt;
|
|
|
|
reg uart_tx;
|
|
wire uart_rx;
|
|
wire [ 7:0] gpioa;
|
|
|
|
wire jrst_b;
|
|
wire nrst_b;
|
|
|
|
wire [ 7:0] WriteData;
|
|
|
|
parameter MAX_CYCLES = 10_000_000_0;
|
|
|
|
assign rst = cycleCnt > 30 || cycleCnt < 10;
|
|
assign jrst_b = cycleCnt > 30 || cycleCnt < 10; // Very important
|
|
assign nrst_b = cycleCnt > 30 || cycleCnt < 10;
|
|
|
|
///////////////////////////////////////
|
|
// Memory Initialization
|
|
///////////////////////////////////////
|
|
integer i;
|
|
// reg [31:0] mem_data_size;
|
|
// reg [31:0] mem_inst_size;
|
|
|
|
reg [31:0] mem_inst_temp[65536];
|
|
// reg [31:0] mem_data_temp[65536];
|
|
|
|
initial begin
|
|
$display("\t******START TO LOAD PROGRAM******\n");
|
|
$readmemh("../work/case.pat", mem_inst_temp);
|
|
// $readmemh("./data.pat", mem_data_temp);
|
|
|
|
for (i = 0; i < 65536; i = i + 1) begin
|
|
`RTL_IAHBL_MEM.ram0.mem[i][7:0] = ((^mem_inst_temp[i][31:24]) === 1'bx ) ? 8'b0:mem_inst_temp[i][31:24];
|
|
`RTL_IAHBL_MEM.ram1.mem[i][7:0] = ((^mem_inst_temp[i][23:16]) === 1'bx ) ? 8'b0:mem_inst_temp[i][23:16];
|
|
`RTL_IAHBL_MEM.ram2.mem[i][7:0] = ((^mem_inst_temp[i][15: 8]) === 1'bx ) ? 8'b0:mem_inst_temp[i][15: 8];
|
|
`RTL_IAHBL_MEM.ram3.mem[i][7:0] = ((^mem_inst_temp[i][ 7: 0]) === 1'bx ) ? 8'b0:mem_inst_temp[i][ 7: 0];
|
|
end
|
|
|
|
for (i = 0; i <= 65536; i = i + 1) begin
|
|
`RTL_DAHBL_MEM.ram0.mem[i][7:0] = 8'b0;
|
|
`RTL_DAHBL_MEM.ram1.mem[i][7:0] = 8'b0;
|
|
`RTL_DAHBL_MEM.ram2.mem[i][7:0] = 8'b0;
|
|
`RTL_DAHBL_MEM.ram3.mem[i][7:0] = 8'b0;
|
|
end
|
|
for (i = 0; i <= 65536; i = i + 1) begin
|
|
`RTL_DAHBL_MEM.ram4.mem[i][7:0] = 8'b0;
|
|
`RTL_DAHBL_MEM.ram5.mem[i][7:0] = 8'b0;
|
|
`RTL_DAHBL_MEM.ram6.mem[i][7:0] = 8'b0;
|
|
`RTL_DAHBL_MEM.ram7.mem[i][7:0] = 8'b0;
|
|
end
|
|
end
|
|
|
|
|
|
integer fd;
|
|
|
|
always @(posedge clk) begin
|
|
cycleCnt <= cycleCnt + 1;
|
|
if (cycleCnt == MAX_CYCLES) begin
|
|
$display("Hit max cycle count (%0d) .. stopping", cycleCnt);
|
|
$finish;
|
|
end
|
|
if (WriteData[7:0] == 8'hff) begin
|
|
$display("\nFinished by program");
|
|
$display("TEST_PASSED");
|
|
$finish;
|
|
end else if (WriteData[7:0] == 8'h1) begin
|
|
$display("TEST_FAILED");
|
|
$finish;
|
|
end else begin
|
|
$fwrite(fd, "%c", WriteData[7:0]);
|
|
$write("%c", WriteData[7:0]);
|
|
end
|
|
end
|
|
|
|
initial begin
|
|
fd = $fopen("console.log", "w");
|
|
end
|
|
|
|
soc rvsoc (
|
|
.i_pad_clk (clk),
|
|
.i_pad_rst_b(rst),
|
|
|
|
.o_pad_jtg_tdo(jtag_tdo),
|
|
.i_pad_jtg_tclk(jtag_tck),
|
|
.i_pad_jtg_tms(jtag_tms),
|
|
.i_pad_jtg_tdi(jtag_tdi),
|
|
.i_pad_jtg_trst_b(jrst_b),
|
|
.i_pad_jtg_nrst_b(nrst_b),
|
|
.i_pad_uart0_sin(uart_tx),
|
|
.o_pad_uart0_sout(uart_rx),
|
|
.b_pad_gpio_porta(gpioa)
|
|
);
|
|
|
|
jtagdpi jtagdpi (
|
|
.clk_i (clk),
|
|
.rst_ni(rst),
|
|
|
|
.jtag_tck(jtag_tck),
|
|
.jtag_tms(jtag_tms),
|
|
.jtag_tdi(jtag_tdi),
|
|
.jtag_tdo(jtag_tdo),
|
|
.jtag_trst_n(),
|
|
.jtag_srst_n()
|
|
);
|
|
|
|
endmodule
|