65 lines
1.6 KiB
Verilog
65 lines
1.6 KiB
Verilog
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module tcm_mem_ram (
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// Inputs
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input clk0_i,
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input rst0_i,
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input [13:0] addr0_i,
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input [31:0] data0_i,
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input [ 3:0] wr0_i,
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input clk1_i,
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input rst1_i,
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input [13:0] addr1_i,
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input [31:0] data1_i,
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input [ 3:0] wr1_i
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// Outputs
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, output [31:0] data0_o,
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output [31:0] data1_o
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);
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integer memlog;
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initial begin
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memlog = $fopen("mem.log", "w");
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end
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//-----------------------------------------------------------------
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// Dual Port RAM 64KB
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// Mode: Read First
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//-----------------------------------------------------------------
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/* verilator lint_off MULTIDRIVEN */
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reg [31:0] ram[16383:0] /*verilator public*/;
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/* verilator lint_on MULTIDRIVEN */
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reg [31:0] ram_read0_q;
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reg [31:0] ram_read1_q;
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// Synchronous write
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always @(posedge clk0_i) begin
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if (wr0_i[0]) ram[addr0_i][7:0] <= data0_i[7:0];
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if (wr0_i[1]) ram[addr0_i][15:8] <= data0_i[15:8];
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if (wr0_i[2]) ram[addr0_i][23:16] <= data0_i[23:16];
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if (wr0_i[3]) ram[addr0_i][31:24] <= data0_i[31:24];
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ram_read0_q <= ram[addr0_i];
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$fwrite(memlog, "addr0: 0x%0h data: 0x%0h \n", addr0_i, ram[addr0_i]);
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end
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always @(posedge clk1_i) begin
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if (wr1_i[0]) ram[addr1_i][7:0] <= data1_i[7:0];
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if (wr1_i[1]) ram[addr1_i][15:8] <= data1_i[15:8];
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if (wr1_i[2]) ram[addr1_i][23:16] <= data1_i[23:16];
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if (wr1_i[3]) ram[addr1_i][31:24] <= data1_i[31:24];
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ram_read1_q <= ram[addr1_i];
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$fwrite(memlog, "addr1: 0x%0h data: 0x%0h \n", addr1_i, ram[addr1_i]);
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end
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assign data0_o = ram_read0_q;
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assign data1_o = ram_read1_q;
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endmodule
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