133 lines
3.9 KiB
Systemverilog
133 lines
3.9 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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`ifdef RV_BUILD_AHB_LITE
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module ahb_sif (
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input logic [63:0] HWDATA,
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input logic HCLK,
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input logic HSEL,
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input logic [3:0] HPROT,
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input logic HWRITE,
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input logic [1:0] HTRANS,
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input logic [2:0] HSIZE,
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input logic HREADY,
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input logic HRESETn,
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input logic [31:0] HADDR,
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input logic [2:0] HBURST,
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output logic HREADYOUT,
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output logic HRESP,
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output logic [63:0] HRDATA
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);
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// `define RV_ICCM_SADR 32'hee000000
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// `define RV_DCCM_SADR 32'hf0040000
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parameter OFFSET_ADDR = 32'h00000000;
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parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k
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logic write;
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logic [31:0] laddr, addr;
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logic [7:0] strb_lat;
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logic [63:0] rdata;
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bit [7:0] mem [bit[MEM_DEPTH-1:0]];
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bit [7:0] wscnt;
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int dws = 0;
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int iws = 0;
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bit dws_rand;
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bit iws_rand;
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bit ok;
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wire [7:0] strb = HSIZE == 3'b000 ? 8'h1 << HADDR[2:0] :
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HSIZE == 3'b001 ? 8'h3 << {HADDR[2:1],1'b0} :
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HSIZE == 3'b010 ? 8'hf << {HADDR[2],2'b0} : 8'hff;
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wire [31:0] RDDR = HADDR - OFFSET_ADDR;
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initial begin
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if ($value$plusargs("iws=%d", iws));
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if ($value$plusargs("dws=%d", dws));
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dws_rand = dws < 0;
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iws_rand = iws < 0;
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end
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always @ (negedge HCLK ) begin
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if(HREADY)
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addr = RDDR;
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if (write & HREADY) begin
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if(strb_lat[7]) mem[{laddr[MEM_DEPTH-1:3],3'd7}] = HWDATA[63:56];
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if(strb_lat[6]) mem[{laddr[MEM_DEPTH-1:3],3'd6}] = HWDATA[55:48];
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if(strb_lat[5]) mem[{laddr[MEM_DEPTH-1:3],3'd5}] = HWDATA[47:40];
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if(strb_lat[4]) mem[{laddr[MEM_DEPTH-1:3],3'd4}] = HWDATA[39:32];
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if(strb_lat[3]) mem[{laddr[MEM_DEPTH-1:3],3'd3}] = HWDATA[31:24];
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if(strb_lat[2]) mem[{laddr[MEM_DEPTH-1:3],3'd2}] = HWDATA[23:16];
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if(strb_lat[1]) mem[{laddr[MEM_DEPTH-1:3],3'd1}] = HWDATA[15:08];
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if(strb_lat[0]) mem[{laddr[MEM_DEPTH-1:3],3'd0}] = HWDATA[07:00];
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end
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if(HREADY & HSEL & |HTRANS) begin
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`ifdef VERILATOR
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if(iws_rand & ~HPROT[0])
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iws = $random & 15;
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if(dws_rand & HPROT[0])
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dws = $random & 15;
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`else
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if(iws_rand & ~HPROT[0])
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ok = std::randomize(iws) with {iws dist {0:=10, [1:3]:/2, [4:15]:/1};};
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if(dws_rand & HPROT[0])
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ok = std::randomize(dws) with {dws dist {0:=10, [1:3]:/2, [4:15]:/1};};
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`endif
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end
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end
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assign HRDATA = HREADY ? rdata : ~rdata;
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assign HREADYOUT = wscnt == 0;
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assign HRESP = 0;
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always @(posedge HCLK or negedge HRESETn) begin
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if(~HRESETn) begin
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laddr <= 32'b0;
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write <= 1'b0;
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rdata <= '0;
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wscnt <= 0;
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end
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else begin
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if(HREADY & HSEL) begin
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laddr <= RDDR;
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write <= HWRITE & |HTRANS;
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if(|HTRANS & ~HWRITE)
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rdata <= {mem[{addr[MEM_DEPTH-1:3],3'd7}],
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mem[{addr[MEM_DEPTH-1:3],3'd6}],
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mem[{addr[MEM_DEPTH-1:3],3'd5}],
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mem[{addr[MEM_DEPTH-1:3],3'd4}],
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mem[{addr[MEM_DEPTH-1:3],3'd3}],
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mem[{addr[MEM_DEPTH-1:3],3'd2}],
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mem[{addr[MEM_DEPTH-1:3],3'd1}],
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mem[{addr[MEM_DEPTH-1:3],3'd0}]};
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strb_lat <= strb;
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end
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end
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if(HREADY & HSEL & |HTRANS)
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wscnt <= HPROT[0] ? dws[7:0] : iws[7:0];
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else if(wscnt != 0)
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wscnt <= wscnt-1;
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end
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endmodule
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`endif
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