340 lines
18 KiB
Systemverilog
340 lines
18 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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//
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// Owner:
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// Function: LSU control
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// Comments:
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//
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//
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// DC1 -> DC2 -> DC3 -> DC4 (Commit)
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//
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//********************************************************************************
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module lsu_lsc_ctl
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import swerv_types::*;
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(
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input logic rst_l,
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input logic clk,
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// clocks per pipe
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input logic lsu_c1_dc4_clk,
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input logic lsu_c1_dc5_clk,
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input logic lsu_c2_dc4_clk,
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input logic lsu_c2_dc5_clk,
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// freez clocks per pipe
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input logic lsu_freeze_c1_dc1_clken,
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input logic lsu_freeze_c1_dc2_clken,
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input logic lsu_freeze_c1_dc2_clk,
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input logic lsu_freeze_c1_dc3_clken,
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input logic lsu_freeze_c1_dc3_clk,
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input logic lsu_freeze_c2_dc1_clk,
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input logic lsu_freeze_c2_dc2_clk,
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input logic lsu_freeze_c2_dc3_clk,
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input logic lsu_store_c1_dc1_clken,
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input logic lsu_store_c1_dc2_clken,
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input logic lsu_store_c1_dc3_clken,
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input logic lsu_store_c1_dc4_clk,
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input logic lsu_store_c1_dc5_clk,
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input logic [31:0] i0_result_e4_eff,
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input logic [31:0] i1_result_e4_eff,
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input logic [31:0] i0_result_e2,
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input logic ld_bus_error_dc3,
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input logic [31:0] ld_bus_error_addr_dc3,
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input logic lsu_single_ecc_error_dc3,
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input logic lsu_single_ecc_error_dc5,
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input logic lsu_double_ecc_error_dc3,
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input logic lsu_freeze_dc3,
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input logic lsu_i0_valid_dc3,
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input logic flush_dc2_up,
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input logic flush_dc3,
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input logic flush_dc4,
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input logic flush_dc5,
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input logic [31:0] exu_lsu_rs1_d, // address
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input logic [31:0] exu_lsu_rs2_d, // store data
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input lsu_pkt_t lsu_p, // lsu control packet
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input logic [11:0] dec_lsu_offset_d,
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input logic [31:0] picm_mask_data_dc3,
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input logic [31:0] lsu_ld_data_dc3,
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input logic [31:0] lsu_ld_data_corr_dc3,
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input logic [31:0] bus_read_data_dc3,
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output logic [31:0] lsu_result_dc3,
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output logic [31:0] lsu_result_corr_dc4, // This is the ECC corrected data going to RF
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// lsu address down the pipe
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output logic [31:0] lsu_addr_dc1,
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output logic [31:0] lsu_addr_dc2,
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output logic [31:0] lsu_addr_dc3,
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output logic [31:0] lsu_addr_dc4,
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output logic [31:0] lsu_addr_dc5,
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// lsu address down the pipe - needed to check unaligned
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output logic [31:0] end_addr_dc1,
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output logic [31:0] end_addr_dc2,
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output logic [31:0] end_addr_dc3,
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output logic [31:0] end_addr_dc4,
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output logic [31:0] end_addr_dc5,
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// store data down the pipe
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output logic [63:0] store_data_dc2,
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output logic [63:0] store_data_dc3,
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output logic [31:0] store_data_dc4,
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output logic [31:0] store_data_dc5,
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input logic [31:0] dec_tlu_mrac_ff,
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output logic lsu_exc_dc2,
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output lsu_error_pkt_t lsu_error_pkt_dc3,
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output logic lsu_single_ecc_error_incr, // Increment the counter for Single ECC error
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output logic lsu_freeze_external_ints_dc3,
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output logic is_sideeffects_dc2,
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output logic is_sideeffects_dc3,
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output logic lsu_commit_dc5,
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// address in dccm/pic/external per pipe stage
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output logic addr_in_dccm_dc1,
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output logic addr_in_dccm_dc2,
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output logic addr_in_dccm_dc3,
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output logic addr_in_pic_dc1,
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output logic addr_in_pic_dc2,
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output logic addr_in_pic_dc3,
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output logic addr_external_dc2,
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output logic addr_external_dc3,
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output logic addr_external_dc4,
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output logic addr_external_dc5,
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// DMA slave
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input logic dma_dccm_req,
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input logic [31:0] dma_mem_addr,
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input logic [2:0] dma_mem_sz,
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input logic dma_mem_write,
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input logic [63:0] dma_mem_wdata,
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// Store buffer related signals
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output lsu_pkt_t lsu_pkt_dc1,
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output lsu_pkt_t lsu_pkt_dc2,
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output lsu_pkt_t lsu_pkt_dc3,
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output lsu_pkt_t lsu_pkt_dc4,
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output lsu_pkt_t lsu_pkt_dc5,
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input logic scan_mode
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);
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`include "global.h"
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logic [31:0] full_addr_dc1;
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logic [31:0] full_end_addr_dc1;
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logic [31:0] lsu_rs1_d;
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logic [11:0] lsu_offset_d;
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logic [31:0] rs1_dc1;
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logic [11:0] offset_dc1;
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logic [12:0] end_addr_offset_dc1;
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logic [31:0] lsu_ld_datafn_dc3;
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logic [31:0] lsu_ld_datafn_corr_dc3;
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logic [31:0] lsu_result_corr_dc3;
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logic [2:0] addr_offset_dc1;
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logic [63:0] dma_mem_wdata_shifted;
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logic addr_external_dc1;
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logic access_fault_dc1, misaligned_fault_dc1;
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logic access_fault_dc2, misaligned_fault_dc2;
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logic access_fault_dc3, misaligned_fault_dc3;
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logic [63:0] store_data_d;
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logic [63:0] store_data_dc1;
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logic [63:0] store_data_pre_dc2;
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logic [63:0] store_data_pre_dc3;
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logic [63:0] store_data_dc2_in;
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logic [31:0] rs1_dc1_raw;
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lsu_pkt_t dma_pkt_d;
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lsu_pkt_t lsu_pkt_dc1_in, lsu_pkt_dc2_in, lsu_pkt_dc3_in, lsu_pkt_dc4_in, lsu_pkt_dc5_in;
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// Premux the rs1/offset for dma
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assign lsu_rs1_d[31:0] = dma_dccm_req ? dma_mem_addr[31:0] : exu_lsu_rs1_d[31:0];
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assign lsu_offset_d[11:0] = dec_lsu_offset_d[11:0] & ~{12{dma_dccm_req}};
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rvdffe #(32) rs1ff (.*, .din(lsu_rs1_d[31:0]), .dout(rs1_dc1_raw[31:0]), .en(lsu_freeze_c1_dc1_clken));
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rvdffe #(12) offsetff (.*, .din(lsu_offset_d[11:0]), .dout(offset_dc1[11:0]), .en(lsu_freeze_c1_dc1_clken));
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assign rs1_dc1[31:0] = (lsu_pkt_dc1.load_ldst_bypass_c1) ? lsu_result_dc3[31:0] : rs1_dc1_raw[31:0];
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// generate the ls address
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// need to refine this is memory is only 128KB
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rvlsadder lsadder (.rs1(rs1_dc1[31:0]),
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.offset(offset_dc1[11:0]),
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.dout(full_addr_dc1[31:0])
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);
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// Module to generate the memory map of the address
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lsu_addrcheck addrcheck (
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.start_addr_dc1(full_addr_dc1[31:0]),
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.end_addr_dc1(full_end_addr_dc1[31:0]),
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.*
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);
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// Calculate start/end address for load/store
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assign addr_offset_dc1[2:0] = ({3{lsu_pkt_dc1.half}} & 3'b01) | ({3{lsu_pkt_dc1.word}} & 3'b11) | ({3{lsu_pkt_dc1.dword}} & 3'b111);
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assign end_addr_offset_dc1[12:0] = {offset_dc1[11],offset_dc1[11:0]} + {9'b0,addr_offset_dc1[2:0]};
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assign full_end_addr_dc1[31:0] = rs1_dc1[31:0] + {{19{end_addr_offset_dc1[12]}},end_addr_offset_dc1[12:0]};
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assign end_addr_dc1[31:0] = full_end_addr_dc1[31:0];
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assign lsu_exc_dc2 = access_fault_dc2 | misaligned_fault_dc2;
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assign lsu_freeze_external_ints_dc3 = lsu_freeze_dc3 & is_sideeffects_dc3;
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// Increment the single bit ecc counter
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assign lsu_single_ecc_error_incr = lsu_single_ecc_error_dc5 & (lsu_commit_dc5 | lsu_pkt_dc5.dma);
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// Generate exception packet
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assign lsu_error_pkt_dc3.exc_valid = (access_fault_dc3 | misaligned_fault_dc3 | ld_bus_error_dc3 | lsu_double_ecc_error_dc3) & lsu_pkt_dc3.valid & ~lsu_pkt_dc3.dma & ~flush_dc3;
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assign lsu_error_pkt_dc3.single_ecc_error = lsu_single_ecc_error_dc3 & ~(access_fault_dc3 | misaligned_fault_dc3 | lsu_double_ecc_error_dc3);
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assign lsu_error_pkt_dc3.inst_type = lsu_pkt_dc3.store;
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assign lsu_error_pkt_dc3.dma_valid = lsu_pkt_dc3.dma;
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assign lsu_error_pkt_dc3.inst_pipe = ~lsu_i0_valid_dc3;
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assign lsu_error_pkt_dc3.exc_type = ~misaligned_fault_dc3;
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// assign lsu_error_pkt_dc3.addr[31:0] = (access_fault_dc3 | misaligned_fault_dc3) ? lsu_addr_dc3[31:0] : ld_bus_error_addr_dc3[31:0];
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assign lsu_error_pkt_dc3.addr[31:0] = lsu_addr_dc3[31:0];
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//Create DMA packet
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assign dma_pkt_d.valid = dma_dccm_req;
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assign dma_pkt_d.dma = 1'b1;
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assign dma_pkt_d.unsign = '0;
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assign dma_pkt_d.store = dma_mem_write;
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assign dma_pkt_d.load = ~dma_mem_write;
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assign dma_pkt_d.by = (dma_mem_sz[2:0] == 3'b0);
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assign dma_pkt_d.half = (dma_mem_sz[2:0] == 3'b1);
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assign dma_pkt_d.word = (dma_mem_sz[2:0] == 3'b10);
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assign dma_pkt_d.dword = (dma_mem_sz[2:0] == 3'b11);
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assign dma_pkt_d.load_ldst_bypass_c1 = '0;
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assign dma_pkt_d.store_data_bypass_c1 = '0;
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assign dma_pkt_d.store_data_bypass_c2 = '0;
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assign dma_pkt_d.store_data_bypass_i0_e2_c2 = '0;
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assign dma_pkt_d.store_data_bypass_e4_c1 = '0;
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assign dma_pkt_d.store_data_bypass_e4_c2 = '0;
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assign dma_pkt_d.store_data_bypass_e4_c3 = '0;
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always_comb begin
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lsu_pkt_dc1_in = dma_dccm_req ? dma_pkt_d : lsu_p;
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lsu_pkt_dc2_in = lsu_pkt_dc1;
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lsu_pkt_dc3_in = lsu_pkt_dc2;
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lsu_pkt_dc4_in = lsu_pkt_dc3;
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lsu_pkt_dc5_in = lsu_pkt_dc4;
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lsu_pkt_dc1_in.valid = (lsu_p.valid & ~flush_dc2_up) | dma_dccm_req;
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lsu_pkt_dc2_in.valid = lsu_pkt_dc1.valid & ~(flush_dc2_up & ~lsu_pkt_dc1.dma);
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lsu_pkt_dc3_in.valid = lsu_pkt_dc2.valid & ~(flush_dc2_up & ~lsu_pkt_dc2.dma);
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lsu_pkt_dc4_in.valid = lsu_pkt_dc3.valid & ~(flush_dc3 & ~lsu_pkt_dc3.dma) & ~lsu_freeze_dc3;
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lsu_pkt_dc5_in.valid = lsu_pkt_dc4.valid & ~(flush_dc4 & ~lsu_pkt_dc4.dma);
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end
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// C2 clock for valid and C1 for other bits of packet
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rvdff #(1) lsu_pkt_vlddc1ff (.*, .din(lsu_pkt_dc1_in.valid), .dout(lsu_pkt_dc1.valid), .clk(lsu_freeze_c2_dc1_clk));
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rvdff #(1) lsu_pkt_vlddc2ff (.*, .din(lsu_pkt_dc2_in.valid), .dout(lsu_pkt_dc2.valid), .clk(lsu_freeze_c2_dc2_clk));
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rvdff #(1) lsu_pkt_vlddc3ff (.*, .din(lsu_pkt_dc3_in.valid), .dout(lsu_pkt_dc3.valid), .clk(lsu_freeze_c2_dc3_clk));
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rvdff #(1) lsu_pkt_vlddc4ff (.*, .din(lsu_pkt_dc4_in.valid), .dout(lsu_pkt_dc4.valid), .clk(lsu_c2_dc4_clk));
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rvdff #(1) lsu_pkt_vlddc5ff (.*, .din(lsu_pkt_dc5_in.valid), .dout(lsu_pkt_dc5.valid), .clk(lsu_c2_dc5_clk));
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rvdffe #($bits(lsu_pkt_t)-1) lsu_pkt_dc1ff (.*, .din(lsu_pkt_dc1_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc1[$bits(lsu_pkt_t)-1:1]), .en(lsu_freeze_c1_dc1_clken));
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rvdffe #($bits(lsu_pkt_t)-1) lsu_pkt_dc2ff (.*, .din(lsu_pkt_dc2_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc2[$bits(lsu_pkt_t)-1:1]), .en(lsu_freeze_c1_dc2_clken));
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rvdffe #($bits(lsu_pkt_t)-1) lsu_pkt_dc3ff (.*, .din(lsu_pkt_dc3_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc3[$bits(lsu_pkt_t)-1:1]), .en(lsu_freeze_c1_dc3_clken));
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rvdff #($bits(lsu_pkt_t)-1) lsu_pkt_dc4ff (.*, .din(lsu_pkt_dc4_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc4[$bits(lsu_pkt_t)-1:1]), .clk(lsu_c1_dc4_clk));
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rvdff #($bits(lsu_pkt_t)-1) lsu_pkt_dc5ff (.*, .din(lsu_pkt_dc5_in[$bits(lsu_pkt_t)-1:1]), .dout(lsu_pkt_dc5[$bits(lsu_pkt_t)-1:1]), .clk(lsu_c1_dc5_clk));
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assign lsu_ld_datafn_dc3[31:0] = addr_external_dc3 ? bus_read_data_dc3[31:0] : lsu_ld_data_dc3[31:0];
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assign lsu_ld_datafn_corr_dc3[31:0] = addr_external_dc3 ? bus_read_data_dc3[31:0] : lsu_ld_data_corr_dc3[31:0];
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// this result must look at prior stores and merge them in
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assign lsu_result_dc3[31:0] = ({32{ lsu_pkt_dc3.unsign & lsu_pkt_dc3.by }} & {24'b0,lsu_ld_datafn_dc3[7:0]}) |
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({32{ lsu_pkt_dc3.unsign & lsu_pkt_dc3.half}} & {16'b0,lsu_ld_datafn_dc3[15:0]}) |
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({32{~lsu_pkt_dc3.unsign & lsu_pkt_dc3.by }} & {{24{ lsu_ld_datafn_dc3[7]}}, lsu_ld_datafn_dc3[7:0]}) |
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({32{~lsu_pkt_dc3.unsign & lsu_pkt_dc3.half}} & {{16{ lsu_ld_datafn_dc3[15]}},lsu_ld_datafn_dc3[15:0]}) |
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({32{lsu_pkt_dc3.word}} & lsu_ld_datafn_dc3[31:0]);
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assign lsu_result_corr_dc3[31:0] = ({32{ lsu_pkt_dc3.unsign & lsu_pkt_dc3.by }} & {24'b0,lsu_ld_datafn_corr_dc3[7:0]}) |
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({32{ lsu_pkt_dc3.unsign & lsu_pkt_dc3.half}} & {16'b0,lsu_ld_datafn_corr_dc3[15:0]}) |
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({32{~lsu_pkt_dc3.unsign & lsu_pkt_dc3.by }} & {{24{ lsu_ld_datafn_corr_dc3[7]}}, lsu_ld_datafn_corr_dc3[7:0]}) |
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({32{~lsu_pkt_dc3.unsign & lsu_pkt_dc3.half}} & {{16{ lsu_ld_datafn_corr_dc3[15]}},lsu_ld_datafn_corr_dc3[15:0]}) |
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({32{lsu_pkt_dc3.word}} & lsu_ld_datafn_corr_dc3[31:0]);
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// absence load/store all 0's
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assign lsu_addr_dc1[31:0] = full_addr_dc1[31:0];
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// Interrupt as a flush source allows the WB to occur
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assign lsu_commit_dc5 = lsu_pkt_dc5.valid & (lsu_pkt_dc5.store | lsu_pkt_dc5.load) & ~flush_dc5 & ~lsu_pkt_dc5.dma;
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assign dma_mem_wdata_shifted[63:0] = dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}; // Shift the dma data to lower bits to make it consistent to lsu stores
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assign store_data_d[63:0] = dma_dccm_req ? dma_mem_wdata_shifted[63:0] : {32'b0,exu_lsu_rs2_d[31:0]};
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assign store_data_dc2_in[63:32] = store_data_dc1[63:32];
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assign store_data_dc2_in[31:0] = (lsu_pkt_dc1.store_data_bypass_c1) ? lsu_result_dc3[31:0] :
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(lsu_pkt_dc1.store_data_bypass_e4_c1[1]) ? i1_result_e4_eff[31:0] :
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(lsu_pkt_dc1.store_data_bypass_e4_c1[0]) ? i0_result_e4_eff[31:0] : store_data_dc1[31:0];
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assign store_data_dc2[63:32] = store_data_pre_dc2[63:32];
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assign store_data_dc2[31:0] = (lsu_pkt_dc2.store_data_bypass_i0_e2_c2) ? i0_result_e2[31:0] :
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(lsu_pkt_dc2.store_data_bypass_c2) ? lsu_result_dc3[31:0] :
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(lsu_pkt_dc2.store_data_bypass_e4_c2[1]) ? i1_result_e4_eff[31:0] :
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(lsu_pkt_dc2.store_data_bypass_e4_c2[0]) ? i0_result_e4_eff[31:0] : store_data_pre_dc2[31:0];
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assign store_data_dc3[63:32] = store_data_pre_dc3[63:32];
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assign store_data_dc3[31:0] = (picm_mask_data_dc3[31:0] | {32{~addr_in_pic_dc3}}) &
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((lsu_pkt_dc3.store_data_bypass_e4_c3[1]) ? i1_result_e4_eff[31:0] :
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(lsu_pkt_dc3.store_data_bypass_e4_c3[0]) ? i0_result_e4_eff[31:0] : store_data_pre_dc3[31:0]);
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rvdff #(32) lsu_result_corr_dc4ff (.*, .din(lsu_result_corr_dc3[31:0]), .dout(lsu_result_corr_dc4[31:0]), .clk(lsu_c1_dc4_clk));
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rvdffe #(64) sddc1ff (.*, .din(store_data_d[63:0]), .dout(store_data_dc1[63:0]), .en(lsu_store_c1_dc1_clken));
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rvdffe #(64) sddc2ff (.*, .din(store_data_dc2_in[63:0]), .dout(store_data_pre_dc2[63:0]), .en(lsu_store_c1_dc2_clken));
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rvdffe #(64) sddc3ff (.*, .din(store_data_dc2[63:0]), .dout(store_data_pre_dc3[63:0]), .en(~lsu_freeze_dc3 & lsu_store_c1_dc3_clken) );
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rvdff #(32) sddc4ff (.*, .din(store_data_dc3[31:0]), .dout(store_data_dc4[31:0]), .clk(lsu_store_c1_dc4_clk));
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rvdff #(32) sddc5ff (.*, .din(store_data_dc4[31:0]), .dout(store_data_dc5[31:0]), .clk(lsu_store_c1_dc5_clk));
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rvdffe #(32) sadc2ff (.*, .din(lsu_addr_dc1[31:0]), .dout(lsu_addr_dc2[31:0]), .en(lsu_freeze_c1_dc2_clken));
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rvdffe #(32) sadc3ff (.*, .din(lsu_addr_dc2[31:0]), .dout(lsu_addr_dc3[31:0]), .en(lsu_freeze_c1_dc3_clken));
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rvdff #(32) sadc4ff (.*, .din(lsu_addr_dc3[31:0]), .dout(lsu_addr_dc4[31:0]), .clk(lsu_c1_dc4_clk));
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rvdff #(32) sadc5ff (.*, .din(lsu_addr_dc4[31:0]), .dout(lsu_addr_dc5[31:0]), .clk(lsu_c1_dc5_clk));
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rvdffe #(32) end_addr_dc2ff (.*, .din(end_addr_dc1[31:0]), .dout(end_addr_dc2[31:0]), .en(lsu_freeze_c1_dc2_clken));
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rvdffe #(32) end_addr_dc3ff (.*, .din(end_addr_dc2[31:0]), .dout(end_addr_dc3[31:0]), .en(lsu_freeze_c1_dc3_clken));
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rvdff #(32) end_addr_dc4ff (.*, .din(end_addr_dc3[31:0]), .dout(end_addr_dc4[31:0]), .clk(lsu_c1_dc4_clk));
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rvdff #(32) end_addr_dc5ff (.*, .din(end_addr_dc4[31:0]), .dout(end_addr_dc5[31:0]), .clk(lsu_c1_dc5_clk));
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rvdff #(1) addr_in_dccm_dc2ff(.din(addr_in_dccm_dc1), .dout(addr_in_dccm_dc2), .clk(lsu_freeze_c1_dc2_clk), .*);
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rvdff #(1) addr_in_dccm_dc3ff(.din(addr_in_dccm_dc2), .dout(addr_in_dccm_dc3), .clk(lsu_freeze_c1_dc3_clk), .*);
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rvdff #(1) addr_in_pic_dc2ff(.din(addr_in_pic_dc1), .dout(addr_in_pic_dc2), .clk(lsu_freeze_c1_dc2_clk), .*);
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rvdff #(1) addr_in_pic_dc3ff(.din(addr_in_pic_dc2), .dout(addr_in_pic_dc3), .clk(lsu_freeze_c1_dc3_clk), .*);
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rvdff #(1) addr_external_dc2ff(.din(addr_external_dc1), .dout(addr_external_dc2), .clk(lsu_freeze_c1_dc2_clk), .*);
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rvdff #(1) addr_external_dc3ff(.din(addr_external_dc2), .dout(addr_external_dc3), .clk(lsu_freeze_c1_dc3_clk), .*);
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rvdff #(1) addr_external_dc4ff(.din(addr_external_dc3), .dout(addr_external_dc4), .clk(lsu_c1_dc4_clk), .*);
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rvdff #(1) addr_external_dc5ff(.din(addr_external_dc4), .dout(addr_external_dc5), .clk(lsu_c1_dc5_clk), .*);
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rvdff #(1) access_fault_dc2ff(.din(access_fault_dc1), .dout(access_fault_dc2), .clk(lsu_freeze_c1_dc2_clk), .*);
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rvdff #(1) access_fault_dc3ff(.din(access_fault_dc2), .dout(access_fault_dc3), .clk(lsu_freeze_c1_dc3_clk), .*);
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rvdff #(1) misaligned_fault_dc2ff(.din(misaligned_fault_dc1), .dout(misaligned_fault_dc2), .clk(lsu_freeze_c1_dc2_clk), .*);
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rvdff #(1) misaligned_fault_dc3ff(.din(misaligned_fault_dc2), .dout(misaligned_fault_dc3), .clk(lsu_freeze_c1_dc3_clk), .*);
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endmodule
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