149 lines
3.7 KiB
Plaintext
149 lines
3.7 KiB
Plaintext
CAPI=2:
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name : chipsalliance.org:cores:SweRV_EH1:1.8
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filesets:
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rtl:
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files:
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- design/include/swerv_types.sv
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- design/lib/beh_lib.sv
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- design/mem.sv
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- design/pic_ctrl.sv
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- design/dma_ctrl.sv
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- design/ifu/ifu_aln_ctl.sv
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- design/ifu/ifu_compress_ctl.sv
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- design/ifu/ifu_ifc_ctl.sv
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- design/ifu/ifu_bp_ctl.sv
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- design/ifu/ifu_ic_mem.sv
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- design/ifu/ifu_mem_ctl.sv
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- design/ifu/ifu_iccm_mem.sv
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- design/ifu/ifu.sv
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- design/dec/dec_decode_ctl.sv
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- design/dec/dec_gpr_ctl.sv
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- design/dec/dec_ib_ctl.sv
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- design/dec/dec_tlu_ctl.sv
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- design/dec/dec_trigger.sv
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- design/dec/dec.sv
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- design/exu/exu_alu_ctl.sv
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- design/exu/exu_mul_ctl.sv
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- design/exu/exu_div_ctl.sv
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- design/exu/exu.sv
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- design/lsu/lsu.sv
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- design/lsu/lsu_bus_buffer.sv
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- design/lsu/lsu_clkdomain.sv
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- design/lsu/lsu_addrcheck.sv
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- design/lsu/lsu_lsc_ctl.sv
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- design/lsu/lsu_stbuf.sv
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- design/lsu/lsu_bus_intf.sv
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- design/lsu/lsu_ecc.sv
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- design/lsu/lsu_dccm_mem.sv
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- design/lsu/lsu_dccm_ctl.sv
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- design/lsu/lsu_trigger.sv
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- design/dbg/dbg.sv
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- design/dmi/dmi_wrapper.v
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- design/dmi/dmi_jtag_to_core_sync.v
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- design/dmi/rvjtag_tap.sv
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- design/lib/mem_lib.sv
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- design/lib/ahb_to_axi4.sv
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- design/lib/axi4_to_ahb.sv
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- design/swerv.sv
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- design/swerv_wrapper.sv
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file_type : systemVerilogSource
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includes:
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files:
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- design/include/build.h : {is_include_file : true}
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- design/include/global.h : {is_include_file : true}
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file_type : systemVerilogSource
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mem_init:
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files:
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- testbench/hex/data.hex : {copyto : data.hex}
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- testbench/hex/program.hex : {copyto : program.hex}
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file_type : user
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tb:
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files: [testbench/ahb_sif.sv, testbench/tb_top.sv]
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file_type : systemVerilogSource
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verilator_tb:
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files : [testbench/test_tb_top.cpp : {file_type : cppSource}]
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vivado_tcl: {files: [tools/vivado.tcl : {file_type : tclSource}]}
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targets:
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default:
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filesets :
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- includes
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- rtl
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- "tool_vivado ? (vivado_tcl)"
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lint:
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default_tool: verilator
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filesets : [includes, rtl]
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generate : [swerv_default_config]
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tools:
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verilator :
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mode : lint-only
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toplevel : swerv_wrapper
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sim:
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default_tool : verilator
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filesets :
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- includes
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- rtl
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- mem_init
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- tb
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- "tool_verilator? (verilator_tb)"
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generate : [swerv_ahb_config]
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tools:
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modelsim:
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vlog_options :
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- -mfcu
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- -cuautoname=du
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- config/common_defines.vh
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rivierapro:
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vlog_options :
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- config/common_defines.vh
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- "-err VCP2694 W1"
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compilation_mode : common
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verilator:
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verilator_options : [--trace, -Wno-fatal]
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toplevel : tb_top
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synth:
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default_tool : vivado
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filesets : [includes, rtl, "tool_vivado ? (vivado_tcl)"]
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generate : [swerv_fpga_config]
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tools:
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vivado:
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part : xc7a100tcsg324-1
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pnr : none
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toplevel : swerv_wrapper
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generate:
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swerv_ahb_config:
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generator: swerv_config
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position : first
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parameters:
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args : ['-ahb_lite', -unset=assert_on]
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swerv_default_config:
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generator: swerv_config
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position : first
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parameters:
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args : [-unset=assert_on]
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swerv_fpga_config:
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generator: swerv_config
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position : first
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parameters:
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args : [-unset=assert_on, -set=fpga_optimize=1]
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generators:
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swerv_config:
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interpreter: python3
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command: configs/swerv_config_gen.py
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description : Create a SweRV configuration. Note! Only supports the default config
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