161 lines
6.6 KiB
Tcl
161 lines
6.6 KiB
Tcl
/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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set ClkMargin 1
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################################################################################
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# GLOBAL UNITS
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################################################################################
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set_units -time ns
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set_units -capacitance pF
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set_case_analysis 0 [get_ports pad_yy_scan_mode]
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set_case_analysis 0 [get_ports pad_yy_icg_scan_en]
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set_case_analysis 0 [get_ports pad_yy_icg_scan_en]
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# CPU_CLOCK
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#set CPUClkFrequency 150
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set CPUClkFrequency 1000
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set CPUClkName CPU_CLOCK
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set CPUClkPoint pll_core_cpuclk
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create_clock -period [expr 1000.0/($CPUClkFrequency*$ClkMargin)] -name $CPUClkName [get_ports pll_core_cpuclk]
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# JTG_CLOCK
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set JTAGClkFrequency 25
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set JTAGClkName JTG_CLOCK
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set JTAGClkPoint pad_had_jtg_tclk
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create_clock -period [expr 1000.0/($JTAGClkFrequency*$ClkMargin)] -name $JTAGClkName [get_ports pad_had_jtg_tclk]
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set CPU_PERIOD [expr 1000.0/($CPUClkFrequency*$ClkMargin)]
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set JTG_PERIOD [expr 1000.0/($JTAGClkFrequency*$ClkMargin)]
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set CLK_INPUTS [get_ports {*clk *clock *tck}]
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set DATA_INPUTS [remove_from_collection [all_inputs] $CLK_INPUTS]
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# CLIC_CLKx_pa_tcipif_top.x_pa_clic_top.x_clicreg_clk.clk_out
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set CLIC_CLK "yes"
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if {$CLIC_CLK == "yes"} {
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create_generated_clock -name CLIC_CLK -source [get_ports pll_core_cpuclk] -edges {1 2 5} [filter [get_flat_pins x_pa_tcipif_top*x_pa_clic_top*x_clicreg_clk*x_gated_clk_cell/*] direction==out]
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set_multicycle_path -from CPU_CLOCK -to CLIC_CLK -setup 2 -start
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set_multicycle_path -from CPU_CLOCK -to CLIC_CLK -hold 1 -start
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set_multicycle_path -from CLIC_CLK -to CPU_CLOCK -setup 2 -end
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set_multicycle_path -from CLIC_CLK -to CPU_CLOCK -hold 1 -end
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}
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set DC_setup_uncertainty 0.2
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set DC_hold_uncertainty 0.08
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set DC_max_fanout 32
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set DC_max_transition 0.5
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if {$PROCESS == "UMC28"} {
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set DC_setup_uncertainty 0.3
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}
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set_max_fanout $DC_max_fanout [current_design]
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set_max_transition $DC_max_transition [current_design]
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set_input_transition 0.1 $CLK_INPUTS
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set_clock_uncertainty -setup $DC_setup_uncertainty [all_clocks]
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set_clock_uncertainty -hold $DC_hold_uncertainty [all_clocks]
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if {$CLIC_CLK == "yes"} {
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set CLIC_INPUTS [get_ports {pad_clic_int_vld* pad_cpu_ext_int_b pad_cpu_sys_cnt*}]
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set DATA_INPUTS [remove_from_collection $DATA_INPUTS $CLIC_INPUTS]
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}
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################################################################################
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# Ports Constrains
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################################################################################
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#JTAG Ports
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set JTAG_INPUTS [get_ports {pad_had_jtg_*}]
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set JTAG_OUTPUTS [get_ports {had_pad_jtg_*}]
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set DATA_INPUTS [remove_from_collection $DATA_INPUTS $JTAG_INPUTS]
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set DATA_OUTPUTS [remove_from_collection [all_outputs] $JTAG_OUTPUTS]
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#JTAG Ports
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set JTAG_INPUTS [get_ports {pad_had_jtg_*}]
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set JTAG_OUTPUTS [get_ports {had_pad_jtg_*}]
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set DATA_INPUTS [remove_from_collection $DATA_INPUTS $JTAG_INPUTS]
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set DATA_OUTPUTS [remove_from_collection [all_outputs] $JTAG_OUTPUTS]
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set LOOSE_BUS_CONSTRAIN "no"
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if {$LOOSE_BUS_CONSTRAIN == "yes"} {
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set_false_path -from [all_inputs]
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set_false_path -to [all_outputs]
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} else {
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#Jtag
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set_input_delay -max [expr $JTG_PERIOD*0.4] -clock $JTAGClkName $JTAG_INPUTS
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set_input_delay -min [expr $JTG_PERIOD*0.2] -clock $JTAGClkName $JTAG_INPUTS
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set_output_delay -max [expr $JTG_PERIOD*0.4] -clock $JTAGClkName $JTAG_OUTPUTS
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set_output_delay -min [expr $JTG_PERIOD*0.2] -clock $JTAGClkName $JTAG_OUTPUTS
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#Default IO
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set_input_delay -max [expr $CPU_PERIOD*0.4] -clock $CPUClkName $DATA_INPUTS
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set_input_delay -min [expr $CPU_PERIOD*0.2] -clock $CPUClkName $DATA_INPUTS
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set_output_delay -max [expr $CPU_PERIOD*0.4] -clock $CPUClkName $DATA_OUTPUTS
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set_output_delay -min [expr $CPU_PERIOD*0.2] -clock $CPUClkName $DATA_OUTPUTS
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#Timing Critical Ports
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set_input_delay -max [expr $CPU_PERIOD*0.6] -clock $CPUClkName [get_ports {*hrdata*}]
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set_input_delay -min [expr $CPU_PERIOD*0.3] -clock $CPUClkName [get_ports {*hrdata*}]
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set_output_delay -max [expr $CPU_PERIOD*0.6] -clock $CPUClkName [get_ports {*haddr* biu_pad_*}]
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set_output_delay -min [expr $CPU_PERIOD*0.3] -clock $CPUClkName [get_ports {*haddr* biu_pad_*}]
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}
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set_output_delay 0 -clock CPU_CLOCK [get_ports rtu_pad_inst_retire*]
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set_output_delay 0 -clock CPU_CLOCK [get_ports rtu_pad_inst_split*]
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set_output_delay 0 -clock CPU_CLOCK [get_ports rtu_pad_retire_pc*]
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set_output_delay 0 -clock CPU_CLOCK [get_ports rtu_pad_wb_data*]
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set_output_delay 0 -clock CPU_CLOCK [get_ports rtu_pad_wb_preg*]
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set_output_delay 0 -clock CPU_CLOCK [get_ports rtu_pad_wb_vld*]
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set_output_delay 0 -clock CPU_CLOCK [get_ports lsu_pad_sc_pass*]
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set_output_delay 0 -clock CPU_CLOCK [get_ports cp0_pad_mcause*]
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set_output_delay 0 -clock CPU_CLOCK [get_ports cp0_pad_mintstatus*]
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set_output_delay 0 -clock CPU_CLOCK [get_ports cp0_pad_mstatus*]
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set_false_path -from CPU_CLOCK -to JTG_CLOCK
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set_false_path -from JTG_CLOCK -to CPU_CLOCK
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set_false_path -from [get_ports pad_cpu_rst_b]
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set_false_path -from [get_ports pad_had_rst_b]
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set_false_path -from [get_ports {pad_*_dahbl_base* pad_*_dahbl_mask* pad_*_iahbl_base* pad_*_iahbl_mask*}]
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set CPUCLK_PER [expr 1000.0/($CPUClkFrequency*$ClkMargin)]
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set Gateclk_cell [remove_from_collection [get_cells -hierarchical * -filter "ref_name =~ *CKLNQD1BWP*"] [get_cells -hierarchical * -filter "@full_name=~ *x_clic_clk*"]]
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if {$PROCESS == "UMC28"} {
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set_clock_gating_check -setup [expr $CPUCLK_PER*0.2] [get_cells -hierarchical * -filter "ref_name =~ *PREICG*"]
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} else {
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set_clock_gating_check -setup [expr $CPUCLK_PER*0.2] [get_cells -hierarchical * -filter "ref_name =~ *CKLNQD*"]
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}
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#design for mul two cycle
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set_clock_latency 0.2 [get_pins -of_objects [get_cells -hierarchical * -filter "full_name=~*x_pa_iu_mul/mul_ex2_wb_res_*&&is_sequential==true&&is_hierarchical==false&&ref_name!~*CKGT*"] -filter "direction==in&&full_name=~*clocked_on*"]
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############################################################
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# clock gating varailbes define
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############################################################
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set ClockGatingSetup [expr 0.1*(1000.0/($CPUClkFrequency*$ClkMargin))]
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set ClockGatingHold 0
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set ClockGatingSyn true ; # true/false
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