285 lines
12 KiB
Systemverilog
285 lines
12 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// ifu_ifc_ctl.sv
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// Function: Fetch pipe control
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//
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// Comments:
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//********************************************************************************
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module ifu_ifc_ctl
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(
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input logic clk,
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input logic free_clk,
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input logic active_clk,
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input logic clk_override, // overrides clock gating
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input logic rst_l, // reset enable, from core pin
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input logic scan_mode, // scan
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input logic ic_hit_f2, // Icache hit
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input logic ic_crit_wd_rdy, // Crit word ready to be forwarded
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input logic ifu_ic_mb_empty, // Miss buffer empty
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input logic ifu_fb_consume1, // Aligner consumed 1 fetch buffer
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input logic ifu_fb_consume2, // Aligner consumed 2 fetch buffers
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input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
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input logic dec_tlu_dbg_halted, // Core is halted
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input logic dec_tlu_pmu_fw_halted, // Core is halted
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input logic exu_flush_final, // FLush
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input logic [31:1] exu_flush_path_final, // Flush path
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input logic ifu_bp_kill_next_f2, // kill next fetch, taken target found
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input logic [31:1] ifu_bp_btb_target_f2, // predicted target PC
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input logic ic_dma_active, // IC DMA active, stop fetching
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input logic ic_write_stall, // IC is writing, stop fetching
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input logic dma_iccm_stall_any, // force a stall in the fetch pipe for DMA ICCM access
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input logic [31:0] dec_tlu_mrac_ff , // side_effect and cacheable for each region
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output logic ifc_fetch_uncacheable_f1, // fetch to uncacheable address as determined by MRAC
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output logic [31:1] ifc_fetch_addr_f1, // fetch addr F1
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output logic [31:1] ifc_fetch_addr_f2, // fetch addr F2
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output logic ifc_fetch_req_f1, // fetch request valid F1
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output logic ifc_fetch_req_f1_raw, // for clock-gating in mem_ctl
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output logic ifc_fetch_req_f2, // fetch request valid F2
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output logic ifu_pmu_fetch_stall, // pmu event measuring fetch stall
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output logic ifc_iccm_access_f1, // fetch to ICCM region
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output logic ifc_region_acc_fault_f1, // fetch access fault
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output logic ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
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);
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logic [31:1] fetch_addr_bf, miss_addr, ifc_fetch_addr_f1_raw;
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logic [31:1] fetch_addr_next;
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logic [31:1] miss_addr_ns;
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logic [4:0] cacheable_select;
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logic [3:0] fb_write_f1, fb_write_ns;
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logic ifc_fetch_req_bf;
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logic overflow_nc;
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logic fb_full_f1_ns, fb_full_f1;
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logic fb_right, fb_right2, fb_right3, fb_left, wfm, fetch_ns, idle;
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logic fetch_req_f2_ns;
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logic missff_en;
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logic fetch_crit_word, ic_crit_wd_rdy_d1, fetch_crit_word_d1, fetch_crit_word_d2;
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logic reset_delayed, reset_detect, reset_detected;
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logic sel_last_addr_bf, sel_miss_addr_bf, sel_btb_addr_bf, sel_next_addr_bf;
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logic miss_f2, miss_a;
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logic flush_fb, dma_iccm_stall_any_f;
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logic dec_tlu_halted_f;
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logic mb_empty_mod, goto_idle, leave_idle;
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logic ic_crit_wd_rdy_mod;
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logic miss_sel_flush;
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logic miss_sel_f2;
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logic miss_sel_f1;
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logic miss_sel_bf;
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logic fetch_bf_en;
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logic ifc_fetch_req_f2_raw;
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logic ifc_f2_clk;
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rvoclkhdr ifu_fa2_cgc ( .en(ifc_fetch_req_f1 | clk_override), .l1clk(ifc_f2_clk), .* );
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// FSM assignment
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typedef enum logic [1:0] { IDLE=2'b00, FETCH=2'b01, STALL=2'b10, WFM=2'b11} state_t;
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state_t state, next_state;
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logic dma_stall;
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assign dma_stall = ic_dma_active | dma_iccm_stall_any_f;
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// detect a reset and start fetching the reset vector
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rvdff #(2) reset_ff (.*, .clk(free_clk), .din({1'b1, reset_detect}), .dout({reset_detect, reset_detected}));
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assign reset_delayed = reset_detect ^ reset_detected;
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rvdff #(3) ran_ff (.*, .clk(free_clk), .din({dma_iccm_stall_any, dec_tlu_dbg_halted | dec_tlu_pmu_fw_halted, miss_f2}), .dout({dma_iccm_stall_any_f, dec_tlu_halted_f, miss_a}));
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// If crit word fetch is blocked, try again
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assign ic_crit_wd_rdy_mod = ic_crit_wd_rdy & ~(fetch_crit_word_d2 & ~ifc_fetch_req_f2);
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// For Ifills, we fetch the critical word. Needed for perf and for rom bypass
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assign fetch_crit_word = ic_crit_wd_rdy_mod & ~ic_crit_wd_rdy_d1 & ~exu_flush_final & ~ic_write_stall;
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assign missff_en = exu_flush_final | (~ic_hit_f2 & ifc_fetch_req_f2) | ifu_bp_kill_next_f2 | fetch_crit_word_d1 | ifu_bp_kill_next_f2 | (ifc_fetch_req_f2 & ~ifc_fetch_req_f1 & ~fetch_crit_word_d2);
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assign miss_sel_flush = exu_flush_final & (((wfm | idle) & ~fetch_crit_word_d1) | dma_stall | ic_write_stall);
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assign miss_sel_f2 = ~exu_flush_final & ~ic_hit_f2 & ifc_fetch_req_f2;
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assign miss_sel_f1 = ~exu_flush_final & ~miss_sel_f2 & ~ifc_fetch_req_f1 & ifc_fetch_req_f2 & ~fetch_crit_word_d2 & ~ifu_bp_kill_next_f2;
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assign miss_sel_bf = ~miss_sel_f2 & ~miss_sel_f1 & ~miss_sel_flush;
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assign miss_addr_ns[31:1] = ( ({31{miss_sel_flush}} & exu_flush_path_final[31:1]) |
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({31{miss_sel_f2}} & ifc_fetch_addr_f2[31:1]) |
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({31{miss_sel_f1}} & ifc_fetch_addr_f1[31:1]) |
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({31{miss_sel_bf}} & fetch_addr_bf[31:1]));
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rvdffe #(31) faddmiss_ff (.*, .en(missff_en), .din(miss_addr_ns[31:1]), .dout(miss_addr[31:1]));
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// Fetch address mux
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// - flush
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// - Miss *or* flush during WFM (icache miss buffer is blocking)
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// - Sequential
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assign sel_last_addr_bf = ~miss_sel_flush & ~ifc_fetch_req_f1 & ifc_fetch_req_f2 & ~ifu_bp_kill_next_f2;
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assign sel_miss_addr_bf = ~miss_sel_flush & ~ifu_bp_kill_next_f2 & ~ifc_fetch_req_f1 & ~ifc_fetch_req_f2;
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assign sel_btb_addr_bf = ~miss_sel_flush & ifu_bp_kill_next_f2;
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assign sel_next_addr_bf = ~miss_sel_flush & ifc_fetch_req_f1;
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assign fetch_addr_bf[31:1] = ( ({31{miss_sel_flush}} & exu_flush_path_final[31:1]) | // FLUSH path
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({31{sel_miss_addr_bf}} & miss_addr[31:1]) | // MISS path
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({31{sel_btb_addr_bf}} & {ifu_bp_btb_target_f2[31:1]})| // BTB target
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({31{sel_last_addr_bf}} & {ifc_fetch_addr_f1[31:1]})| // Last cycle
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({31{sel_next_addr_bf}} & {fetch_addr_next[31:1]})); // SEQ path
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assign {overflow_nc, fetch_addr_next[31:1]} = {({1'b0, ifc_fetch_addr_f1[31:4]} + 29'b1), 3'b0};
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assign ifc_fetch_req_bf = (fetch_ns | fetch_crit_word) ;
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assign fetch_bf_en = (fetch_ns | fetch_crit_word);
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assign miss_f2 = ifc_fetch_req_f2 & ~ic_hit_f2;
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assign mb_empty_mod = (ifu_ic_mb_empty | exu_flush_final) & ~dma_stall & ~miss_f2 & ~miss_a;
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// Halt flushes and takes us to IDLE
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assign goto_idle = exu_flush_final & dec_tlu_flush_noredir_wb;
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// If we're in IDLE, and we get a flush, goto FETCH
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assign leave_idle = exu_flush_final & ~dec_tlu_flush_noredir_wb & idle;
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//.i 7
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//.o 2
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//.ilb state[1] state[0] reset_delayed miss_f2 mb_empty_mod goto_idle leave_idle
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//.ob next_state[1] next_state[0]
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//.type fr
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//
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//# fetch 01, stall 10, wfm 11, idle 00
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//-- 1---- 01
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//-- 0--1- 00
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//00 0--00 00
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//00 0--01 01
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//
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//01 01-0- 11
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//01 00-0- 01
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//
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//11 0-10- 01
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//11 0-00- 11
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assign next_state[1] = (~state[1] & state[0] & ~reset_delayed & miss_f2 & ~goto_idle) |
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(state[1] & ~reset_delayed & ~mb_empty_mod & ~goto_idle);
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assign next_state[0] = (~goto_idle & leave_idle) | (state[0] & ~goto_idle) |
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(reset_delayed);
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assign flush_fb = exu_flush_final;
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// model fb write logic to mass balance the fetch buffers
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assign fb_right = (~ifu_fb_consume1 & ~ifu_fb_consume2 & miss_f2) | // F2 cache miss, repair mass balance
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( ifu_fb_consume1 & ~ifu_fb_consume2 & ~ifc_fetch_req_f1 & ~miss_f2) | // Consumed and no new fetch
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(ifu_fb_consume2 & ifc_fetch_req_f1 & ~miss_f2); // Consumed 2 and new fetch
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assign fb_right2 = (ifu_fb_consume1 & ~ifu_fb_consume2 & miss_f2) | // consume 1 and miss 1
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(ifu_fb_consume2 & ~ifc_fetch_req_f1); // Consumed 2 and no new fetch
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assign fb_right3 = (ifu_fb_consume2 & miss_f2); // consume 2 and miss
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assign fb_left = ifc_fetch_req_f1 & ~(ifu_fb_consume1 | ifu_fb_consume2) & ~miss_f2;
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assign fb_write_ns[3:0] = ( ({4{(flush_fb & ~ifc_fetch_req_f1)}} & 4'b0001) |
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({4{(flush_fb & ifc_fetch_req_f1)}} & 4'b0010) |
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({4{~flush_fb & fb_right }} & {1'b0, fb_write_f1[3:1]}) |
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({4{~flush_fb & fb_right2}} & {2'b0, fb_write_f1[3:2]}) |
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({4{~flush_fb & fb_right3}} & {3'b0, fb_write_f1[3]} ) |
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({4{~flush_fb & fb_left }} & {fb_write_f1[2:0], 1'b0}) |
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({4{~flush_fb & ~fb_right & ~fb_right2 & ~fb_left & ~fb_right3}} & fb_write_f1[3:0]));
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assign fb_full_f1_ns = fb_write_ns[3];
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assign idle = state[1:0] == IDLE;
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assign wfm = state[1:0] == WFM;
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assign fetch_ns = next_state[1:0] == FETCH;
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rvdff #(2) fsm_ff (.*, .clk(active_clk), .din({next_state[1:0]}), .dout({state[1:0]}));
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rvdff #(5) fbwrite_ff (.*, .clk(active_clk), .din({fb_full_f1_ns, fb_write_ns[3:0]}), .dout({fb_full_f1, fb_write_f1[3:0]}));
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assign ifu_pmu_fetch_stall = wfm |
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(ifc_fetch_req_f1_raw &
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( (fb_full_f1 & ~(ifu_fb_consume2 | ifu_fb_consume1 | exu_flush_final)) |
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dma_stall));
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// BTB hit kills this fetch
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assign ifc_fetch_req_f1 = ( ifc_fetch_req_f1_raw &
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~ifu_bp_kill_next_f2 &
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~(fb_full_f1 & ~(ifu_fb_consume2 | ifu_fb_consume1 | exu_flush_final)) &
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~dma_stall &
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~ic_write_stall &
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~dec_tlu_flush_noredir_wb );
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// kill F2 request if we flush or if the prior fetch missed the cache/mem
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assign fetch_req_f2_ns = ifc_fetch_req_f1 & ~miss_f2;
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rvdff #(2) req_ff (.*, .clk(active_clk), .din({ifc_fetch_req_bf, fetch_req_f2_ns}), .dout({ifc_fetch_req_f1_raw, ifc_fetch_req_f2_raw}));
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assign ifc_fetch_req_f2 = ifc_fetch_req_f2_raw & ~exu_flush_final;
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rvdffe #(31) faddrf1_ff (.*, .en(fetch_bf_en), .din(fetch_addr_bf[31:1]), .dout(ifc_fetch_addr_f1_raw[31:1]));
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rvdff #(31) faddrf2_ff (.*, .clk(ifc_f2_clk), .din(ifc_fetch_addr_f1[31:1]), .dout(ifc_fetch_addr_f2[31:1]));
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assign ifc_fetch_addr_f1[31:1] = ( ({31{exu_flush_final}} & exu_flush_path_final[31:1]) |
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({31{~exu_flush_final}} & ifc_fetch_addr_f1_raw[31:1]));
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rvdff #(3) iccrit_ff (.*, .clk(active_clk), .din({ic_crit_wd_rdy_mod, fetch_crit_word, fetch_crit_word_d1}),
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.dout({ic_crit_wd_rdy_d1, fetch_crit_word_d1, fetch_crit_word_d2}));
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`ifdef RV_ICCM_ENABLE
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logic iccm_acc_in_region_f1;
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logic iccm_acc_in_range_f1;
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rvrangecheck #( .CCM_SADR (`RV_ICCM_SADR),
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.CCM_SIZE (`RV_ICCM_SIZE) ) iccm_rangecheck (
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.addr ({ifc_fetch_addr_f1[31:1],1'b0}) ,
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.in_range (iccm_acc_in_range_f1) ,
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.in_region(iccm_acc_in_region_f1)
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);
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assign ifc_iccm_access_f1 = iccm_acc_in_range_f1 ;
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assign ifc_dma_access_ok = ( (~ifc_iccm_access_f1 |
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(fb_full_f1 & ~(ifu_fb_consume2 | ifu_fb_consume1)) |
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wfm |
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idle ) & ~exu_flush_final) |
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dma_iccm_stall_any_f;
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assign ifc_region_acc_fault_f1 = ~iccm_acc_in_range_f1 & iccm_acc_in_region_f1 ;
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`else
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assign ifc_iccm_access_f1 = 1'b0 ;
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assign ifc_dma_access_ok = 1'b0 ;
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assign ifc_region_acc_fault_f1 = 1'b0 ;
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`endif
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assign cacheable_select[4:0] = {ifc_fetch_addr_f1[31:28] , 1'b0 } ;
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assign ifc_fetch_uncacheable_f1 = ~dec_tlu_mrac_ff[cacheable_select] ; // bit 0 of each region description is the cacheable bit
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endmodule // ifu_ifc_ctl
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