cores-swerv-el2/demo/Makefile

export RV_ROOT = ${PWD}/..
GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb

ABI = -mabi=ilp32 -march=rv32imc

DEMODIR = ${PWD}
BUILD_DIR = ${DEMODIR}/build
RV_SOC = ${RV_ROOT}/soc

TEST = jtag

ifdef debug
 DEBUG_PLUS = +dumpon
 VERILATOR_DEBUG = --trace
endif

LINK = $(DEMODIR)/link.ld
LINKPRO = $(DEMODIR)/link_pro.ld

# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
CFLAGS += "-std=c++11"
# Optimization for better performance; alternative is nothing for slower runtime (faster compiles)
# -O2 for faster runtime (slower compiles), or -O for balance.
VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"

# Targets
all: clean verilator

clean:
	rm -rf build obj_dir

swerv_define :
	BUILD_PATH=${BUILD_DIR} PERLLIB=${RV_SOC} ${RV_SOC}/swerv.config -target=default -set build_axi4

##################### Verilog Builds #####################################

verilator-build: swerv_define
	echo '`undef RV_ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
	verilator --cc -CFLAGS ${CFLAGS} \
	              $(BUILD_DIR)/common_defines.vh \
								$(BUILD_DIR)/el2_pdef.vh \
	              -I${BUILD_DIR} \
								-Wno-WIDTH \
	              -Wno-UNOPTFLAT \
	              -F ${RV_SOC}/soc_top.mk \
	              -F ${RV_SOC}/soc_sim.mk \
	              $(RV_SOC)/soc_sim.sv \
	              --top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
	cp ${DEMODIR}/test_soc_sim.cpp obj_dir
	$(MAKE) -j -e -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)

verilator-build-xml: swerv_define
	echo '`undef RV_ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
	verilator --xml-only -CFLAGS ${CFLAGS} \
	              $(BUILD_DIR)/common_defines.vh \
								$(BUILD_DIR)/el2_pdef.vh \
	              -I${BUILD_DIR} \
								-Wno-WIDTH \
	              -Wno-UNOPTFLAT \
	              -F ${RV_SOC}/soc_top.mk \
	              -F ${RV_SOC}/soc_sim.mk \
	              $(RV_SOC)/soc_sim.sv \
	              --top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG) \
								-o graph.dot
	cp ${DEMODIR}/test_soc_sim.cpp obj_dir
	cp ${DEMODIR}/gendot.py obj_dir
	python3 gendot.py
	dot -Tpdf -o ./obj_dir/graph.pdf ./obj_dir/graph.dot

##################### Simulation Runs #####################################

verilator: program.hex verilator-build
	cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}

sim:
	cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}

##################### Test hex Build #####################################

program.hex: $(TEST).o $(LINK)
	@echo Building $(TEST)
	$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINKPRO) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
	$(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/program.hex
	$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINK) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
	$(GCC_PREFIX)-objdump -S  $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
	@echo Completed building $(TEST)

%.o : %.s swerv_define
	$(GCC_PREFIX)-cpp -g -I${BUILD_DIR}  $<  > $(BUILD_DIR)/$*.cpp.s
	$(GCC_PREFIX)-as -g $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@

##################### openocd #####################################

openocd:
	openocd -f swerv.cfg

gdb:
	$(GDB_PREFIX) -x gdbinit ./build/jtag.bin

help:
	@echo Possible targets: verilator help clean all verilator-build program.hex

.PHONY: help clean verilator