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cores-swerv-el2/tools/vivado.tcl

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Add FuseSoC support for SweRV EL2 This adds an initial FuseSoC core description file for SweRV EL2. In addition to the core file there is also a python wrapper for the core configuration (configs/swerv_config_gen.py) that is used as a FuseSoC generator. There is also a tcl file (tools/vivado.tcl) with Vivado-specific options that FuseSoC will pick up automatically when Vivado is used. It has been successfully tested in a modified SweRVolf SoC to boot Zephyr OS in a Verilator simulation and on the Nexys A7 FPGA board. TODO: - Add target for running the bundled SweRV EL2 testbench - Add Model/Questasim support
2020-01-31 17:31:19 +08:00
set_property is_global_include true [get_files config/common_defines.vh]
set_property is_global_include true [get_files config/el2_pdef.vh]
set_property file_type SystemVerilog [get_files config/el2_pdef.vh]