76 lines
2.3 KiB
Systemverilog
76 lines
2.3 KiB
Systemverilog
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or it's affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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module el2_exu_mul_ctl
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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)
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(
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input logic clk, // Top level clock
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input logic rst_l, // Reset
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input logic scan_mode, // Scan mode
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input el2_mul_pkt_t mul_p, // {Valid, RS1 signed operand, RS2 signed operand, Select low 32-bits of result}
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input logic [31:0] rs1_in, // A operand
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input logic [31:0] rs2_in, // B operand
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output logic [31:0] result_x // Result
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);
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logic mul_x_enable;
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logic signed [32:0] rs1_ext_in;
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logic signed [32:0] rs2_ext_in;
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logic [65:0] prod_x;
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logic low_x;
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assign mul_x_enable = mul_p.valid;
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assign rs1_ext_in[32] = mul_p.rs1_sign & rs1_in[31];
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assign rs2_ext_in[32] = mul_p.rs2_sign & rs2_in[31];
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assign rs1_ext_in[31:0] = rs1_in[31:0];
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assign rs2_ext_in[31:0] = rs2_in[31:0];
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// --------------------------- Multiply ----------------------------------
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logic signed [32:0] rs1_x;
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logic signed [32:0] rs2_x;
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rvdffe #(34) i_a_x_ff (.*, .din({mul_p.low,rs1_ext_in[32:0]}), .dout({low_x,rs1_x[32:0]}), .en(mul_x_enable));
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rvdffe #(33) i_b_x_ff (.*, .din( rs2_ext_in[32:0] ), .dout( rs2_x[32:0] ), .en(mul_x_enable));
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assign prod_x[65:0] = rs1_x * rs2_x;
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assign result_x[31:0] = ( {32{~low_x}} & prod_x[63:32] ) |
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( {32{ low_x}} & prod_x[31:0] );
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endmodule // el2_exu_mul_ctl
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