883 lines
31 KiB
Systemverilog
883 lines
31 KiB
Systemverilog
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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`ifndef VERILATOR
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module tb_top;
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`else
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module tb_top ( input bit core_clk );
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`endif
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`ifndef VERILATOR
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bit core_clk;
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`endif
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logic rst_l;
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logic nmi_int;
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logic [31:0] reset_vector;
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logic [31:0] nmi_vector;
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logic [31:1] jtag_id;
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logic [31:0] ic_haddr ;
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logic [2:0] ic_hburst ;
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logic ic_hmastlock ;
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logic [3:0] ic_hprot ;
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logic [2:0] ic_hsize ;
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logic [1:0] ic_htrans ;
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logic ic_hwrite ;
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logic [63:0] ic_hrdata ;
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logic ic_hready ;
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logic ic_hresp ;
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logic [31:0] lsu_haddr ;
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logic [2:0] lsu_hburst ;
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logic lsu_hmastlock ;
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logic [3:0] lsu_hprot ;
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logic [2:0] lsu_hsize ;
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logic [1:0] lsu_htrans ;
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logic lsu_hwrite ;
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logic [63:0] lsu_hrdata ;
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logic [63:0] lsu_hwdata ;
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logic lsu_hready ;
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logic lsu_hresp ;
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logic [31:0] sb_haddr ;
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logic [2:0] sb_hburst ;
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logic sb_hmastlock ;
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logic [3:0] sb_hprot ;
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logic [2:0] sb_hsize ;
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logic [1:0] sb_htrans ;
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logic sb_hwrite ;
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logic [63:0] sb_hrdata ;
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logic [63:0] sb_hwdata ;
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logic sb_hready ;
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logic sb_hresp ;
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logic [31:0] trace_rv_i_insn_ip;
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logic [31:0] trace_rv_i_address_ip;
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logic [1:0] trace_rv_i_valid_ip;
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logic [1:0] trace_rv_i_exception_ip;
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logic [4:0] trace_rv_i_ecause_ip;
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logic [2:0] trace_rv_i_interrupt_ip;
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logic [31:0] trace_rv_i_tval_ip;
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logic o_debug_mode_status;
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logic jtag_tdo;
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logic o_cpu_halt_ack;
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logic o_cpu_halt_status;
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logic o_cpu_run_ack;
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logic mailbox_write;
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logic [63:0] dma_hrdata ;
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logic [63:0] dma_hwdata ;
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logic dma_hready ;
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logic dma_hresp ;
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logic mpc_debug_halt_req;
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logic mpc_debug_run_req;
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logic mpc_reset_run_req;
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logic mpc_debug_halt_ack;
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logic mpc_debug_run_ack;
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logic debug_brkpt_status;
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bit [31:0] cycleCnt ;
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logic mailbox_data_val;
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wire dma_hready_out;
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int commit_count;
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logic wb_valid[1:0];
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logic [4:0] wb_dest[1:0];
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logic [31:0] wb_data[1:0];
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`ifdef RV_BUILD_AXI4
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//-------------------------- LSU AXI signals--------------------------
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// AXI Write Channels
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wire lsu_axi_awvalid;
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wire lsu_axi_awready;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_awid;
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wire [31:0] lsu_axi_awaddr;
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wire [3:0] lsu_axi_awregion;
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wire [7:0] lsu_axi_awlen;
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wire [2:0] lsu_axi_awsize;
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wire [1:0] lsu_axi_awburst;
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wire lsu_axi_awlock;
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wire [3:0] lsu_axi_awcache;
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wire [2:0] lsu_axi_awprot;
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wire [3:0] lsu_axi_awqos;
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wire lsu_axi_wvalid;
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wire lsu_axi_wready;
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wire [63:0] lsu_axi_wdata;
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wire [7:0] lsu_axi_wstrb;
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wire lsu_axi_wlast;
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wire lsu_axi_bvalid;
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wire lsu_axi_bready;
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wire [1:0] lsu_axi_bresp;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_bid;
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// AXI Read Channels
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wire lsu_axi_arvalid;
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wire lsu_axi_arready;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_arid;
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wire [31:0] lsu_axi_araddr;
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wire [3:0] lsu_axi_arregion;
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wire [7:0] lsu_axi_arlen;
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wire [2:0] lsu_axi_arsize;
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wire [1:0] lsu_axi_arburst;
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wire lsu_axi_arlock;
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wire [3:0] lsu_axi_arcache;
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wire [2:0] lsu_axi_arprot;
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wire [3:0] lsu_axi_arqos;
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wire lsu_axi_rvalid;
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wire lsu_axi_rready;
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wire [`RV_LSU_BUS_TAG-1:0] lsu_axi_rid;
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wire [63:0] lsu_axi_rdata;
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wire [1:0] lsu_axi_rresp;
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wire lsu_axi_rlast;
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//-------------------------- IFU AXI signals--------------------------
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// AXI Write Channels
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wire ifu_axi_awvalid;
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wire ifu_axi_awready;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_awid;
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wire [31:0] ifu_axi_awaddr;
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wire [3:0] ifu_axi_awregion;
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wire [7:0] ifu_axi_awlen;
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wire [2:0] ifu_axi_awsize;
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wire [1:0] ifu_axi_awburst;
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wire ifu_axi_awlock;
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wire [3:0] ifu_axi_awcache;
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wire [2:0] ifu_axi_awprot;
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wire [3:0] ifu_axi_awqos;
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wire ifu_axi_wvalid;
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wire ifu_axi_wready;
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wire [63:0] ifu_axi_wdata;
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wire [7:0] ifu_axi_wstrb;
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wire ifu_axi_wlast;
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wire ifu_axi_bvalid;
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wire ifu_axi_bready;
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wire [1:0] ifu_axi_bresp;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_bid;
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// AXI Read Channels
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wire ifu_axi_arvalid;
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wire ifu_axi_arready;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_arid;
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wire [31:0] ifu_axi_araddr;
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wire [3:0] ifu_axi_arregion;
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wire [7:0] ifu_axi_arlen;
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wire [2:0] ifu_axi_arsize;
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wire [1:0] ifu_axi_arburst;
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wire ifu_axi_arlock;
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wire [3:0] ifu_axi_arcache;
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wire [2:0] ifu_axi_arprot;
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wire [3:0] ifu_axi_arqos;
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wire ifu_axi_rvalid;
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wire ifu_axi_rready;
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wire [`RV_IFU_BUS_TAG-1:0] ifu_axi_rid;
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wire [63:0] ifu_axi_rdata;
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wire [1:0] ifu_axi_rresp;
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wire ifu_axi_rlast;
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//-------------------------- SB AXI signals--------------------------
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// AXI Write Channels
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wire sb_axi_awvalid;
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wire sb_axi_awready;
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wire [`RV_SB_BUS_TAG-1:0] sb_axi_awid;
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wire [31:0] sb_axi_awaddr;
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wire [3:0] sb_axi_awregion;
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wire [7:0] sb_axi_awlen;
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wire [2:0] sb_axi_awsize;
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wire [1:0] sb_axi_awburst;
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wire sb_axi_awlock;
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wire [3:0] sb_axi_awcache;
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wire [2:0] sb_axi_awprot;
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wire [3:0] sb_axi_awqos;
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wire sb_axi_wvalid;
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wire sb_axi_wready;
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wire [63:0] sb_axi_wdata;
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wire [7:0] sb_axi_wstrb;
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wire sb_axi_wlast;
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wire sb_axi_bvalid;
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wire sb_axi_bready;
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wire [1:0] sb_axi_bresp;
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wire [`RV_SB_BUS_TAG-1:0] sb_axi_bid;
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// AXI Read Channels
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wire sb_axi_arvalid;
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wire sb_axi_arready;
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wire [`RV_SB_BUS_TAG-1:0] sb_axi_arid;
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wire [31:0] sb_axi_araddr;
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wire [3:0] sb_axi_arregion;
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wire [7:0] sb_axi_arlen;
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wire [2:0] sb_axi_arsize;
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wire [1:0] sb_axi_arburst;
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wire sb_axi_arlock;
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wire [3:0] sb_axi_arcache;
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wire [2:0] sb_axi_arprot;
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wire [3:0] sb_axi_arqos;
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wire sb_axi_rvalid;
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wire sb_axi_rready;
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wire [`RV_SB_BUS_TAG-1:0] sb_axi_rid;
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wire [63:0] sb_axi_rdata;
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wire [1:0] sb_axi_rresp;
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wire sb_axi_rlast;
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//-------------------------- DMA AXI signals--------------------------
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// AXI Write Channels
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wire dma_axi_awvalid;
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wire dma_axi_awready;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_awid;
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wire [31:0] dma_axi_awaddr;
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wire [2:0] dma_axi_awsize;
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wire [2:0] dma_axi_awprot;
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wire [7:0] dma_axi_awlen;
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wire [1:0] dma_axi_awburst;
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wire dma_axi_wvalid;
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wire dma_axi_wready;
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wire [63:0] dma_axi_wdata;
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wire [7:0] dma_axi_wstrb;
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wire dma_axi_wlast;
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wire dma_axi_bvalid;
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wire dma_axi_bready;
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wire [1:0] dma_axi_bresp;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_bid;
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// AXI Read Channels
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wire dma_axi_arvalid;
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wire dma_axi_arready;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_arid;
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wire [31:0] dma_axi_araddr;
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wire [2:0] dma_axi_arsize;
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wire [2:0] dma_axi_arprot;
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wire [7:0] dma_axi_arlen;
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wire [1:0] dma_axi_arburst;
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wire dma_axi_rvalid;
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wire dma_axi_rready;
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wire [`RV_DMA_BUS_TAG-1:0] dma_axi_rid;
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wire [63:0] dma_axi_rdata;
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wire [1:0] dma_axi_rresp;
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wire dma_axi_rlast;
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`endif
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wire[63:0] WriteData;
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assign mailbox_write = lmem.mailbox_write;
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assign WriteData = lmem.WriteData;
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assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
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parameter MAX_CYCLES = 2_000_000;
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integer fd, tp, el;
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always @(negedge core_clk) begin
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cycleCnt <= cycleCnt+1;
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// Test timeout monitor
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if(cycleCnt == MAX_CYCLES) begin
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$display ("Hit max cycle count (%0d) .. stopping",cycleCnt);
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$finish;
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end
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// console Monitor
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if( mailbox_data_val & mailbox_write) begin
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$fwrite(fd,"%c", WriteData[7:0]);
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$write("%c", WriteData[7:0]);
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end
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// End Of test monitor
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if(mailbox_write && WriteData[7:0] == 8'hff) begin
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$display("TEST_PASSED");
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$display("\nFinished : minstret = %0d, mcycle = %0d", rvtop.swerv.dec.tlu.minstretl[31:0],rvtop.swerv.dec.tlu.mcyclel[31:0]);
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$display("See \"exec.log\" for execution trace with register updates..\n");
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$finish;
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end
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else if(mailbox_write && WriteData[7:0] == 8'h1) begin
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$display("TEST_FAILED");
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$finish;
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end
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end
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// trace monitor
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always @(posedge core_clk) begin
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wb_valid[0] <= rvtop.swerv.dec.dec_i0_wen_r;
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wb_dest[0] <= rvtop.swerv.dec.dec_i0_waddr_r;
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wb_data[0] <= rvtop.swerv.dec.dec_i0_wdata_r;
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if (rvtop.trace_rv_i_valid_ip !== 0) begin
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$fwrite(tp,"%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", rvtop.trace_rv_i_valid_ip, 0, trace_rv_i_address_ip,
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0, trace_rv_i_insn_ip,trace_rv_i_exception_ip,trace_rv_i_ecause_ip,
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trace_rv_i_tval_ip,trace_rv_i_interrupt_ip);
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||
|
|
// Basic trace - no exception register updates
|
||
|
|
// #1 0 ee000000 b0201073 c 0b02 00000000
|
||
|
|
for (int i=0; i<1; i++)
|
||
|
|
if (rvtop.trace_rv_i_valid_ip[i]==1) begin
|
||
|
|
commit_count++;
|
||
|
|
$fwrite (el, "%10d : %6s 0 %h %h %s\n", cycleCnt, $sformatf("#%0d",commit_count),
|
||
|
|
trace_rv_i_address_ip[31+i*32 -:32], trace_rv_i_insn_ip[31+i*32-:32],
|
||
|
|
wb_dest[i] !=0 ? $sformatf("r%0d=%h", wb_dest[i], wb_data[i]) : "");
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
|
||
|
|
initial begin
|
||
|
|
// tie offs
|
||
|
|
jtag_id[31:28] = 4'b1;
|
||
|
|
jtag_id[27:12] = '0;
|
||
|
|
jtag_id[11:1] = 11'h45;
|
||
|
|
reset_vector = 32'h0;
|
||
|
|
nmi_vector = 32'hee000000;
|
||
|
|
nmi_int = 0;
|
||
|
|
|
||
|
|
$readmemh("data.hex", lmem.mem);
|
||
|
|
$readmemh("program.hex", imem.mem);
|
||
|
|
tp = $fopen("trace_port.csv","w");
|
||
|
|
el = $fopen("exec.log","w");
|
||
|
|
$fwrite (el, "//Cycle : #inst 0 pc opcode reg regnum value\n");
|
||
|
|
fd = $fopen("console.log","w");
|
||
|
|
commit_count = 0;
|
||
|
|
preload_dccm();
|
||
|
|
|
||
|
|
`ifndef VERILATOR
|
||
|
|
if($test$plusargs("dumpon")) $dumpvars;
|
||
|
|
forever core_clk = #5 ~core_clk;
|
||
|
|
`endif
|
||
|
|
end
|
||
|
|
|
||
|
|
|
||
|
|
assign rst_l = cycleCnt > 5;
|
||
|
|
|
||
|
|
//=========================================================================-
|
||
|
|
// RTL instance
|
||
|
|
//=========================================================================-
|
||
|
|
el2_swerv_wrapper rvtop (
|
||
|
|
.rst_l ( rst_l ),
|
||
|
|
.clk ( core_clk ),
|
||
|
|
.rst_vec ( reset_vector[31:1]),
|
||
|
|
.nmi_int ( nmi_int ),
|
||
|
|
.nmi_vec ( nmi_vector[31:1]),
|
||
|
|
.jtag_id ( jtag_id[31:1]),
|
||
|
|
|
||
|
|
`ifdef RV_BUILD_AHB_LITE
|
||
|
|
.haddr ( ic_haddr ),
|
||
|
|
.hburst ( ic_hburst ),
|
||
|
|
.hmastlock ( ic_hmastlock ),
|
||
|
|
.hprot ( ic_hprot ),
|
||
|
|
.hsize ( ic_hsize ),
|
||
|
|
.htrans ( ic_htrans ),
|
||
|
|
.hwrite ( ic_hwrite ),
|
||
|
|
|
||
|
|
.hrdata ( ic_hrdata[63:0]),
|
||
|
|
.hready ( ic_hready ),
|
||
|
|
.hresp ( ic_hresp ),
|
||
|
|
|
||
|
|
//---------------------------------------------------------------
|
||
|
|
// Debug AHB Master
|
||
|
|
//---------------------------------------------------------------
|
||
|
|
.sb_haddr ( sb_haddr ),
|
||
|
|
.sb_hburst ( sb_hburst ),
|
||
|
|
.sb_hmastlock ( sb_hmastlock ),
|
||
|
|
.sb_hprot ( sb_hprot ),
|
||
|
|
.sb_hsize ( sb_hsize ),
|
||
|
|
.sb_htrans ( sb_htrans ),
|
||
|
|
.sb_hwrite ( sb_hwrite ),
|
||
|
|
.sb_hwdata ( sb_hwdata ),
|
||
|
|
|
||
|
|
.sb_hrdata ( sb_hrdata ),
|
||
|
|
.sb_hready ( sb_hready ),
|
||
|
|
.sb_hresp ( sb_hresp ),
|
||
|
|
|
||
|
|
//---------------------------------------------------------------
|
||
|
|
// LSU AHB Master
|
||
|
|
//---------------------------------------------------------------
|
||
|
|
.lsu_haddr ( lsu_haddr ),
|
||
|
|
.lsu_hburst ( lsu_hburst ),
|
||
|
|
.lsu_hmastlock ( lsu_hmastlock ),
|
||
|
|
.lsu_hprot ( lsu_hprot ),
|
||
|
|
.lsu_hsize ( lsu_hsize ),
|
||
|
|
.lsu_htrans ( lsu_htrans ),
|
||
|
|
.lsu_hwrite ( lsu_hwrite ),
|
||
|
|
.lsu_hwdata ( lsu_hwdata ),
|
||
|
|
|
||
|
|
.lsu_hrdata ( lsu_hrdata[63:0]),
|
||
|
|
.lsu_hready ( lsu_hready ),
|
||
|
|
.lsu_hresp ( lsu_hresp ),
|
||
|
|
|
||
|
|
//---------------------------------------------------------------
|
||
|
|
// DMA Slave
|
||
|
|
//---------------------------------------------------------------
|
||
|
|
.dma_haddr ( '0 ),
|
||
|
|
.dma_hburst ( '0 ),
|
||
|
|
.dma_hmastlock ( '0 ),
|
||
|
|
.dma_hprot ( '0 ),
|
||
|
|
.dma_hsize ( '0 ),
|
||
|
|
.dma_htrans ( '0 ),
|
||
|
|
.dma_hwrite ( '0 ),
|
||
|
|
.dma_hwdata ( '0 ),
|
||
|
|
|
||
|
|
.dma_hrdata ( dma_hrdata ),
|
||
|
|
.dma_hresp ( dma_hresp ),
|
||
|
|
.dma_hsel ( 1'b1 ),
|
||
|
|
.dma_hreadyin ( dma_hready_out ),
|
||
|
|
.dma_hreadyout ( dma_hready_out ),
|
||
|
|
`endif
|
||
|
|
`ifdef RV_BUILD_AXI4
|
||
|
|
//-------------------------- LSU AXI signals--------------------------
|
||
|
|
// AXI Write Channels
|
||
|
|
.lsu_axi_awvalid (lsu_axi_awvalid),
|
||
|
|
.lsu_axi_awready (lsu_axi_awready),
|
||
|
|
.lsu_axi_awid (lsu_axi_awid),
|
||
|
|
.lsu_axi_awaddr (lsu_axi_awaddr),
|
||
|
|
.lsu_axi_awregion (lsu_axi_awregion),
|
||
|
|
.lsu_axi_awlen (lsu_axi_awlen),
|
||
|
|
.lsu_axi_awsize (lsu_axi_awsize),
|
||
|
|
.lsu_axi_awburst (lsu_axi_awburst),
|
||
|
|
.lsu_axi_awlock (lsu_axi_awlock),
|
||
|
|
.lsu_axi_awcache (lsu_axi_awcache),
|
||
|
|
.lsu_axi_awprot (lsu_axi_awprot),
|
||
|
|
.lsu_axi_awqos (lsu_axi_awqos),
|
||
|
|
|
||
|
|
.lsu_axi_wvalid (lsu_axi_wvalid),
|
||
|
|
.lsu_axi_wready (lsu_axi_wready),
|
||
|
|
.lsu_axi_wdata (lsu_axi_wdata),
|
||
|
|
.lsu_axi_wstrb (lsu_axi_wstrb),
|
||
|
|
.lsu_axi_wlast (lsu_axi_wlast),
|
||
|
|
|
||
|
|
.lsu_axi_bvalid (lsu_axi_bvalid),
|
||
|
|
.lsu_axi_bready (lsu_axi_bready),
|
||
|
|
.lsu_axi_bresp (lsu_axi_bresp),
|
||
|
|
.lsu_axi_bid (lsu_axi_bid),
|
||
|
|
|
||
|
|
|
||
|
|
.lsu_axi_arvalid (lsu_axi_arvalid),
|
||
|
|
.lsu_axi_arready (lsu_axi_arready),
|
||
|
|
.lsu_axi_arid (lsu_axi_arid),
|
||
|
|
.lsu_axi_araddr (lsu_axi_araddr),
|
||
|
|
.lsu_axi_arregion (lsu_axi_arregion),
|
||
|
|
.lsu_axi_arlen (lsu_axi_arlen),
|
||
|
|
.lsu_axi_arsize (lsu_axi_arsize),
|
||
|
|
.lsu_axi_arburst (lsu_axi_arburst),
|
||
|
|
.lsu_axi_arlock (lsu_axi_arlock),
|
||
|
|
.lsu_axi_arcache (lsu_axi_arcache),
|
||
|
|
.lsu_axi_arprot (lsu_axi_arprot),
|
||
|
|
.lsu_axi_arqos (lsu_axi_arqos),
|
||
|
|
|
||
|
|
.lsu_axi_rvalid (lsu_axi_rvalid),
|
||
|
|
.lsu_axi_rready (lsu_axi_rready),
|
||
|
|
.lsu_axi_rid (lsu_axi_rid),
|
||
|
|
.lsu_axi_rdata (lsu_axi_rdata),
|
||
|
|
.lsu_axi_rresp (lsu_axi_rresp),
|
||
|
|
.lsu_axi_rlast (lsu_axi_rlast),
|
||
|
|
|
||
|
|
//-------------------------- IFU AXI signals--------------------------
|
||
|
|
// AXI Write Channels
|
||
|
|
.ifu_axi_awvalid (ifu_axi_awvalid),
|
||
|
|
.ifu_axi_awready (ifu_axi_awready),
|
||
|
|
.ifu_axi_awid (ifu_axi_awid),
|
||
|
|
.ifu_axi_awaddr (ifu_axi_awaddr),
|
||
|
|
.ifu_axi_awregion (ifu_axi_awregion),
|
||
|
|
.ifu_axi_awlen (ifu_axi_awlen),
|
||
|
|
.ifu_axi_awsize (ifu_axi_awsize),
|
||
|
|
.ifu_axi_awburst (ifu_axi_awburst),
|
||
|
|
.ifu_axi_awlock (ifu_axi_awlock),
|
||
|
|
.ifu_axi_awcache (ifu_axi_awcache),
|
||
|
|
.ifu_axi_awprot (ifu_axi_awprot),
|
||
|
|
.ifu_axi_awqos (ifu_axi_awqos),
|
||
|
|
|
||
|
|
.ifu_axi_wvalid (ifu_axi_wvalid),
|
||
|
|
.ifu_axi_wready (ifu_axi_wready),
|
||
|
|
.ifu_axi_wdata (ifu_axi_wdata),
|
||
|
|
.ifu_axi_wstrb (ifu_axi_wstrb),
|
||
|
|
.ifu_axi_wlast (ifu_axi_wlast),
|
||
|
|
|
||
|
|
.ifu_axi_bvalid (ifu_axi_bvalid),
|
||
|
|
.ifu_axi_bready (ifu_axi_bready),
|
||
|
|
.ifu_axi_bresp (ifu_axi_bresp),
|
||
|
|
.ifu_axi_bid (ifu_axi_bid),
|
||
|
|
|
||
|
|
.ifu_axi_arvalid (ifu_axi_arvalid),
|
||
|
|
.ifu_axi_arready (ifu_axi_arready),
|
||
|
|
.ifu_axi_arid (ifu_axi_arid),
|
||
|
|
.ifu_axi_araddr (ifu_axi_araddr),
|
||
|
|
.ifu_axi_arregion (ifu_axi_arregion),
|
||
|
|
.ifu_axi_arlen (ifu_axi_arlen),
|
||
|
|
.ifu_axi_arsize (ifu_axi_arsize),
|
||
|
|
.ifu_axi_arburst (ifu_axi_arburst),
|
||
|
|
.ifu_axi_arlock (ifu_axi_arlock),
|
||
|
|
.ifu_axi_arcache (ifu_axi_arcache),
|
||
|
|
.ifu_axi_arprot (ifu_axi_arprot),
|
||
|
|
.ifu_axi_arqos (ifu_axi_arqos),
|
||
|
|
|
||
|
|
.ifu_axi_rvalid (ifu_axi_rvalid),
|
||
|
|
.ifu_axi_rready (ifu_axi_rready),
|
||
|
|
.ifu_axi_rid (ifu_axi_rid),
|
||
|
|
.ifu_axi_rdata (ifu_axi_rdata),
|
||
|
|
.ifu_axi_rresp (ifu_axi_rresp),
|
||
|
|
.ifu_axi_rlast (ifu_axi_rlast),
|
||
|
|
|
||
|
|
//-------------------------- SB AXI signals--------------------------
|
||
|
|
// AXI Write Channels
|
||
|
|
.sb_axi_awvalid (sb_axi_awvalid),
|
||
|
|
.sb_axi_awready (sb_axi_awready),
|
||
|
|
.sb_axi_awid (sb_axi_awid),
|
||
|
|
.sb_axi_awaddr (sb_axi_awaddr),
|
||
|
|
.sb_axi_awregion (sb_axi_awregion),
|
||
|
|
.sb_axi_awlen (sb_axi_awlen),
|
||
|
|
.sb_axi_awsize (sb_axi_awsize),
|
||
|
|
.sb_axi_awburst (sb_axi_awburst),
|
||
|
|
.sb_axi_awlock (sb_axi_awlock),
|
||
|
|
.sb_axi_awcache (sb_axi_awcache),
|
||
|
|
.sb_axi_awprot (sb_axi_awprot),
|
||
|
|
.sb_axi_awqos (sb_axi_awqos),
|
||
|
|
|
||
|
|
.sb_axi_wvalid (sb_axi_wvalid),
|
||
|
|
.sb_axi_wready (sb_axi_wready),
|
||
|
|
.sb_axi_wdata (sb_axi_wdata),
|
||
|
|
.sb_axi_wstrb (sb_axi_wstrb),
|
||
|
|
.sb_axi_wlast (sb_axi_wlast),
|
||
|
|
|
||
|
|
.sb_axi_bvalid (sb_axi_bvalid),
|
||
|
|
.sb_axi_bready (sb_axi_bready),
|
||
|
|
.sb_axi_bresp (sb_axi_bresp),
|
||
|
|
.sb_axi_bid (sb_axi_bid),
|
||
|
|
|
||
|
|
|
||
|
|
.sb_axi_arvalid (sb_axi_arvalid),
|
||
|
|
.sb_axi_arready (sb_axi_arready),
|
||
|
|
.sb_axi_arid (sb_axi_arid),
|
||
|
|
.sb_axi_araddr (sb_axi_araddr),
|
||
|
|
.sb_axi_arregion (sb_axi_arregion),
|
||
|
|
.sb_axi_arlen (sb_axi_arlen),
|
||
|
|
.sb_axi_arsize (sb_axi_arsize),
|
||
|
|
.sb_axi_arburst (sb_axi_arburst),
|
||
|
|
.sb_axi_arlock (sb_axi_arlock),
|
||
|
|
.sb_axi_arcache (sb_axi_arcache),
|
||
|
|
.sb_axi_arprot (sb_axi_arprot),
|
||
|
|
.sb_axi_arqos (sb_axi_arqos),
|
||
|
|
|
||
|
|
.sb_axi_rvalid (sb_axi_rvalid),
|
||
|
|
.sb_axi_rready (sb_axi_rready),
|
||
|
|
.sb_axi_rid (sb_axi_rid),
|
||
|
|
.sb_axi_rdata (sb_axi_rdata),
|
||
|
|
.sb_axi_rresp (sb_axi_rresp),
|
||
|
|
.sb_axi_rlast (sb_axi_rlast),
|
||
|
|
|
||
|
|
//-------------------------- DMA AXI signals--------------------------
|
||
|
|
// AXI Write Channels
|
||
|
|
.dma_axi_awvalid (1'b0),
|
||
|
|
.dma_axi_awready (dma_axi_awready),
|
||
|
|
.dma_axi_awid (dma_axi_awid),
|
||
|
|
.dma_axi_awaddr (dma_axi_awaddr),
|
||
|
|
.dma_axi_awsize (dma_axi_awsize),
|
||
|
|
.dma_axi_awprot (dma_axi_awprot),
|
||
|
|
.dma_axi_awlen (dma_axi_awlen),
|
||
|
|
.dma_axi_awburst (dma_axi_awburst),
|
||
|
|
|
||
|
|
|
||
|
|
.dma_axi_wvalid (1'b0),
|
||
|
|
.dma_axi_wready (dma_axi_wready),
|
||
|
|
.dma_axi_wdata (dma_axi_wdata),
|
||
|
|
.dma_axi_wstrb (dma_axi_wstrb),
|
||
|
|
.dma_axi_wlast (dma_axi_wlast),
|
||
|
|
|
||
|
|
.dma_axi_bvalid (dma_axi_bvalid),
|
||
|
|
.dma_axi_bready (1'b0),
|
||
|
|
.dma_axi_bresp (dma_axi_bresp),
|
||
|
|
.dma_axi_bid (dma_axi_bid),
|
||
|
|
|
||
|
|
|
||
|
|
.dma_axi_arvalid (1'b0),
|
||
|
|
.dma_axi_arready (dma_axi_arready),
|
||
|
|
.dma_axi_arid (dma_axi_arid),
|
||
|
|
.dma_axi_araddr (dma_axi_araddr),
|
||
|
|
.dma_axi_arsize (dma_axi_arsize),
|
||
|
|
.dma_axi_arprot (dma_axi_arprot),
|
||
|
|
.dma_axi_arlen (dma_axi_arlen),
|
||
|
|
.dma_axi_arburst (dma_axi_arburst),
|
||
|
|
|
||
|
|
.dma_axi_rvalid (dma_axi_rvalid),
|
||
|
|
.dma_axi_rready (1'b0),
|
||
|
|
.dma_axi_rid (dma_axi_rid),
|
||
|
|
.dma_axi_rdata (dma_axi_rdata),
|
||
|
|
.dma_axi_rresp (dma_axi_rresp),
|
||
|
|
.dma_axi_rlast (dma_axi_rlast),
|
||
|
|
`endif
|
||
|
|
.timer_int ( 1'b0 ),
|
||
|
|
.extintsrc_req ( '0 ),
|
||
|
|
|
||
|
|
.lsu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface
|
||
|
|
.ifu_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB master interface
|
||
|
|
.dbg_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB Debug master interface
|
||
|
|
.dma_bus_clk_en ( 1'b1 ),// Clock ratio b/w cpu core clk & AHB slave interface
|
||
|
|
|
||
|
|
.trace_rv_i_insn_ip (trace_rv_i_insn_ip),
|
||
|
|
.trace_rv_i_address_ip (trace_rv_i_address_ip),
|
||
|
|
.trace_rv_i_valid_ip (trace_rv_i_valid_ip),
|
||
|
|
.trace_rv_i_exception_ip(trace_rv_i_exception_ip),
|
||
|
|
.trace_rv_i_ecause_ip (trace_rv_i_ecause_ip),
|
||
|
|
.trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip),
|
||
|
|
.trace_rv_i_tval_ip (trace_rv_i_tval_ip),
|
||
|
|
|
||
|
|
.jtag_tck ( 1'b0 ),
|
||
|
|
.jtag_tms ( 1'b0 ),
|
||
|
|
.jtag_tdi ( 1'b0 ),
|
||
|
|
.jtag_trst_n ( 1'b0 ),
|
||
|
|
.jtag_tdo ( jtag_tdo ),
|
||
|
|
|
||
|
|
.mpc_debug_halt_ack ( mpc_debug_halt_ack),
|
||
|
|
.mpc_debug_halt_req ( 1'b0),
|
||
|
|
.mpc_debug_run_ack ( mpc_debug_run_ack),
|
||
|
|
.mpc_debug_run_req ( 1'b1),
|
||
|
|
.mpc_reset_run_req ( 1'b1), // Start running after reset
|
||
|
|
.debug_brkpt_status (debug_brkpt_status),
|
||
|
|
|
||
|
|
.i_cpu_halt_req ( 1'b0 ), // Async halt req to CPU
|
||
|
|
.o_cpu_halt_ack ( o_cpu_halt_ack ), // core response to halt
|
||
|
|
.o_cpu_halt_status ( o_cpu_halt_status ), // 1'b1 indicates core is halted
|
||
|
|
.i_cpu_run_req ( 1'b0 ), // Async restart req to CPU
|
||
|
|
.o_debug_mode_status (o_debug_mode_status),
|
||
|
|
.o_cpu_run_ack ( o_cpu_run_ack ), // Core response to run req
|
||
|
|
|
||
|
|
.dec_tlu_perfcnt0 (),
|
||
|
|
.dec_tlu_perfcnt1 (),
|
||
|
|
.dec_tlu_perfcnt2 (),
|
||
|
|
.dec_tlu_perfcnt3 (),
|
||
|
|
|
||
|
|
.soft_int ('0),
|
||
|
|
.core_id ('0),
|
||
|
|
.scan_mode ( 1'b0 ), // To enable scan mode
|
||
|
|
.mbist_mode ( 1'b0 ) // to enable mbist
|
||
|
|
|
||
|
|
);
|
||
|
|
|
||
|
|
|
||
|
|
//=========================================================================-
|
||
|
|
// AHB I$ instance
|
||
|
|
//=========================================================================-
|
||
|
|
`ifdef RV_BUILD_AHB_LITE
|
||
|
|
|
||
|
|
ahb_sif imem (
|
||
|
|
// Inputs
|
||
|
|
.HWDATA(64'h0),
|
||
|
|
.HCLK(core_clk),
|
||
|
|
.HSEL(1'b1),
|
||
|
|
.HPROT(ic_hprot),
|
||
|
|
.HWRITE(ic_hwrite),
|
||
|
|
.HTRANS(ic_htrans),
|
||
|
|
.HSIZE(ic_hsize),
|
||
|
|
.HREADY(ic_hready),
|
||
|
|
.HRESETn(rst_l),
|
||
|
|
.HADDR(ic_haddr),
|
||
|
|
.HBURST(ic_hburst),
|
||
|
|
|
||
|
|
// Outputs
|
||
|
|
.HREADYOUT(ic_hready),
|
||
|
|
.HRESP(ic_hresp),
|
||
|
|
.HRDATA(ic_hrdata[63:0])
|
||
|
|
);
|
||
|
|
|
||
|
|
|
||
|
|
ahb_sif lmem (
|
||
|
|
// Inputs
|
||
|
|
.HWDATA(lsu_hwdata),
|
||
|
|
.HCLK(core_clk),
|
||
|
|
.HSEL(1'b1),
|
||
|
|
.HPROT(lsu_hprot),
|
||
|
|
.HWRITE(lsu_hwrite),
|
||
|
|
.HTRANS(lsu_htrans),
|
||
|
|
.HSIZE(lsu_hsize),
|
||
|
|
.HREADY(lsu_hready),
|
||
|
|
.HRESETn(rst_l),
|
||
|
|
.HADDR(lsu_haddr),
|
||
|
|
.HBURST(lsu_hburst),
|
||
|
|
|
||
|
|
// Outputs
|
||
|
|
.HREADYOUT(lsu_hready),
|
||
|
|
.HRESP(lsu_hresp),
|
||
|
|
.HRDATA(lsu_hrdata[63:0])
|
||
|
|
);
|
||
|
|
|
||
|
|
`endif
|
||
|
|
`ifdef RV_BUILD_AXI4
|
||
|
|
axi_slv #(.TAGW(`RV_IFU_BUS_TAG)) imem(
|
||
|
|
.aclk(core_clk),
|
||
|
|
.rst_l(rst_l),
|
||
|
|
.arvalid(ifu_axi_arvalid),
|
||
|
|
.arready(ifu_axi_arready),
|
||
|
|
.araddr(ifu_axi_araddr),
|
||
|
|
.arid(ifu_axi_arid),
|
||
|
|
.arlen(ifu_axi_arlen),
|
||
|
|
.arburst(ifu_axi_arburst),
|
||
|
|
.arsize(ifu_axi_arsize),
|
||
|
|
|
||
|
|
.rvalid(ifu_axi_rvalid),
|
||
|
|
.rready(ifu_axi_rready),
|
||
|
|
.rdata(ifu_axi_rdata),
|
||
|
|
.rresp(ifu_axi_rresp),
|
||
|
|
.rid(ifu_axi_rid),
|
||
|
|
.rlast(ifu_axi_rlast),
|
||
|
|
|
||
|
|
.awvalid(1'b0),
|
||
|
|
.awready(),
|
||
|
|
.awaddr('0),
|
||
|
|
.awid('0),
|
||
|
|
.awlen('0),
|
||
|
|
.awburst('0),
|
||
|
|
.awsize('0),
|
||
|
|
|
||
|
|
.wdata('0),
|
||
|
|
.wstrb('0),
|
||
|
|
.wvalid(1'b0),
|
||
|
|
.wready(),
|
||
|
|
|
||
|
|
.bvalid(),
|
||
|
|
.bready(1'b0),
|
||
|
|
.bresp(),
|
||
|
|
.bid()
|
||
|
|
);
|
||
|
|
|
||
|
|
defparam lmem.TAGW =`RV_LSU_BUS_TAG;
|
||
|
|
|
||
|
|
//axi_slv #(.TAGW(`RV_LSU_BUS_TAG)) lmem(
|
||
|
|
axi_slv lmem(
|
||
|
|
.aclk(core_clk),
|
||
|
|
.rst_l(rst_l),
|
||
|
|
.arvalid(lsu_axi_arvalid),
|
||
|
|
.arready(lsu_axi_arready),
|
||
|
|
.araddr(lsu_axi_araddr),
|
||
|
|
.arid(lsu_axi_arid),
|
||
|
|
.arlen(lsu_axi_arlen),
|
||
|
|
.arburst(lsu_axi_arburst),
|
||
|
|
.arsize(lsu_axi_arsize),
|
||
|
|
|
||
|
|
.rvalid(lsu_axi_rvalid),
|
||
|
|
.rready(lsu_axi_rready),
|
||
|
|
.rdata(lsu_axi_rdata),
|
||
|
|
.rresp(lsu_axi_rresp),
|
||
|
|
.rid(lsu_axi_rid),
|
||
|
|
.rlast(lsu_axi_rlast),
|
||
|
|
|
||
|
|
.awvalid(lsu_axi_awvalid),
|
||
|
|
.awready(lsu_axi_awready),
|
||
|
|
.awaddr(lsu_axi_awaddr),
|
||
|
|
.awid(lsu_axi_awid),
|
||
|
|
.awlen(lsu_axi_awlen),
|
||
|
|
.awburst(lsu_axi_awburst),
|
||
|
|
.awsize(lsu_axi_awsize),
|
||
|
|
|
||
|
|
.wdata(lsu_axi_wdata),
|
||
|
|
.wstrb(lsu_axi_wstrb),
|
||
|
|
.wvalid(lsu_axi_wvalid),
|
||
|
|
.wready(lsu_axi_wready),
|
||
|
|
|
||
|
|
.bvalid(lsu_axi_bvalid),
|
||
|
|
.bready(lsu_axi_bready),
|
||
|
|
.bresp(lsu_axi_bresp),
|
||
|
|
.bid(lsu_axi_bid)
|
||
|
|
);
|
||
|
|
`endif
|
||
|
|
|
||
|
|
|
||
|
|
task preload_dccm;
|
||
|
|
bit[31:0] data;
|
||
|
|
bit[31:0] addr, eaddr;
|
||
|
|
int adr;
|
||
|
|
|
||
|
|
addr = 'hfff8;
|
||
|
|
eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
||
|
|
if (eaddr != `RV_DCCM_SADR) return;
|
||
|
|
addr = 'hfffc;
|
||
|
|
eaddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
|
||
|
|
$display("DCCM pre-load from %h to %h", `RV_DCCM_SADR, eaddr);
|
||
|
|
|
||
|
|
for(addr=`RV_DCCM_SADR; addr <= eaddr; addr+=4) begin
|
||
|
|
adr = addr & 'hffff;
|
||
|
|
data = {lmem.mem[adr+3],lmem.mem[adr+2],lmem.mem[adr+1],lmem.mem[adr]};
|
||
|
|
slam_dccm_ram(addr, data == 0 ? 0 : {riscv_ecc32(data),data});
|
||
|
|
end
|
||
|
|
|
||
|
|
endtask
|
||
|
|
|
||
|
|
`ifdef VERILATOR
|
||
|
|
`define DRAM(bank) rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].ram.ram_core
|
||
|
|
`else
|
||
|
|
`define DRAM(bank) rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm.dccm_bank.ram_core
|
||
|
|
`endif
|
||
|
|
|
||
|
|
task slam_dccm_ram(input [31:0] addr, input[38:0] data);
|
||
|
|
int bank, indx;
|
||
|
|
bank = get_dccm_bank(addr, indx);
|
||
|
|
//`ifndef VERILATOR
|
||
|
|
case(bank)
|
||
|
|
0: `DRAM(0)[indx] = data;
|
||
|
|
1: `DRAM(1)[indx] = data;
|
||
|
|
`ifdef RV_DCCM_NUM_BANKS_4
|
||
|
|
2: `DRAM(2)[indx] = data;
|
||
|
|
3: `DRAM(3)[indx] = data;
|
||
|
|
`endif
|
||
|
|
`ifdef RV_DCCM_NUM_BANKS_8
|
||
|
|
2: `DRAM(2)[indx] = data;
|
||
|
|
3: `DRAM(3)[indx] = data;
|
||
|
|
4: `DRAM(4)[indx] = data;
|
||
|
|
5: `DRAM(5)[indx] = data;
|
||
|
|
6: `DRAM(6)[indx] = data;
|
||
|
|
7: `DRAM(7)[indx] = data;
|
||
|
|
`endif
|
||
|
|
endcase
|
||
|
|
//`endif
|
||
|
|
endtask
|
||
|
|
|
||
|
|
|
||
|
|
function[6:0] riscv_ecc32(input[31:0] data);
|
||
|
|
reg[6:0] synd;
|
||
|
|
synd[0] = ^(data & 32'h56aa_ad5b);
|
||
|
|
synd[1] = ^(data & 32'h9b33_366d);
|
||
|
|
synd[2] = ^(data & 32'he3c3_c78e);
|
||
|
|
synd[3] = ^(data & 32'h03fc_07f0);
|
||
|
|
synd[4] = ^(data & 32'h03ff_f800);
|
||
|
|
synd[5] = ^(data & 32'hfc00_0000);
|
||
|
|
synd[6] = ^{data, synd[5:0]};
|
||
|
|
return synd;
|
||
|
|
endfunction
|
||
|
|
|
||
|
|
function int get_dccm_bank(input int addr, output int bank_idx);
|
||
|
|
`ifdef RV_DCCM_NUM_BANKS_2
|
||
|
|
bank_idx = int'(addr[`RV_DCCM_BITS-1:3]);
|
||
|
|
return int'( addr[2]);
|
||
|
|
`elsif RV_DCCM_NUM_BANKS_4
|
||
|
|
bank_idx = int'(addr[`RV_DCCM_BITS-1:4]);
|
||
|
|
return int'(addr[3:2]);
|
||
|
|
`elsif RV_DCCM_NUM_BANKS_8
|
||
|
|
bank_idx = int'(addr[`RV_DCCM_BITS-1:5]);
|
||
|
|
return int'( addr[4:2]);
|
||
|
|
`endif
|
||
|
|
endfunction
|
||
|
|
|
||
|
|
endmodule
|