66 lines
1.5 KiB
C++
66 lines
1.5 KiB
C++
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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#include <stdlib.h>
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#include <iostream>
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#include <utility>
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#include <string>
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#include "Vsoc_sim.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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vluint64_t main_time = 0;
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double sc_time_stamp () {
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return main_time;
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}
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int main(int argc, char** argv) {
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std::cout << "\nVerilatorTB: Start of sim\n" << std::endl;
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Verilated::commandArgs(argc, argv);
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Vsoc_sim* soc = new Vsoc_sim;
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// init trace dump
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VerilatedVcdC* tfp = NULL;
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#if VM_TRACE
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Verilated::traceEverOn(true);
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tfp = new VerilatedVcdC;
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soc->trace (tfp, 24);
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tfp->open ("sim.vcd");
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#endif
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// Simulate
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while(!Verilated::gotFinish()){
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#if VM_TRACE
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tfp->dump (main_time);
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#endif
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main_time += 5;
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soc->core_clk = !soc->core_clk;
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soc->eval();
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}
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#if VM_TRACE
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tfp->close();
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#endif
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std::cout << "\nVerilatorTB: End of sim" << std::endl;
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exit(EXIT_SUCCESS);
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}
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