From 025a720e35bb779c889d2c959233e1739eccbcf4 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Thu, 24 Sep 2020 16:16:03 +0200
Subject: [PATCH] Fix non-blocking assignment in mem_lib.sv

A typo in mem_lib.sv caused suboptimal mapping which led to high
resource usage on FPGA targets.
---
 design/lib/mem_lib.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/design/lib/mem_lib.sv b/design/lib/mem_lib.sv
index e741c61..00702ea 100644
--- a/design/lib/mem_lib.sv
+++ b/design/lib/mem_lib.sv
@@ -28,7 +28,7 @@ module ram_``depth``x``width(               \
 reg [(width-1):0] ram_core [(depth-1):0];   \
                                             \
 always @(posedge CLK) begin              \
-   if (ME && WE) ram_core[ADR] = D;        \
+   if (ME && WE) ram_core[ADR] <= D;        \
    if (ME && ~WE) Q <= ram_core[ADR];       \
 end                                         \
                                             \