diff --git a/soc/ahb_sif.sv b/soc/ahb_sif.sv
index a80b50c..e6d85e1 100644
--- a/soc/ahb_sif.sv
+++ b/soc/ahb_sif.sv
@@ -53,58 +53,186 @@ module axi_slv #(
     output reg [TAGW-1:0] bid
 );
 
-  parameter MEM_DEPTH = 15;  // memory size = 0x8000 = 32k
+  parameter MEM_DEPTH = 15;  // memory size = 0x8000 = 32k WIDTH=15
+  parameter MEM_DEPTH_EACH = MEM_DEPTH - 3;  // memory size = 0x8000 = 32k WIDTH=15
 
-  bit [7:0] mem[(1<<MEM_DEPTH)-1:0];
+  bit [7:0] mem0[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem1[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem2[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem3[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem4[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem5[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem6[(1<<MEM_DEPTH_EACH)-1:0];
+  bit [7:0] mem7[(1<<MEM_DEPTH_EACH)-1:0];
 
   bit [63:0] memdata;
 
-  wire [MEM_DEPTH-1:0] saraddr = araddr[MEM_DEPTH-1:0];
-  wire [MEM_DEPTH-1:0] sawaddr = awaddr[MEM_DEPTH-1:0];
+  wire [MEM_DEPTH-4:0] saraddr0 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h0 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] saraddr1 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h1 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] saraddr2 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h2 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] saraddr3 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h3 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] saraddr4 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h4 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] saraddr5 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h5 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] saraddr6 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h6 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] saraddr7 = araddr[MEM_DEPTH - 1:3];
 
+  wire [7:0] rm0 = mem0[saraddr0];
+  wire [7:0] rm1 = mem1[saraddr1];
+  wire [7:0] rm2 = mem2[saraddr2];
+  wire [7:0] rm3 = mem3[saraddr3];
+  wire [7:0] rm4 = mem4[saraddr4];
+  wire [7:0] rm5 = mem5[saraddr5];
+  wire [7:0] rm6 = mem6[saraddr6];
+  wire [7:0] rm7 = mem7[saraddr7];
+
+  wire [MEM_DEPTH-4:0] sawaddr0 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 0 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] sawaddr1 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 1 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] sawaddr2 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 2 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] sawaddr3 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 3 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] sawaddr4 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 4 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] sawaddr5 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 5 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] sawaddr6 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 6 ? 1 : 0);
+  wire [MEM_DEPTH-4:0] sawaddr7 = awaddr[MEM_DEPTH - 1:3];
+
+  initial begin
+    mem0[0] = 8'h63;
+    mem1[0] = 8'h0;
+    mem2[0] = 8'h0;
+    mem3[0] = 8'h0;
+  end
   always @(posedge aclk or negedge rst_l) begin
     if (!rst_l) begin
       rvalid <= 0;
       bvalid <= 0;
     end else begin
-      bid    <= awid;
-      rid    <= arid;
+      bid <= awid;
+      rid <= arid;
       rvalid <= arvalid;
       bvalid <= awvalid;
-      rdata  <= memdata;
+      rdata <= memdata;
     end
   end
 
   always @(negedge aclk) begin
     if (arvalid)
-      memdata <= {
-        mem[saraddr+7],
-        mem[saraddr+6],
-        mem[saraddr+5],
-        mem[saraddr+4],
-        mem[saraddr+3],
-        mem[saraddr+2],
-        mem[saraddr+1],
-        mem[saraddr]
-      };
+      case (araddr[2:0])
+        3'h0: begin
+          memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
+        end
+        3'h1: begin
+          memdata <= {rm0, rm7, rm6, rm5, rm4, rm3, rm2, rm1};
+        end
+        3'h2: begin
+          memdata <= {rm1, rm0, rm7, rm6, rm5, rm4, rm3, rm2};
+        end
+        3'h3: begin
+          memdata <= {rm2, rm1, rm0, rm7, rm6, rm5, rm4, rm3};
+        end
+        3'h4: begin
+          memdata <= {rm3, rm2, rm1, rm0, rm7, rm6, rm5, rm4};
+        end
+        3'h5: begin
+          memdata <= {rm4, rm3, rm2, rm1, rm0, rm7, rm6, rm5};
+        end
+        3'h6: begin
+          memdata <= {rm5, rm4, rm3, rm2, rm1, rm0, rm7, rm6};
+        end
+        3'h7: begin
+          memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
+        end
+      endcase
+
     if (awvalid) begin
-      if (wstrb[7]) mem[sawaddr+7] = wdata[63:56];
-      if (wstrb[6]) mem[sawaddr+6] = wdata[55:48];
-      if (wstrb[5]) mem[sawaddr+5] = wdata[47:40];
-      if (wstrb[4]) mem[sawaddr+4] = wdata[39:32];
-      if (wstrb[3]) mem[sawaddr+3] = wdata[31:24];
-      if (wstrb[2]) mem[sawaddr+2] = wdata[23:16];
-      if (wstrb[1]) mem[sawaddr+1] = wdata[15:08];
-      if (wstrb[0]) mem[sawaddr+0] = wdata[07:00];
+      case (awaddr[2:0])
+        3'h0: begin
+          if (wstrb[7]) mem7[sawaddr7] = wdata[63:56];
+          if (wstrb[6]) mem6[sawaddr6] = wdata[55:48];
+          if (wstrb[5]) mem5[sawaddr5] = wdata[47:40];
+          if (wstrb[4]) mem4[sawaddr4] = wdata[39:32];
+          if (wstrb[3]) mem3[sawaddr3] = wdata[31:24];
+          if (wstrb[2]) mem2[sawaddr2] = wdata[23:16];
+          if (wstrb[1]) mem1[sawaddr1] = wdata[15:08];
+          if (wstrb[0]) mem0[sawaddr0] = wdata[07:00];
+        end
+        3'h1: begin
+          if (wstrb[7]) mem0[sawaddr0] = wdata[63:56];
+          if (wstrb[6]) mem7[sawaddr7] = wdata[55:48];
+          if (wstrb[5]) mem6[sawaddr6] = wdata[47:40];
+          if (wstrb[4]) mem5[sawaddr5] = wdata[39:32];
+          if (wstrb[3]) mem4[sawaddr4] = wdata[31:24];
+          if (wstrb[2]) mem3[sawaddr3] = wdata[23:16];
+          if (wstrb[1]) mem2[sawaddr2] = wdata[15:08];
+          if (wstrb[0]) mem1[sawaddr1] = wdata[07:00];
+        end
+        3'h2: begin
+          if (wstrb[7]) mem1[sawaddr1] = wdata[63:56];
+          if (wstrb[6]) mem0[sawaddr0] = wdata[55:48];
+          if (wstrb[5]) mem7[sawaddr7] = wdata[47:40];
+          if (wstrb[4]) mem6[sawaddr6] = wdata[39:32];
+          if (wstrb[3]) mem5[sawaddr5] = wdata[31:24];
+          if (wstrb[2]) mem4[sawaddr4] = wdata[23:16];
+          if (wstrb[1]) mem3[sawaddr3] = wdata[15:08];
+          if (wstrb[0]) mem2[sawaddr2] = wdata[07:00];
+        end
+        3'h3: begin
+          if (wstrb[7]) mem2[sawaddr2] = wdata[63:56];
+          if (wstrb[6]) mem1[sawaddr1] = wdata[55:48];
+          if (wstrb[5]) mem0[sawaddr0] = wdata[47:40];
+          if (wstrb[4]) mem7[sawaddr7] = wdata[39:32];
+          if (wstrb[3]) mem6[sawaddr6] = wdata[31:24];
+          if (wstrb[2]) mem5[sawaddr5] = wdata[23:16];
+          if (wstrb[1]) mem4[sawaddr4] = wdata[15:08];
+          if (wstrb[0]) mem3[sawaddr3] = wdata[07:00];
+        end
+        3'h4: begin
+          if (wstrb[7]) mem3[sawaddr3] = wdata[63:56];
+          if (wstrb[6]) mem2[sawaddr2] = wdata[55:48];
+          if (wstrb[5]) mem1[sawaddr1] = wdata[47:40];
+          if (wstrb[4]) mem0[sawaddr0] = wdata[39:32];
+          if (wstrb[3]) mem7[sawaddr7] = wdata[31:24];
+          if (wstrb[2]) mem6[sawaddr6] = wdata[23:16];
+          if (wstrb[1]) mem5[sawaddr5] = wdata[15:08];
+          if (wstrb[0]) mem4[sawaddr4] = wdata[07:00];
+        end
+        3'h5: begin
+          if (wstrb[7]) mem4[sawaddr4] = wdata[63:56];
+          if (wstrb[6]) mem3[sawaddr3] = wdata[55:48];
+          if (wstrb[5]) mem2[sawaddr2] = wdata[47:40];
+          if (wstrb[4]) mem1[sawaddr1] = wdata[39:32];
+          if (wstrb[3]) mem0[sawaddr0] = wdata[31:24];
+          if (wstrb[2]) mem7[sawaddr7] = wdata[23:16];
+          if (wstrb[1]) mem6[sawaddr6] = wdata[15:08];
+          if (wstrb[0]) mem5[sawaddr5] = wdata[07:00];
+        end
+        3'h6: begin
+          if (wstrb[7]) mem5[sawaddr5] = wdata[63:56];
+          if (wstrb[6]) mem4[sawaddr4] = wdata[55:48];
+          if (wstrb[5]) mem3[sawaddr3] = wdata[47:40];
+          if (wstrb[4]) mem2[sawaddr2] = wdata[39:32];
+          if (wstrb[3]) mem1[sawaddr1] = wdata[31:24];
+          if (wstrb[2]) mem0[sawaddr0] = wdata[23:16];
+          if (wstrb[1]) mem7[sawaddr7] = wdata[15:08];
+          if (wstrb[0]) mem6[sawaddr6] = wdata[07:00];
+        end
+        3'h7: begin
+          if (wstrb[7]) mem6[sawaddr6] = wdata[63:56];
+          if (wstrb[6]) mem5[sawaddr5] = wdata[55:48];
+          if (wstrb[5]) mem4[sawaddr4] = wdata[47:40];
+          if (wstrb[4]) mem3[sawaddr3] = wdata[39:32];
+          if (wstrb[3]) mem2[sawaddr2] = wdata[31:24];
+          if (wstrb[2]) mem1[sawaddr1] = wdata[23:16];
+          if (wstrb[1]) mem0[sawaddr0] = wdata[15:08];
+          if (wstrb[0]) mem7[sawaddr7] = wdata[07:00];
+        end
+      endcase
     end
   end
 
-
   assign arready = 1'b1;
   assign awready = 1'b1;
-  assign wready  = 1'b1;
-  assign rresp   = 2'b0;
-  assign bresp   = 2'b0;
-  assign rlast   = 1'b1;
+  assign wready = 1'b1;
+  assign rresp = 2'b0;
+  assign bresp = 2'b0;
+  assign rlast = 1'b1;
 
 endmodule
diff --git a/soc/soc_sim.sv b/soc/soc_sim.sv
index 750bf89..0171675 100644
--- a/soc/soc_sim.sv
+++ b/soc/soc_sim.sv
@@ -18,25 +18,25 @@ module soc_sim (
     input bit core_clk
 );
 
-  logic         rst_l;
-  logic         dbg_rst_l;
+  logic rst_l;
+  logic dbg_rst_l;
 
-  wire          jtag_tdo;
-  wire          jtag_tck;
-  wire          jtag_tms;
-  wire          jtag_tdi;
-  wire          jtag_trst_n;
+  wire jtag_tdo;
+  wire jtag_tck;
+  wire jtag_tms;
+  wire jtag_tdi;
+  wire jtag_trst_n;
 
-  bit    [31:0] cycleCnt;
-  logic         mailbox_data_val;
-  int           commit_count;
+  bit [31:0] cycleCnt;
+  logic mailbox_data_val;
+  int commit_count;
 
-  logic         wb_valid;
-  logic  [ 4:0] wb_dest;
-  logic  [31:0] wb_data;
+  logic wb_valid;
+  logic [4:0] wb_dest;
+  logic [31:0] wb_data;
 
-  wire   [63:0] WriteData;
-  string        abi_reg          [32];  // ABI register names
+  wire [63:0] WriteData;
+  string abi_reg[32];  // ABI register names
 
   assign WriteData = rvsoc.lsu_axi_wdata;
   assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
@@ -130,6 +130,8 @@ module soc_sim (
     end
   end
 
+  reg [7:0] hex[(1<<rvsoc.imem.MEM_DEPTH)-1:0];
+
   initial begin
     abi_reg[0] = "zero";
     abi_reg[1] = "ra";
@@ -170,22 +172,45 @@ module soc_sim (
     fd = $fopen("console.log", "w");
     commit_count = 0;
 
-    $readmemh("program.hex", rvsoc.lmem.mem);
-    $readmemh("program.hex", rvsoc.imem.mem);
+    $readmemh("program.hex", hex);
+    for (
+        reg [rvsoc.imem.MEM_DEPTH-1:0] i = 0; i < (1 << (rvsoc.imem.MEM_DEPTH - 3)); i++
+    ) begin
+      rvsoc.imem.mem0[i] = hex[(i << 3) + 0];
+      rvsoc.imem.mem1[i] = hex[(i << 3) + 1];
+      rvsoc.imem.mem2[i] = hex[(i << 3) + 2];
+      rvsoc.imem.mem3[i] = hex[(i << 3) + 3];
+      rvsoc.imem.mem4[i] = hex[(i << 3) + 4];
+      rvsoc.imem.mem5[i] = hex[(i << 3) + 5];
+      rvsoc.imem.mem6[i] = hex[(i << 3) + 6];
+      rvsoc.imem.mem7[i] = hex[(i << 3) + 7];
+    end
+    for (
+        reg [rvsoc.lmem.MEM_DEPTH-1:0] i = 0; i < (1 << (rvsoc.lmem.MEM_DEPTH - 3)); i++
+    ) begin
+      rvsoc.lmem.mem0[i] = hex[(i << 3) + 0];
+      rvsoc.lmem.mem1[i] = hex[(i << 3) + 1];
+      rvsoc.lmem.mem2[i] = hex[(i << 3) + 2];
+      rvsoc.lmem.mem3[i] = hex[(i << 3) + 3];
+      rvsoc.lmem.mem4[i] = hex[(i << 3) + 4];
+      rvsoc.lmem.mem5[i] = hex[(i << 3) + 5];
+      rvsoc.lmem.mem6[i] = hex[(i << 3) + 6];
+      rvsoc.lmem.mem7[i] = hex[(i << 3) + 7];
+    end
   end
 
   assign rst_l = cycleCnt > 20;
   assign dbg_rst_l = cycleCnt > 10;
 
   soc_top rvsoc (
-      .clk(core_clk),
-      .rst(rst_l),
+      .clk    (core_clk),
+      .rst    (rst_l),
       .dbg_rst(dbg_rst_l),
 
-      .jtag_tdo(jtag_tdo),
-      .jtag_tck(jtag_tck),
-      .jtag_tms(jtag_tms),
-      .jtag_tdi(jtag_tdi),
+      .jtag_tdo   (jtag_tdo),
+      .jtag_tck   (jtag_tck),
+      .jtag_tms   (jtag_tms),
+      .jtag_tdi   (jtag_tdi),
       .jtag_trst_n(jtag_trst_n)
   );
 
@@ -193,10 +218,10 @@ module soc_sim (
       .clk_i (core_clk),
       .rst_ni(rst_l),
 
-      .jtag_tck(jtag_tck),
-      .jtag_tms(jtag_tms),
-      .jtag_tdi(jtag_tdi),
-      .jtag_tdo(jtag_tdo),
+      .jtag_tck   (jtag_tck),
+      .jtag_tms   (jtag_tms),
+      .jtag_tdi   (jtag_tdi),
+      .jtag_tdo   (jtag_tdo),
       .jtag_trst_n(jtag_trst_n),
       .jtag_srst_n()
   );